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# Date Author Comment
97129ac8 03/14/2012 11:20 pm Andreas Färber

target-xtensa: Don't overuse CPUState

Scripted conversion:
sed -i "s/CPUState/CPUXtensaState/g" target-xtensa/*.[hc]
sed -i "s/#define CPUXtensaState/#define CPUState/" target-xtensa/cpu.h

Signed-off-by: Andreas Färber <>
Acked-by: Anthony Liguori <>
f14c4b5f 02/20/2012 06:07 pm Max Filippov

target-xtensa: add DBREAK data breakpoints

Add DBREAKA/DBREAKC SRs and implement DBREAK breakpoints as debug
watchpoints.

This implementation is not fully compliant to ISA: when a breakpoint is
set to an unmapped/inaccessible memory address it generates TLB/memory...
e61dc8f7 02/18/2012 12:55 pm Max Filippov

target-xtensa: implement instruction breakpoints

Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK and
BREAK.N instructions and IBREAK breakpoints.

IBREAK breakpoint address is considered constant for TB lifetime.
On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated....
890c6333 10/16/2011 12:03 am Max Filippov

target-xtensa: fix guest hang on masked CCOMPARE interrupt

QEMU timer is used to post CCOMPARE interrupt when the core is halted.
If that CCOMPARE interrupt is masked off then the timer must be rearmed
in the callback, otherwise it will be rearmed next time the core goes to...
bccd9ec5 10/01/2011 12:31 pm Blue Swirl

softmmu_header: pass CPUState to tlb_fill

Pass CPUState pointer to tlb_fill() instead of architecture local
cpu_single_env hacks.

Signed-off-by: Blue Swirl <>
b67ea0cd 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement memory protection options

- TLB opcode group;
- region protection option (ISA, 4.6.3);
- region translation option (ISA, 4.6.4);
- MMU option (ISA, 4.6.5).

Cache control attribute bits are not used by this implementation.

Signed-off-by: Max Filippov <>...
553e44f9 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement windowed registers

See ISA, 4.7.1 for details.

Physical registers and currently visible window are separate fields in
CPUEnv. Only current window is accessible to TCG. On operations that
change window base helpers copy current window to and from physical...
797d780b 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement loop option

See ISA, 4.3.2 for details.

Operations that change LEND SR value invalidate TBs at the old and at
the new LEND. LEND value at TB compilation time is considered constant
and loop instruction is generated based on this value....
5b4e481b 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement unaligned exception option

See ISA, 4.4.4 for details.

Correct (aligned as per ISA) address for unaligned access is generated
in case this option is not enabled.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
b994e91b 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement interrupt option

See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt
option) and 4.4.8 (timer interrupt option) for details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
3580ecad 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement shifts (ST1 and RST1 groups)

- ST1: SAR (shift amount special register) manipulation, NSA;
- RST1: shifts, 16-bit multiplication.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
40643d7c 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement exceptions

- mark privileged opcodes with ring check;
- make debug exception on exception handler entry.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
2328826b 09/10/2011 07:57 pm Max Filippov

target-xtensa: add target stubs

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
dedc5eae 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement disas_xtensa_insn

Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.

Implement code generation loop with single step/breakpoint checking.

Signed-off-by: Max Filippov <>...