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exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target-i386: Use define for cpuid vendor string size
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386/cpu: Name new CPUID bits
Update QEMU's knowledge of CPUID bit names. This allows toenable/disable those new features on QEMU's command line whenusing KVM and prepares future feature enablement in QEMU.
This adds F16C, RDRAND, LWP, TBM, TopoExt, PerfCtr_Core, PerfCtr_NB,...
target-i386: Pass X86CPU to cpu_x86_inject_mce()
Needed for changing run_on_cpu() argument to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
cpus: Pass CPUState to [qemu_]cpu_has_work()
For target-mips also change the return type to bool.
Make include paths for cpu-qom.h consistent for alpha and unicore32.
Signed-off-by: Andreas Färber <afaerber@suse.de>[AF: Updated new target-openrisc function accordingly]...
target-i386: Pass X86CPU to cpu_x86_load_seg_cache_sipi()
Simplifies the call in apic_sipi() again and needed for moving haltedfield to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Igor Mammedov <imammedo@redhat.com>
qemu: enable PV EOI for qemu 1.3
Enable KVM PV EOI by default. You can still disable it with-kvm_pv_eoi cpu flag. To avoid breaking cross-version migration,enable only for qemu 1.3 (or in the future, newer) machine type.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
cpu_dump_state: move DUMP_FPU and DUMP_CCOP flags from x86-only to generic
Move the DUMP_FPU and DUMP_CCOP flags for cpu_dump_state() from beingx86-specific flags to being generic ones. This allows us to drop someTARGET_I386 ifdefs in various places, and means that we can (potentially)...
x86: Implement SMEP and SMAP
This patch implements Supervisor Mode Execution Prevention (SMEP) andSupervisor Mode Access Prevention (SMAP) for x86. The purpose of thepatch, obviously, is to help kernel developers debug the support forthose features....
i386: kvm: use a #define for the set of alias feature bits
Instea of using a hardcoded hex constant, define CPUID_EXT2_AMD_ALIASESas the set of CPUID[8000_0001].EDX bits that on AMD are the same as thebits of CPUID1.EDX.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>...
Drop cpu_list_id macro
Since the only user of the extended cpu_list_id() formatwas the x86 ?model/?dump/?cpuid output, we can drop itcompletely.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>...
target-i386: Add missing CPUID_* constants
Those constants will be used by new CPU model definitions.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Reviewed-by: Igor Mammedov <imammedo@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
kvm: get/set PV EOI MSR
Support get/set of new PV EOI MSR, for migration.Add an optional section for MSR value - send itout in case MSR was changed from the default value (0).
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Merge branch 'x86cpu_qom_tcg_v2' of git://github.com/imammedo/qemu
apic: Defer interrupt updates to VCPU thread
KVM performs TPR raising asynchronously to QEMU, specifically outsideQEMU's global lock. When an interrupt is injected into the APIC and TPRis checked to decide if this can be delivered, a stale TPR value may be...
kvm: expose tsc deadline timer feature to guest
This patch exposes tsc deadline timer feature to guest if1). in-kernel irqchip is used, and2). kvm has emulated tsc deadline timer, and3). user authorize the feature exposing via cpu or +/ tsc-deadline...
x86: split off SVM helpers
Move SVM helpers to svm_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
x86: avoid AREG0 for exceptions
Add an explicit CPUX86State parameter instead of relying on AREG0.
Merge raise_exception_env() to raise_exception(), likewise withraise_exception_err_env() and raise_exception_err().
Introduce cpu_svm_check_intercept_param() and cpu_vmexit()...
x86: split off exception handlers
Move exception handlers from op_helper.c to excp_helper.c.
x86: split off condition code helpers
Move condition code helpers to cc_helper.c.
Move the shared inline functions lshift(), cpu_load_eflags() andcpu_cc_compute_all() to cpu.h.
target-i386: move tcg initialization into x86_cpu_initfn()
In order to make cpu object not depended on external ad-hocinitialization routines, move tcg initialization from cpu_x86_initinside cpu object "x86_cpu_initfn()".
Signed-off-by: Igor Mammedov <imammedo@redhat.com>...
target-i386: Pass X86CPU to do_cpu_{init,sipi}()
Allows to use cpu_reset() in place of cpu_state_reset().
target-i386: Let cpu_x86_init() return X86CPU
Turn cpu_init macro into a static inline function returning CPUX86Statefor backwards compatibility.
Expose CPUID leaf 7 only for -cpu host
Changes v2 -> v3; - Check for kvm_enabled() before setting cpuid_7_0_ebx_features
Changes v1 -> v2: - Use kvm_arch_get_supported_cpuid() instead of host_cpuid() on cpu_x86_fill_host().
We should use GET_SUPPORTED_CPUID for all bits on "-cpu host"...
target-i386: Pass X86CPU to cpu_x86_register()
Avoids an x86_env_get_cpu() call there, to work with QOM properties.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>Reviewed-by: Igor Mammedov <imammedo@redhat.com>
target-i386: QOM'ify CPU
Embed CPUX86State as first member of X86CPU.Distinguish between "x86_64-cpu" and "i386-cpu".Drop cpu_x86_close() in favor of calling object_delete() directly.
For now let CPUClass::reset() call cpu_state_reset().
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
target-i386: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUX86State/g" target-i386/*.[hc] sed -i "s/#define CPUX86State/#define CPUState/" target-i386/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
target-i386: Mask NX bit from cpu_get_phys_page_debug result
This was a long pending bug, now revealed by the assert inphys_page_find that stumbled over the large page index returned bycpu_get_phys_page_debug for NX-marked pages: We need to mask out NX and...
target-i386: Add infrastructure for reporting TPR MMIO accesses
This will allow the APIC core to file a TPR access report. Depending onthe accelerator and kernel irqchip mode, it will either be deliveredright away or queued for later reporting.
In TCG mode, we can restart the triggering instruction and can therefore...
kvm: x86: Avoid runtime allocation of xsave buffer
Keep a per-VCPU xsave buffer for kvm_put/get_xsave instead ofcontinuously allocating and freeing it on state sync.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
i386: wire up MSR_IA32_MISC_ENABLE
It's needed for its default value - bit 0 specifies that "rep movs" isgood enough for memcpy, and Linux may use a slower memcpu if it is not set,depending on cpu family/model.
Signed-off-by: Avi Kivity <avi@redhat.com>...
kvm: support TSC deadline MSR with subsection
KVM add emulation of lapic tsc deadline timer for guest.This patch is co-operation work at qemu side.
Use subsections to save/restore the field (mtosatti).
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>...
Revert "kvm: support TSC deadline MSR"
This reverts commit bfc2455ddbb41148494a084d15777e6bed7533c3.New patch with subsections will follow.
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
kvm: support TSC deadline MSR
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
target-i386: Remove data type CCTable
Remove also two assert statements which were the last remaining users.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Merge remote-tracking branch 'qemu-kvm/uq/master' into staging
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
qemu-x86: Add tsc_freq option to -cpu
To let the user configure the desired tsc frequency for theguest if running in KVM.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This isneeded by later patches.
x86: use caller supplied CPUState for interrupt related stuff
Several x86 specific functions are called from cpu-exec.c with theassumption that global env register is valid. This will be changedlater, so make the functions use caller supplied CPUState parameter....
kvm: x86: Save/restore FPU OP, IP and DP
These FPU states are properly maintained by KVM but not yet by TCG. Sofar we unconditionally set them to 0 in the guest which may causestate corruptions, though not with modern guests.
To avoid breaking backward migration, use a conditional subsection that...
kvm: Add CPUID support for VIA CPU
When KVM is running on VIA CPU with host cpu's model, thefeautures of VIA CPU will be passed into kvm guest by callingthe CPUID instruction for Centaur.
Signed-off-by: BrillyWu<brillywu@viatech.com.cn>Signed-off-by: KaryJin<karyjin@viatech.com.cn>...
target-i386: remove old code handling float64
Now that target-i386 uses softfloat, floatx80 is always available andthere is no need anymore to have code handling both float64 and floax80.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
irq: Privatize CPU_INTERRUPT_NMI.
This interrupt name is used by i386, CRIS, and MicroBlaze.Copy the name into each target.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-i386: Privatize some i386-specific interrupt names.
SMI, VIRQ, INIT, SIPI, and MCE are all only used by the i386 port.
x86: Properly reset PAT MSR
Conforming to the Intel spec, set the power-on value of PAT also onreset, but save it across INIT.
x86: Perform implicit mcg_status reset
Reorder mcg_status in CPUState to achieve automatic clearing on reset.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>CC: Huang Ying <ying.huang@intel.com>CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>CC: Jin Dongming <jin.dongming@np.css.fujitsu.com>...
x86: Small cleanups of MCE helpers
Fix some code style issues, use proper headers, and align to cpu_x86naming scheme. No functional changes.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>CC: Huang Ying <ying.huang@intel.com>CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>...
x86: Refine error reporting of MCE injection services
As this service is used by the human monitor, make sure that errors getreported to the right channel, and also raise the verbosity.
This requires to move Monitor typedef in qemu-common.h to resolve the...
x86: Optionally avoid injecting AO MCEs while others are pending
Allow to tell cpu_x86_inject_mce that it should ignore Action OptionalMCE events when the target VCPU is still processing another one. Thiswill be used by KVM soon.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
kvm: make tsc stable over migration and machine start
If the machine is stopped, we should not record two different tsc valuesupon a save operation. The same problem happens with kvmclock.
But kvmclock is taking a different diretion, being now seen as a separate...
kvm: x86: Implicitly clear nmi_injected/pending on reset
All CPUX86State variables before CPU_COMMON are automatically cleared onreset. Reorder nmi_injected and nmi_pending to avoid having to touchthem explicitly.
kvm: Improve reporting of fatal errors
Report KVM_EXIT_UNKNOWN, KVM_EXIT_FAIL_ENTRY, and KVM_EXIT_EXCEPTIONwith more details to stderr. The latter two are so far x86-only, so movethem into the arch-specific handler. Integrate the Intel real modewarning on KVM_EXIT_FAIL_ENTRY that qemu-kvm carries, but actually...
Add function for checking mca broadcast of CPU
Add function for checking whether current CPU support mca broadcast.
Signed-off-by: Jin Dongming <jin.dongming@np.css.fujitsu.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
target-i386: Fix accidental use of SoftFloat uint64 type
softfloat.h's uint64 type has least-width semantics.Use uint64_t instead since that is used in helpers.
Signed-off-by: Andreas Färber <andreas.faerber@web.de>...
Add support for async page fault to qemu
Add save/restore of MSR for migration and cpuid bit.
Signed-off-by: Gleb Natapov <gleb@redhat.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
Add svm cpuid features
This patch adds the svm cpuid feature flags to the qemuintialization path. It also adds the svm features availableon phenom to its cpu-definition and extends the host cputype to support all svm features KVM can provide.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>...
MCE: Relay UCR MCE to guest
Port qemu-kvm's
commit 4b62fff1101a7ad77553147717a8bd3bf79df7efAuthor: Huang Ying <ying.huang@intel.com>Date: Mon Sep 21 10:43:25 2009 +0800
UCR (uncorrected recovery) MCE is supported in recent Intel CPUs,...
remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
move cpu_pc_from_tb to target-*/exec.h
kvm: Enable XSAVE live migration support
Signed-off-by: Sheng Yang <sheng@linux.intel.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
apic: qdev conversion cleanup
Make APICState completely private to apic.c by using DeviceStatein external APIs.
Move apic_init() to pc.c.
apic: avoid using CPUState internals
Move the actual CPUState contents handling to cpu.h and cpuid.c.
Handle CPU reset and set env->halted in pc.c.
Add a function to get the local APIC state of the currentCPU for the MMIO.
apic: avoid passing CPUState from CPU code
Pass only APICState when accessing APIC from CPU code.
x86/cpuid: move CPUID functions into separate file
about half of target-i386/helper.c consist of CPUID related functions.Only one of them is a real TCG helper function. So move the wholeCPUID stuff out of this into a separate file to get bettermaintainable parts....
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets otherthan Alpha. This will be used for page_find_alloc, which issupposed to be using virtual addresses in the first place....
Add cpu model configuration support..
This is a reimplementation of prior versions which addsthe ability to define cpu models for contemporary processors.The added models are likewise selected via -cpu <name>,and are intended to displace the existing convention...
Add KVM paravirt cpuid leaf
Initialize KVM paravirt cpuid leaf and allow user to control guestvisible PV features through -cpu flag.
Signed-off-by: Gleb Natapov <gleb@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
kvm: x86: Use separate exception_injected CPUState field
Marcelo correctly remarked that there are usage conflicts between QEMUcore code and KVM /wrt exception_index. So spend a separate field andalso save/restore it properly.
target-i386: Fix evaluation of DR7 register
hw_breakpoint_type and hw_breakpoint_len used the wrong index multiplierto extract type and len.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
v2: properly save kvm system time msr registers
Currently, the msrs involved in setting up pvclock are not saved overmigration and/or save/restore. This patch puts their value in specialfields in our CPUState, and deal with them using vmstate.
kvm also has to account for it, by including them in the msr list...
kvm: x86: Add support for VCPU event states
This patch extends the qemu-kvm state sync logic with support forKVM_GET/SET_VCPU_EVENTS, giving access to yet missing exception,interrupt and NMI states.
kvm: x86: Refactor use of interrupt_bitmap
Drop interrupt_bitmap from the cpustate and solely rely on the integerinterupt_injected. This prepares us for the new injected-interruptinterface, which will deprecate the bitmap, while preservingcompatibility....
target-i386: move recently added vmstate fields at the end of the structure
This reduce the impact on hosts that have addressing modes with limitedoffsets. Suggested by Laurent Desnogues.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
gdbstub: x86: Switch 64/32 bit registers dynamically
Commit 56aebc891674cd2d07b3f64183415697be200084 changed gdbstub in waythat debugging 32 or 16-bit guest code is no longer possible with qemufor x86_64 guest CPUs. Since that commit, qemu only provides registers...
x86: split FPReg union
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
x86: split MTRRVar union
x86: add fpregs_format_vmstate
Don't even ask, being able to load/save between 64<->80bit floats should be forbidden
x86: mce_banks always have the same size
mce_banks is always MCE_BANKS_DEF * 4 in size, value never change
CC: Huang Ying <ying.huang@intel.com>Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
x86: fpuc is uint16_t not unsigned int
x86: fpus is uint16_t not unsigned int
We save more that fpus on that 16 bits (fpstt), we need an additional field
x86: add fptag_vmstate to the state
It is needed to store fptags
x86: add pending_irq_vmstate to the state
It is needed to save the interrupt_bitmap
x86: make a20_mask int32_t
This makes the savevm code correct, and sign extensins gives us exactlywhat we need (namely, sign extend to 64 bits when used with 64bit addresess.
Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax....
target-i386: add RDTSCP support
RDTSCP reads the time stamp counter and atomically also the contentof a 32-bit MSR, which can be freely set by the OS. This allows CPUlocal data to be queried by userspace.Linux uses this to allow a fast implementation of the getcpu()...
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with afew minor variations. This patch sets up appropriate defaults for ageneric handle_cpu_signal and provides overrides for particular targets...
Unbreak large mem support by removing kqemu
kqemu introduces a number of restrictions on the i386 target. The worst is thatit prevents large memory from working in the default build.
Furthermore, kqemu is fundamentally flawed in a number of ways. It relies on...
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Update to a hopefully more future proof FSF address
gdbstub: x86: Support for setting segment registers
This allows to set segment registers via gdb also in system emulationmode. Basic sanity checks are applied and nothing is changed if theyfail. But screwing up the target via this interface will never be...
Make sure to mark MCE defines as ULL
Fixes build on 32-bit
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
QEMU: MCE: Add MCE simulation to qemu/tcg
- MCE features are initialized when VCPU is intialized according to CPUID.- A monitor command "mce" is added to inject a MCE.- A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE.
aliguori: fix build for linux-user...
preserve the hypervisor bit while KVM trims the CPUID bits
The KVM kernel will disable all bits in CPUID which are not present inthe host. As this is mostly true for the hypervisor bit (1.ecx),preserve its value before the trim and restore it afterwards....
Handle init/sipi in a main cpu exec loop. (v2)
This should fix compilation problem in case of CONFIG_USER_ONLY.
Currently INIT/SIPI is handled in the context of CPU that sends IPI.This patch changes this to handle them like all other events in a maincpu exec loop. When KVM will gain thread per vcpu capability it will...
allow CPUID vendor override
KVM-enabled QEMU will always report the vendor ID of the physical CPU it isrunning on. Allow to override this if explicitly requested on thecommand line. It will not suffice to name a CPU type (like -cpu phenom),but you have to explicitly set the vendor: -cpu phenom,vendor=AuthenticAMD...
x86: Add support for resume flag
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
kvm: x86: Save/restore KVM-specific CPU states
Save and restore all so far neglected KVM-specific CPU states. Handlingthe TSC stabilizes migration in KVM mode. The interrupt_bitmap andmp_state are currently unused, but will become relevant for in-kernel...