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Name Size
Makefile.objs 465 Bytes
arm-semi.c 17.2 kB
cpu-qom.h 6.2 kB
cpu.c 32.6 kB
cpu.h 42.5 kB
cpu64.c 3.6 kB
crypto_helper.c 13 kB
gdbstub.c 2.8 kB
gdbstub64.c 1.9 kB
helper-a64.c 7.5 kB
helper-a64.h 2 kB
helper.c 157.7 kB
helper.h 19 kB
iwmmxt_helper.c 24.8 kB
kvm-consts.h 4.4 kB
kvm-stub.c 437 Bytes
kvm.c 10.4 kB
kvm32.c 15.7 kB
kvm64.c 5.2 kB
kvm_arm.h 4.2 kB
machine.c 7.9 kB
neon_helper.c 53.2 kB
op_addsub.h 1.8 kB
op_helper.c 9 kB
translate-a64.c 283.7 kB
translate.c 378.5 kB
translate.h 1.9 kB

Latest revisions

# Date Author Comment
1ed69e82 02/26/2014 07:20 pm Peter Maydell

target-arm: A64: Implement WFI

Implement the WFI instruction for A64; this just involves wiring
up the instruction, and adding a gen_a64_set_pc_im() which was
accidentally omitted from the A64 decoder top loop.

Signed-off-by: Peter Maydell <>...
a7adc4b7 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 generic timers

Implement the AArch64 view of the generic timer system registers.

Signed-off-by: Peter Maydell <>
e60cef86 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 ID and feature registers

Implement the AArch64-specific ID and feature registers. Although
many of these are currently not used by the architecture (and so
always zero for all implementations), we define the full set of
fields in the ARMCPU struct for symmetry....
0b45451e 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 dummy breakpoint and watchpoint registers

In AArch64 the breakpoint and watchpoint registers are mandatory, so the
kernel always accesses them on bootup. Implement dummy versions, which
read as written but have no actual effect....
cd5c11b8 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI

Define a dummy version of the AArch64 OSLAR_EL1 system register
which just ignores writes. Linux will always write to this (it
is the OS lock used for debugging), but we don't support debug.

Signed-off-by: Peter Maydell <>...
d9ea7d29 02/26/2014 07:20 pm Peter Maydell

target-arm: Get MMU index information correct for A64 code

Emit the correct MMU index information for loads and stores from
A64 code, rather than hardwiring it to "always kernel mode",
by storing the exception level in the TB flags, and make
cpu_mmu_index() return the right answer when the CPU is in...
cb2e37df 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 TCR_EL1

Implement the AArch64 TCR_EL1, which is the 64 bit view of
the AArch32 TTBCR. (The uses of the bits in the register are
completely different, but in any given situation the CPU will
always interpret them one way or the other. In fact for QEMU EL1...
a505d7fe 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 VBAR_EL1

Implement the A64 view of the VBAR system register.

Signed-off-by: Peter Maydell <>
Reviewed-by: Peter Crosthwaite <>
327ed10f 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 TTBR*

Implement the AArch64 TTBR* registers. For v7 these were already 64 bits
to handle LPAE, but implemented as two separate uint32_t fields.
Combine them into a single uint64_t which can be used for all purposes.
Since this requires touching every use, take the opportunity to rename...
4b7fff2f 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 MPIDR

Implement the AArch64 MPIDR system register.

Signed-off-by: Peter Maydell <>
Reviewed-by: Peter Crosthwaite <>

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