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1 | 267002cd | bellard | /*
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2 | 3cbee15b | j_mayer | * QEMU PowerMac CUDA device support
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3 | 5fafdf24 | ths | *
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4 | 3cbee15b | j_mayer | * Copyright (c) 2004-2007 Fabrice Bellard
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5 | 3cbee15b | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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6 | 5fafdf24 | ths | *
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7 | 267002cd | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 267002cd | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | 267002cd | bellard | * in the Software without restriction, including without limitation the rights
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10 | 267002cd | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 267002cd | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | 267002cd | bellard | * furnished to do so, subject to the following conditions:
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13 | 267002cd | bellard | *
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14 | 267002cd | bellard | * The above copyright notice and this permission notice shall be included in
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15 | 267002cd | bellard | * all copies or substantial portions of the Software.
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16 | 267002cd | bellard | *
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17 | 267002cd | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 267002cd | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 267002cd | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 267002cd | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 267002cd | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 267002cd | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 267002cd | bellard | * THE SOFTWARE.
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24 | 267002cd | bellard | */
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25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 3cbee15b | j_mayer | #include "ppc_mac.h" |
27 | 87ecb68b | pbrook | #include "qemu-timer.h" |
28 | 87ecb68b | pbrook | #include "sysemu.h" |
29 | 267002cd | bellard | |
30 | 61271e5c | bellard | /* XXX: implement all timer modes */
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31 | 61271e5c | bellard | |
32 | 819e712b | bellard | //#define DEBUG_CUDA
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33 | 819e712b | bellard | //#define DEBUG_CUDA_PACKET
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34 | 819e712b | bellard | |
35 | 267002cd | bellard | /* Bits in B data register: all active low */
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36 | 267002cd | bellard | #define TREQ 0x08 /* Transfer request (input) */ |
37 | 267002cd | bellard | #define TACK 0x10 /* Transfer acknowledge (output) */ |
38 | 267002cd | bellard | #define TIP 0x20 /* Transfer in progress (output) */ |
39 | 267002cd | bellard | |
40 | 267002cd | bellard | /* Bits in ACR */
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41 | 267002cd | bellard | #define SR_CTRL 0x1c /* Shift register control bits */ |
42 | 267002cd | bellard | #define SR_EXT 0x0c /* Shift on external clock */ |
43 | 267002cd | bellard | #define SR_OUT 0x10 /* Shift out if 1 */ |
44 | 267002cd | bellard | |
45 | 267002cd | bellard | /* Bits in IFR and IER */
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46 | 267002cd | bellard | #define IER_SET 0x80 /* set bits in IER */ |
47 | 267002cd | bellard | #define IER_CLR 0 /* clear bits in IER */ |
48 | 267002cd | bellard | #define SR_INT 0x04 /* Shift register full/empty */ |
49 | 267002cd | bellard | #define T1_INT 0x40 /* Timer 1 interrupt */ |
50 | 61271e5c | bellard | #define T2_INT 0x20 /* Timer 2 interrupt */ |
51 | 267002cd | bellard | |
52 | 267002cd | bellard | /* Bits in ACR */
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53 | 267002cd | bellard | #define T1MODE 0xc0 /* Timer 1 mode */ |
54 | 267002cd | bellard | #define T1MODE_CONT 0x40 /* continuous interrupts */ |
55 | 267002cd | bellard | |
56 | 267002cd | bellard | /* commands (1st byte) */
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57 | 267002cd | bellard | #define ADB_PACKET 0 |
58 | 267002cd | bellard | #define CUDA_PACKET 1 |
59 | 267002cd | bellard | #define ERROR_PACKET 2 |
60 | 267002cd | bellard | #define TIMER_PACKET 3 |
61 | 267002cd | bellard | #define POWER_PACKET 4 |
62 | 267002cd | bellard | #define MACIIC_PACKET 5 |
63 | 267002cd | bellard | #define PMU_PACKET 6 |
64 | 267002cd | bellard | |
65 | 267002cd | bellard | |
66 | 267002cd | bellard | /* CUDA commands (2nd byte) */
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67 | 267002cd | bellard | #define CUDA_WARM_START 0x0 |
68 | 267002cd | bellard | #define CUDA_AUTOPOLL 0x1 |
69 | 267002cd | bellard | #define CUDA_GET_6805_ADDR 0x2 |
70 | 267002cd | bellard | #define CUDA_GET_TIME 0x3 |
71 | 267002cd | bellard | #define CUDA_GET_PRAM 0x7 |
72 | 267002cd | bellard | #define CUDA_SET_6805_ADDR 0x8 |
73 | 267002cd | bellard | #define CUDA_SET_TIME 0x9 |
74 | 267002cd | bellard | #define CUDA_POWERDOWN 0xa |
75 | 267002cd | bellard | #define CUDA_POWERUP_TIME 0xb |
76 | 267002cd | bellard | #define CUDA_SET_PRAM 0xc |
77 | 267002cd | bellard | #define CUDA_MS_RESET 0xd |
78 | 267002cd | bellard | #define CUDA_SEND_DFAC 0xe |
79 | 267002cd | bellard | #define CUDA_BATTERY_SWAP_SENSE 0x10 |
80 | 267002cd | bellard | #define CUDA_RESET_SYSTEM 0x11 |
81 | 267002cd | bellard | #define CUDA_SET_IPL 0x12 |
82 | 267002cd | bellard | #define CUDA_FILE_SERVER_FLAG 0x13 |
83 | 267002cd | bellard | #define CUDA_SET_AUTO_RATE 0x14 |
84 | 267002cd | bellard | #define CUDA_GET_AUTO_RATE 0x16 |
85 | 267002cd | bellard | #define CUDA_SET_DEVICE_LIST 0x19 |
86 | 267002cd | bellard | #define CUDA_GET_DEVICE_LIST 0x1a |
87 | 267002cd | bellard | #define CUDA_SET_ONE_SECOND_MODE 0x1b |
88 | 267002cd | bellard | #define CUDA_SET_POWER_MESSAGES 0x21 |
89 | 267002cd | bellard | #define CUDA_GET_SET_IIC 0x22 |
90 | 267002cd | bellard | #define CUDA_WAKEUP 0x23 |
91 | 267002cd | bellard | #define CUDA_TIMER_TICKLE 0x24 |
92 | 267002cd | bellard | #define CUDA_COMBINED_FORMAT_IIC 0x25 |
93 | 267002cd | bellard | |
94 | 267002cd | bellard | #define CUDA_TIMER_FREQ (4700000 / 6) |
95 | e2733d20 | bellard | #define CUDA_ADB_POLL_FREQ 50 |
96 | 267002cd | bellard | |
97 | d7ce296f | bellard | /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
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98 | d7ce296f | bellard | #define RTC_OFFSET 2082844800 |
99 | d7ce296f | bellard | |
100 | 267002cd | bellard | typedef struct CUDATimer { |
101 | 5fafdf24 | ths | int index;
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102 | 61271e5c | bellard | uint16_t latch; |
103 | 267002cd | bellard | uint16_t counter_value; /* counter value at load time */
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104 | 267002cd | bellard | int64_t load_time; |
105 | 267002cd | bellard | int64_t next_irq_time; |
106 | 267002cd | bellard | QEMUTimer *timer; |
107 | 267002cd | bellard | } CUDATimer; |
108 | 267002cd | bellard | |
109 | 267002cd | bellard | typedef struct CUDAState { |
110 | 267002cd | bellard | /* cuda registers */
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111 | 267002cd | bellard | uint8_t b; /* B-side data */
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112 | 267002cd | bellard | uint8_t a; /* A-side data */
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113 | 267002cd | bellard | uint8_t dirb; /* B-side direction (1=output) */
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114 | 267002cd | bellard | uint8_t dira; /* A-side direction (1=output) */
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115 | 267002cd | bellard | uint8_t sr; /* Shift register */
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116 | 267002cd | bellard | uint8_t acr; /* Auxiliary control register */
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117 | 267002cd | bellard | uint8_t pcr; /* Peripheral control register */
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118 | 267002cd | bellard | uint8_t ifr; /* Interrupt flag register */
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119 | 267002cd | bellard | uint8_t ier; /* Interrupt enable register */
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120 | 267002cd | bellard | uint8_t anh; /* A-side data, no handshake */
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121 | 267002cd | bellard | |
122 | 267002cd | bellard | CUDATimer timers[2];
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123 | 3b46e624 | ths | |
124 | 267002cd | bellard | uint8_t last_b; /* last value of B register */
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125 | 267002cd | bellard | uint8_t last_acr; /* last value of B register */
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126 | 3b46e624 | ths | |
127 | 267002cd | bellard | int data_in_size;
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128 | 267002cd | bellard | int data_in_index;
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129 | 267002cd | bellard | int data_out_index;
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130 | 267002cd | bellard | |
131 | d537cf6c | pbrook | qemu_irq irq; |
132 | 267002cd | bellard | uint8_t autopoll; |
133 | 267002cd | bellard | uint8_t data_in[128];
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134 | 267002cd | bellard | uint8_t data_out[16];
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135 | e2733d20 | bellard | QEMUTimer *adb_poll_timer; |
136 | 267002cd | bellard | } CUDAState; |
137 | 267002cd | bellard | |
138 | 267002cd | bellard | static CUDAState cuda_state;
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139 | 267002cd | bellard | ADBBusState adb_bus; |
140 | 267002cd | bellard | |
141 | 267002cd | bellard | static void cuda_update(CUDAState *s); |
142 | 5fafdf24 | ths | static void cuda_receive_packet_from_host(CUDAState *s, |
143 | 267002cd | bellard | const uint8_t *data, int len); |
144 | 5fafdf24 | ths | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
145 | 819e712b | bellard | int64_t current_time); |
146 | 267002cd | bellard | |
147 | 267002cd | bellard | static void cuda_update_irq(CUDAState *s) |
148 | 267002cd | bellard | { |
149 | 819e712b | bellard | if (s->ifr & s->ier & (SR_INT | T1_INT)) {
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150 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
151 | 267002cd | bellard | } else {
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152 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
153 | 267002cd | bellard | } |
154 | 267002cd | bellard | } |
155 | 267002cd | bellard | |
156 | 267002cd | bellard | static unsigned int get_counter(CUDATimer *s) |
157 | 267002cd | bellard | { |
158 | 267002cd | bellard | int64_t d; |
159 | 267002cd | bellard | unsigned int counter; |
160 | 267002cd | bellard | |
161 | 5fafdf24 | ths | d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, |
162 | 267002cd | bellard | CUDA_TIMER_FREQ, ticks_per_sec); |
163 | 61271e5c | bellard | if (s->index == 0) { |
164 | 61271e5c | bellard | /* the timer goes down from latch to -1 (period of latch + 2) */
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165 | 61271e5c | bellard | if (d <= (s->counter_value + 1)) { |
166 | 61271e5c | bellard | counter = (s->counter_value - d) & 0xffff;
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167 | 61271e5c | bellard | } else {
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168 | 61271e5c | bellard | counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
169 | 5fafdf24 | ths | counter = (s->latch - counter) & 0xffff;
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170 | 61271e5c | bellard | } |
171 | 267002cd | bellard | } else {
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172 | 61271e5c | bellard | counter = (s->counter_value - d) & 0xffff;
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173 | 267002cd | bellard | } |
174 | 267002cd | bellard | return counter;
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175 | 267002cd | bellard | } |
176 | 267002cd | bellard | |
177 | 819e712b | bellard | static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) |
178 | 267002cd | bellard | { |
179 | 819e712b | bellard | #ifdef DEBUG_CUDA
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180 | 819e712b | bellard | printf("cuda: T%d.counter=%d\n",
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181 | 819e712b | bellard | 1 + (ti->timer == NULL), val); |
182 | 819e712b | bellard | #endif
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183 | 819e712b | bellard | ti->load_time = qemu_get_clock(vm_clock); |
184 | 819e712b | bellard | ti->counter_value = val; |
185 | 819e712b | bellard | cuda_timer_update(s, ti, ti->load_time); |
186 | 267002cd | bellard | } |
187 | 267002cd | bellard | |
188 | 267002cd | bellard | static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
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189 | 267002cd | bellard | { |
190 | 61271e5c | bellard | int64_t d, next_time; |
191 | 61271e5c | bellard | unsigned int counter; |
192 | 61271e5c | bellard | |
193 | 267002cd | bellard | /* current counter value */
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194 | 5fafdf24 | ths | d = muldiv64(current_time - s->load_time, |
195 | 267002cd | bellard | CUDA_TIMER_FREQ, ticks_per_sec); |
196 | 61271e5c | bellard | /* the timer goes down from latch to -1 (period of latch + 2) */
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197 | 61271e5c | bellard | if (d <= (s->counter_value + 1)) { |
198 | 61271e5c | bellard | counter = (s->counter_value - d) & 0xffff;
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199 | 61271e5c | bellard | } else {
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200 | 61271e5c | bellard | counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
201 | 5fafdf24 | ths | counter = (s->latch - counter) & 0xffff;
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202 | 61271e5c | bellard | } |
203 | 3b46e624 | ths | |
204 | 61271e5c | bellard | /* Note: we consider the irq is raised on 0 */
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205 | 61271e5c | bellard | if (counter == 0xffff) { |
206 | 61271e5c | bellard | next_time = d + s->latch + 1;
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207 | 61271e5c | bellard | } else if (counter == 0) { |
208 | 61271e5c | bellard | next_time = d + s->latch + 2;
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209 | 61271e5c | bellard | } else {
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210 | 61271e5c | bellard | next_time = d + counter; |
211 | 267002cd | bellard | } |
212 | dccfafc4 | bellard | #if 0
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213 | 819e712b | bellard | #ifdef DEBUG_CUDA
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214 | 5fafdf24 | ths | printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
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215 | 819e712b | bellard | s->latch, d, next_time - d);
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216 | 819e712b | bellard | #endif
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217 | dccfafc4 | bellard | #endif
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218 | 5fafdf24 | ths | next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) + |
219 | 267002cd | bellard | s->load_time; |
220 | 267002cd | bellard | if (next_time <= current_time)
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221 | 267002cd | bellard | next_time = current_time + 1;
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222 | 267002cd | bellard | return next_time;
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223 | 267002cd | bellard | } |
224 | 267002cd | bellard | |
225 | 5fafdf24 | ths | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
226 | 819e712b | bellard | int64_t current_time) |
227 | 819e712b | bellard | { |
228 | 819e712b | bellard | if (!ti->timer)
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229 | 819e712b | bellard | return;
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230 | 819e712b | bellard | if ((s->acr & T1MODE) != T1MODE_CONT) {
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231 | 819e712b | bellard | qemu_del_timer(ti->timer); |
232 | 819e712b | bellard | } else {
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233 | 819e712b | bellard | ti->next_irq_time = get_next_irq_time(ti, current_time); |
234 | 819e712b | bellard | qemu_mod_timer(ti->timer, ti->next_irq_time); |
235 | 819e712b | bellard | } |
236 | 819e712b | bellard | } |
237 | 819e712b | bellard | |
238 | 267002cd | bellard | static void cuda_timer1(void *opaque) |
239 | 267002cd | bellard | { |
240 | 267002cd | bellard | CUDAState *s = opaque; |
241 | 267002cd | bellard | CUDATimer *ti = &s->timers[0];
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242 | 267002cd | bellard | |
243 | 819e712b | bellard | cuda_timer_update(s, ti, ti->next_irq_time); |
244 | 267002cd | bellard | s->ifr |= T1_INT; |
245 | 267002cd | bellard | cuda_update_irq(s); |
246 | 267002cd | bellard | } |
247 | 267002cd | bellard | |
248 | 267002cd | bellard | static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) |
249 | 267002cd | bellard | { |
250 | 267002cd | bellard | CUDAState *s = opaque; |
251 | 267002cd | bellard | uint32_t val; |
252 | 267002cd | bellard | |
253 | 267002cd | bellard | addr = (addr >> 9) & 0xf; |
254 | 267002cd | bellard | switch(addr) {
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255 | 267002cd | bellard | case 0: |
256 | 267002cd | bellard | val = s->b; |
257 | 267002cd | bellard | break;
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258 | 267002cd | bellard | case 1: |
259 | 267002cd | bellard | val = s->a; |
260 | 267002cd | bellard | break;
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261 | 267002cd | bellard | case 2: |
262 | 267002cd | bellard | val = s->dirb; |
263 | 267002cd | bellard | break;
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264 | 267002cd | bellard | case 3: |
265 | 267002cd | bellard | val = s->dira; |
266 | 267002cd | bellard | break;
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267 | 267002cd | bellard | case 4: |
268 | 267002cd | bellard | val = get_counter(&s->timers[0]) & 0xff; |
269 | 267002cd | bellard | s->ifr &= ~T1_INT; |
270 | 267002cd | bellard | cuda_update_irq(s); |
271 | 267002cd | bellard | break;
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272 | 267002cd | bellard | case 5: |
273 | 267002cd | bellard | val = get_counter(&s->timers[0]) >> 8; |
274 | 267002cd | bellard | cuda_update_irq(s); |
275 | 267002cd | bellard | break;
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276 | 267002cd | bellard | case 6: |
277 | 267002cd | bellard | val = s->timers[0].latch & 0xff; |
278 | 267002cd | bellard | break;
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279 | 267002cd | bellard | case 7: |
280 | 61271e5c | bellard | /* XXX: check this */
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281 | 267002cd | bellard | val = (s->timers[0].latch >> 8) & 0xff; |
282 | 267002cd | bellard | break;
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283 | 267002cd | bellard | case 8: |
284 | 267002cd | bellard | val = get_counter(&s->timers[1]) & 0xff; |
285 | 61271e5c | bellard | s->ifr &= ~T2_INT; |
286 | 267002cd | bellard | break;
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287 | 267002cd | bellard | case 9: |
288 | 267002cd | bellard | val = get_counter(&s->timers[1]) >> 8; |
289 | 267002cd | bellard | break;
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290 | 267002cd | bellard | case 10: |
291 | 819e712b | bellard | val = s->sr; |
292 | 819e712b | bellard | s->ifr &= ~SR_INT; |
293 | 819e712b | bellard | cuda_update_irq(s); |
294 | 267002cd | bellard | break;
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295 | 267002cd | bellard | case 11: |
296 | 267002cd | bellard | val = s->acr; |
297 | 267002cd | bellard | break;
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298 | 267002cd | bellard | case 12: |
299 | 267002cd | bellard | val = s->pcr; |
300 | 267002cd | bellard | break;
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301 | 267002cd | bellard | case 13: |
302 | 267002cd | bellard | val = s->ifr; |
303 | 5fafdf24 | ths | if (s->ifr & s->ier)
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304 | b7c7b181 | bellard | val |= 0x80;
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305 | 267002cd | bellard | break;
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306 | 267002cd | bellard | case 14: |
307 | b7c7b181 | bellard | val = s->ier | 0x80;
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308 | 267002cd | bellard | break;
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309 | 267002cd | bellard | default:
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310 | 267002cd | bellard | case 15: |
311 | 267002cd | bellard | val = s->anh; |
312 | 267002cd | bellard | break;
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313 | 267002cd | bellard | } |
314 | 267002cd | bellard | #ifdef DEBUG_CUDA
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315 | 819e712b | bellard | if (addr != 13 || val != 0) |
316 | 819e712b | bellard | printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
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317 | 267002cd | bellard | #endif
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318 | 267002cd | bellard | return val;
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319 | 267002cd | bellard | } |
320 | 267002cd | bellard | |
321 | 267002cd | bellard | static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
322 | 267002cd | bellard | { |
323 | 267002cd | bellard | CUDAState *s = opaque; |
324 | 3b46e624 | ths | |
325 | 267002cd | bellard | addr = (addr >> 9) & 0xf; |
326 | 267002cd | bellard | #ifdef DEBUG_CUDA
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327 | 267002cd | bellard | printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
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328 | 267002cd | bellard | #endif
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329 | 267002cd | bellard | |
330 | 267002cd | bellard | switch(addr) {
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331 | 267002cd | bellard | case 0: |
332 | 267002cd | bellard | s->b = val; |
333 | 267002cd | bellard | cuda_update(s); |
334 | 267002cd | bellard | break;
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335 | 267002cd | bellard | case 1: |
336 | 267002cd | bellard | s->a = val; |
337 | 267002cd | bellard | break;
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338 | 267002cd | bellard | case 2: |
339 | 267002cd | bellard | s->dirb = val; |
340 | 267002cd | bellard | break;
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341 | 267002cd | bellard | case 3: |
342 | 267002cd | bellard | s->dira = val; |
343 | 267002cd | bellard | break;
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344 | 267002cd | bellard | case 4: |
345 | 61271e5c | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
346 | 61271e5c | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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347 | 267002cd | bellard | break;
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348 | 267002cd | bellard | case 5: |
349 | 61271e5c | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
350 | 61271e5c | bellard | s->ifr &= ~T1_INT; |
351 | 61271e5c | bellard | set_counter(s, &s->timers[0], s->timers[0].latch); |
352 | 267002cd | bellard | break;
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353 | 267002cd | bellard | case 6: |
354 | 267002cd | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
355 | 819e712b | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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356 | 267002cd | bellard | break;
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357 | 267002cd | bellard | case 7: |
358 | 267002cd | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
359 | 61271e5c | bellard | s->ifr &= ~T1_INT; |
360 | 819e712b | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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361 | 267002cd | bellard | break;
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362 | 267002cd | bellard | case 8: |
363 | 61271e5c | bellard | s->timers[1].latch = val;
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364 | 819e712b | bellard | set_counter(s, &s->timers[1], val);
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365 | 267002cd | bellard | break;
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366 | 267002cd | bellard | case 9: |
367 | 61271e5c | bellard | set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch); |
368 | 267002cd | bellard | break;
|
369 | 267002cd | bellard | case 10: |
370 | 267002cd | bellard | s->sr = val; |
371 | 267002cd | bellard | break;
|
372 | 267002cd | bellard | case 11: |
373 | 267002cd | bellard | s->acr = val; |
374 | 819e712b | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
375 | 267002cd | bellard | cuda_update(s); |
376 | 267002cd | bellard | break;
|
377 | 267002cd | bellard | case 12: |
378 | 267002cd | bellard | s->pcr = val; |
379 | 267002cd | bellard | break;
|
380 | 267002cd | bellard | case 13: |
381 | 267002cd | bellard | /* reset bits */
|
382 | 267002cd | bellard | s->ifr &= ~val; |
383 | 267002cd | bellard | cuda_update_irq(s); |
384 | 267002cd | bellard | break;
|
385 | 267002cd | bellard | case 14: |
386 | 267002cd | bellard | if (val & IER_SET) {
|
387 | 267002cd | bellard | /* set bits */
|
388 | 267002cd | bellard | s->ier |= val & 0x7f;
|
389 | 267002cd | bellard | } else {
|
390 | 267002cd | bellard | /* reset bits */
|
391 | 267002cd | bellard | s->ier &= ~val; |
392 | 267002cd | bellard | } |
393 | 267002cd | bellard | cuda_update_irq(s); |
394 | 267002cd | bellard | break;
|
395 | 267002cd | bellard | default:
|
396 | 267002cd | bellard | case 15: |
397 | 267002cd | bellard | s->anh = val; |
398 | 267002cd | bellard | break;
|
399 | 267002cd | bellard | } |
400 | 267002cd | bellard | } |
401 | 267002cd | bellard | |
402 | 267002cd | bellard | /* NOTE: TIP and TREQ are negated */
|
403 | 267002cd | bellard | static void cuda_update(CUDAState *s) |
404 | 267002cd | bellard | { |
405 | 819e712b | bellard | int packet_received, len;
|
406 | 819e712b | bellard | |
407 | 819e712b | bellard | packet_received = 0;
|
408 | 819e712b | bellard | if (!(s->b & TIP)) {
|
409 | 819e712b | bellard | /* transfer requested from host */
|
410 | 267002cd | bellard | |
411 | 819e712b | bellard | if (s->acr & SR_OUT) {
|
412 | 819e712b | bellard | /* data output */
|
413 | 819e712b | bellard | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
414 | 819e712b | bellard | if (s->data_out_index < sizeof(s->data_out)) { |
415 | 819e712b | bellard | #ifdef DEBUG_CUDA
|
416 | 819e712b | bellard | printf("cuda: send: %02x\n", s->sr);
|
417 | 819e712b | bellard | #endif
|
418 | 819e712b | bellard | s->data_out[s->data_out_index++] = s->sr; |
419 | 819e712b | bellard | s->ifr |= SR_INT; |
420 | 819e712b | bellard | cuda_update_irq(s); |
421 | 819e712b | bellard | } |
422 | 819e712b | bellard | } |
423 | 819e712b | bellard | } else {
|
424 | 819e712b | bellard | if (s->data_in_index < s->data_in_size) {
|
425 | 819e712b | bellard | /* data input */
|
426 | 819e712b | bellard | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
427 | 819e712b | bellard | s->sr = s->data_in[s->data_in_index++]; |
428 | 819e712b | bellard | #ifdef DEBUG_CUDA
|
429 | 819e712b | bellard | printf("cuda: recv: %02x\n", s->sr);
|
430 | 819e712b | bellard | #endif
|
431 | 819e712b | bellard | /* indicate end of transfer */
|
432 | 819e712b | bellard | if (s->data_in_index >= s->data_in_size) {
|
433 | 819e712b | bellard | s->b = (s->b | TREQ); |
434 | 819e712b | bellard | } |
435 | 819e712b | bellard | s->ifr |= SR_INT; |
436 | 819e712b | bellard | cuda_update_irq(s); |
437 | 819e712b | bellard | } |
438 | 267002cd | bellard | } |
439 | 819e712b | bellard | } |
440 | 819e712b | bellard | } else {
|
441 | 819e712b | bellard | /* no transfer requested: handle sync case */
|
442 | 819e712b | bellard | if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
|
443 | 819e712b | bellard | /* update TREQ state each time TACK change state */
|
444 | 819e712b | bellard | if (s->b & TACK)
|
445 | 819e712b | bellard | s->b = (s->b | TREQ); |
446 | 819e712b | bellard | else
|
447 | 819e712b | bellard | s->b = (s->b & ~TREQ); |
448 | 267002cd | bellard | s->ifr |= SR_INT; |
449 | 267002cd | bellard | cuda_update_irq(s); |
450 | 819e712b | bellard | } else {
|
451 | 819e712b | bellard | if (!(s->last_b & TIP)) {
|
452 | e91c8a77 | ths | /* handle end of host to cuda transfer */
|
453 | 819e712b | bellard | packet_received = (s->data_out_index > 0);
|
454 | e91c8a77 | ths | /* always an IRQ at the end of transfer */
|
455 | 819e712b | bellard | s->ifr |= SR_INT; |
456 | 819e712b | bellard | cuda_update_irq(s); |
457 | 819e712b | bellard | } |
458 | 819e712b | bellard | /* signal if there is data to read */
|
459 | 819e712b | bellard | if (s->data_in_index < s->data_in_size) {
|
460 | 819e712b | bellard | s->b = (s->b & ~TREQ); |
461 | 819e712b | bellard | } |
462 | 267002cd | bellard | } |
463 | 267002cd | bellard | } |
464 | 267002cd | bellard | |
465 | 267002cd | bellard | s->last_acr = s->acr; |
466 | 267002cd | bellard | s->last_b = s->b; |
467 | 819e712b | bellard | |
468 | 819e712b | bellard | /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
|
469 | 819e712b | bellard | recursively */
|
470 | 819e712b | bellard | if (packet_received) {
|
471 | 819e712b | bellard | len = s->data_out_index; |
472 | 819e712b | bellard | s->data_out_index = 0;
|
473 | 819e712b | bellard | cuda_receive_packet_from_host(s, s->data_out, len); |
474 | 819e712b | bellard | } |
475 | 267002cd | bellard | } |
476 | 267002cd | bellard | |
477 | 5fafdf24 | ths | static void cuda_send_packet_to_host(CUDAState *s, |
478 | 267002cd | bellard | const uint8_t *data, int len) |
479 | 267002cd | bellard | { |
480 | 819e712b | bellard | #ifdef DEBUG_CUDA_PACKET
|
481 | 819e712b | bellard | { |
482 | 819e712b | bellard | int i;
|
483 | 819e712b | bellard | printf("cuda_send_packet_to_host:\n");
|
484 | 819e712b | bellard | for(i = 0; i < len; i++) |
485 | 819e712b | bellard | printf(" %02x", data[i]);
|
486 | 819e712b | bellard | printf("\n");
|
487 | 819e712b | bellard | } |
488 | 819e712b | bellard | #endif
|
489 | 267002cd | bellard | memcpy(s->data_in, data, len); |
490 | 267002cd | bellard | s->data_in_size = len; |
491 | 267002cd | bellard | s->data_in_index = 0;
|
492 | 267002cd | bellard | cuda_update(s); |
493 | 267002cd | bellard | s->ifr |= SR_INT; |
494 | 267002cd | bellard | cuda_update_irq(s); |
495 | 267002cd | bellard | } |
496 | 267002cd | bellard | |
497 | 7db4eea6 | bellard | static void cuda_adb_poll(void *opaque) |
498 | e2733d20 | bellard | { |
499 | e2733d20 | bellard | CUDAState *s = opaque; |
500 | e2733d20 | bellard | uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
501 | e2733d20 | bellard | int olen;
|
502 | e2733d20 | bellard | |
503 | e2733d20 | bellard | olen = adb_poll(&adb_bus, obuf + 2);
|
504 | e2733d20 | bellard | if (olen > 0) { |
505 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
506 | e2733d20 | bellard | obuf[1] = 0x40; /* polled data */ |
507 | e2733d20 | bellard | cuda_send_packet_to_host(s, obuf, olen + 2);
|
508 | e2733d20 | bellard | } |
509 | 5fafdf24 | ths | qemu_mod_timer(s->adb_poll_timer, |
510 | 5fafdf24 | ths | qemu_get_clock(vm_clock) + |
511 | e2733d20 | bellard | (ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
512 | e2733d20 | bellard | } |
513 | e2733d20 | bellard | |
514 | 5fafdf24 | ths | static void cuda_receive_packet(CUDAState *s, |
515 | 267002cd | bellard | const uint8_t *data, int len) |
516 | 267002cd | bellard | { |
517 | 267002cd | bellard | uint8_t obuf[16];
|
518 | e2733d20 | bellard | int ti, autopoll;
|
519 | 267002cd | bellard | |
520 | 267002cd | bellard | switch(data[0]) { |
521 | 267002cd | bellard | case CUDA_AUTOPOLL:
|
522 | e2733d20 | bellard | autopoll = (data[1] != 0); |
523 | e2733d20 | bellard | if (autopoll != s->autopoll) {
|
524 | e2733d20 | bellard | s->autopoll = autopoll; |
525 | e2733d20 | bellard | if (autopoll) {
|
526 | 5fafdf24 | ths | qemu_mod_timer(s->adb_poll_timer, |
527 | 5fafdf24 | ths | qemu_get_clock(vm_clock) + |
528 | e2733d20 | bellard | (ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
529 | e2733d20 | bellard | } else {
|
530 | e2733d20 | bellard | qemu_del_timer(s->adb_poll_timer); |
531 | e2733d20 | bellard | } |
532 | e2733d20 | bellard | } |
533 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
534 | 267002cd | bellard | obuf[1] = data[1]; |
535 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
536 | 267002cd | bellard | break;
|
537 | 267002cd | bellard | case CUDA_GET_TIME:
|
538 | dccfafc4 | bellard | case CUDA_SET_TIME:
|
539 | 267002cd | bellard | /* XXX: add time support ? */
|
540 | d7ce296f | bellard | ti = time(NULL) + RTC_OFFSET;
|
541 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
542 | 267002cd | bellard | obuf[1] = 0; |
543 | 267002cd | bellard | obuf[2] = 0; |
544 | 267002cd | bellard | obuf[3] = ti >> 24; |
545 | 267002cd | bellard | obuf[4] = ti >> 16; |
546 | 267002cd | bellard | obuf[5] = ti >> 8; |
547 | 267002cd | bellard | obuf[6] = ti;
|
548 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 7);
|
549 | 267002cd | bellard | break;
|
550 | 267002cd | bellard | case CUDA_FILE_SERVER_FLAG:
|
551 | 267002cd | bellard | case CUDA_SET_DEVICE_LIST:
|
552 | 267002cd | bellard | case CUDA_SET_AUTO_RATE:
|
553 | 267002cd | bellard | case CUDA_SET_POWER_MESSAGES:
|
554 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
555 | 267002cd | bellard | obuf[1] = 0; |
556 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
557 | 267002cd | bellard | break;
|
558 | d7ce296f | bellard | case CUDA_POWERDOWN:
|
559 | d7ce296f | bellard | obuf[0] = CUDA_PACKET;
|
560 | d7ce296f | bellard | obuf[1] = 0; |
561 | d7ce296f | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
562 | d7ce296f | bellard | qemu_system_shutdown_request(); |
563 | d7ce296f | bellard | break;
|
564 | 0686970f | j_mayer | case CUDA_RESET_SYSTEM:
|
565 | 0686970f | j_mayer | obuf[0] = CUDA_PACKET;
|
566 | 0686970f | j_mayer | obuf[1] = 0; |
567 | 0686970f | j_mayer | cuda_send_packet_to_host(s, obuf, 2);
|
568 | 0686970f | j_mayer | qemu_system_reset_request(); |
569 | 0686970f | j_mayer | break;
|
570 | 267002cd | bellard | default:
|
571 | 267002cd | bellard | break;
|
572 | 267002cd | bellard | } |
573 | 267002cd | bellard | } |
574 | 267002cd | bellard | |
575 | 5fafdf24 | ths | static void cuda_receive_packet_from_host(CUDAState *s, |
576 | 267002cd | bellard | const uint8_t *data, int len) |
577 | 267002cd | bellard | { |
578 | 819e712b | bellard | #ifdef DEBUG_CUDA_PACKET
|
579 | 819e712b | bellard | { |
580 | 819e712b | bellard | int i;
|
581 | cadae95f | bellard | printf("cuda_receive_packet_from_host:\n");
|
582 | 819e712b | bellard | for(i = 0; i < len; i++) |
583 | 819e712b | bellard | printf(" %02x", data[i]);
|
584 | 819e712b | bellard | printf("\n");
|
585 | 819e712b | bellard | } |
586 | 819e712b | bellard | #endif
|
587 | 267002cd | bellard | switch(data[0]) { |
588 | 267002cd | bellard | case ADB_PACKET:
|
589 | e2733d20 | bellard | { |
590 | e2733d20 | bellard | uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
591 | e2733d20 | bellard | int olen;
|
592 | e2733d20 | bellard | olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1); |
593 | 38f0b147 | bellard | if (olen > 0) { |
594 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
595 | e2733d20 | bellard | obuf[1] = 0x00; |
596 | e2733d20 | bellard | } else {
|
597 | 38f0b147 | bellard | /* error */
|
598 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
599 | 38f0b147 | bellard | obuf[1] = -olen;
|
600 | 38f0b147 | bellard | olen = 0;
|
601 | e2733d20 | bellard | } |
602 | e2733d20 | bellard | cuda_send_packet_to_host(s, obuf, olen + 2);
|
603 | e2733d20 | bellard | } |
604 | 267002cd | bellard | break;
|
605 | 267002cd | bellard | case CUDA_PACKET:
|
606 | 267002cd | bellard | cuda_receive_packet(s, data + 1, len - 1); |
607 | 267002cd | bellard | break;
|
608 | 267002cd | bellard | } |
609 | 267002cd | bellard | } |
610 | 267002cd | bellard | |
611 | 267002cd | bellard | static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
612 | 267002cd | bellard | { |
613 | 267002cd | bellard | } |
614 | 267002cd | bellard | |
615 | 267002cd | bellard | static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
616 | 267002cd | bellard | { |
617 | 267002cd | bellard | } |
618 | 267002cd | bellard | |
619 | 267002cd | bellard | static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr) |
620 | 267002cd | bellard | { |
621 | 267002cd | bellard | return 0; |
622 | 267002cd | bellard | } |
623 | 267002cd | bellard | |
624 | 267002cd | bellard | static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr) |
625 | 267002cd | bellard | { |
626 | 267002cd | bellard | return 0; |
627 | 267002cd | bellard | } |
628 | 267002cd | bellard | |
629 | 267002cd | bellard | static CPUWriteMemoryFunc *cuda_write[] = {
|
630 | 267002cd | bellard | &cuda_writeb, |
631 | 267002cd | bellard | &cuda_writew, |
632 | 267002cd | bellard | &cuda_writel, |
633 | 267002cd | bellard | }; |
634 | 267002cd | bellard | |
635 | 267002cd | bellard | static CPUReadMemoryFunc *cuda_read[] = {
|
636 | 267002cd | bellard | &cuda_readb, |
637 | 267002cd | bellard | &cuda_readw, |
638 | 267002cd | bellard | &cuda_readl, |
639 | 267002cd | bellard | }; |
640 | 267002cd | bellard | |
641 | 3cbee15b | j_mayer | void cuda_init (int *cuda_mem_index, qemu_irq irq) |
642 | 267002cd | bellard | { |
643 | 267002cd | bellard | CUDAState *s = &cuda_state; |
644 | 267002cd | bellard | |
645 | 819e712b | bellard | s->irq = irq; |
646 | 819e712b | bellard | |
647 | 61271e5c | bellard | s->timers[0].index = 0; |
648 | 267002cd | bellard | s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
|
649 | 61271e5c | bellard | s->timers[0].latch = 0xffff; |
650 | 819e712b | bellard | set_counter(s, &s->timers[0], 0xffff); |
651 | 61271e5c | bellard | |
652 | 61271e5c | bellard | s->timers[1].index = 1; |
653 | 61271e5c | bellard | s->timers[1].latch = 0; |
654 | cadae95f | bellard | // s->ier = T1_INT | SR_INT;
|
655 | cadae95f | bellard | s->ier = 0;
|
656 | 819e712b | bellard | set_counter(s, &s->timers[1], 0xffff); |
657 | e2733d20 | bellard | |
658 | e2733d20 | bellard | s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s); |
659 | 3cbee15b | j_mayer | *cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
|
660 | 267002cd | bellard | } |