root / hw / grackle_pci.c @ 1ffc346f
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1 | 502a5395 | pbrook | /*
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2 | 3cbee15b | j_mayer | * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
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3 | 502a5395 | pbrook | *
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4 | 3cbee15b | j_mayer | * Copyright (c) 2006-2007 Fabrice Bellard
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5 | 3cbee15b | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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6 | 5fafdf24 | ths | *
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7 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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9 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
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10 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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12 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
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13 | 502a5395 | pbrook | *
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14 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
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15 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
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16 | 502a5395 | pbrook | *
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17 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 502a5395 | pbrook | * THE SOFTWARE.
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24 | 502a5395 | pbrook | */
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25 | 502a5395 | pbrook | |
26 | 87ecb68b | pbrook | #include "hw.h" |
27 | 3cbee15b | j_mayer | #include "ppc_mac.h" |
28 | 87ecb68b | pbrook | #include "pci.h" |
29 | 87ecb68b | pbrook | |
30 | 502a5395 | pbrook | typedef target_phys_addr_t pci_addr_t;
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31 | 502a5395 | pbrook | #include "pci_host.h" |
32 | 502a5395 | pbrook | |
33 | 502a5395 | pbrook | typedef PCIHostState GrackleState;
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34 | 502a5395 | pbrook | |
35 | 502a5395 | pbrook | static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, |
36 | 502a5395 | pbrook | uint32_t val) |
37 | 502a5395 | pbrook | { |
38 | 502a5395 | pbrook | GrackleState *s = opaque; |
39 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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40 | 502a5395 | pbrook | val = bswap32(val); |
41 | 502a5395 | pbrook | #endif
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42 | 502a5395 | pbrook | s->config_reg = val; |
43 | 502a5395 | pbrook | } |
44 | 502a5395 | pbrook | |
45 | 502a5395 | pbrook | static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) |
46 | 502a5395 | pbrook | { |
47 | 502a5395 | pbrook | GrackleState *s = opaque; |
48 | 502a5395 | pbrook | uint32_t val; |
49 | 502a5395 | pbrook | |
50 | 502a5395 | pbrook | val = s->config_reg; |
51 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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52 | 502a5395 | pbrook | val = bswap32(val); |
53 | 502a5395 | pbrook | #endif
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54 | 502a5395 | pbrook | return val;
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55 | 502a5395 | pbrook | } |
56 | 502a5395 | pbrook | |
57 | 502a5395 | pbrook | static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
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58 | 502a5395 | pbrook | &pci_grackle_config_writel, |
59 | 502a5395 | pbrook | &pci_grackle_config_writel, |
60 | 502a5395 | pbrook | &pci_grackle_config_writel, |
61 | 502a5395 | pbrook | }; |
62 | 502a5395 | pbrook | |
63 | 502a5395 | pbrook | static CPUReadMemoryFunc *pci_grackle_config_read[] = {
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64 | 502a5395 | pbrook | &pci_grackle_config_readl, |
65 | 502a5395 | pbrook | &pci_grackle_config_readl, |
66 | 502a5395 | pbrook | &pci_grackle_config_readl, |
67 | 502a5395 | pbrook | }; |
68 | 502a5395 | pbrook | |
69 | 502a5395 | pbrook | static CPUWriteMemoryFunc *pci_grackle_write[] = {
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70 | 502a5395 | pbrook | &pci_host_data_writeb, |
71 | 502a5395 | pbrook | &pci_host_data_writew, |
72 | 502a5395 | pbrook | &pci_host_data_writel, |
73 | 502a5395 | pbrook | }; |
74 | 502a5395 | pbrook | |
75 | 502a5395 | pbrook | static CPUReadMemoryFunc *pci_grackle_read[] = {
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76 | 502a5395 | pbrook | &pci_host_data_readb, |
77 | 502a5395 | pbrook | &pci_host_data_readw, |
78 | 502a5395 | pbrook | &pci_host_data_readl, |
79 | 502a5395 | pbrook | }; |
80 | 502a5395 | pbrook | |
81 | d2b59317 | pbrook | /* Don't know if this matches real hardware, but it agrees with OHW. */
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82 | d2b59317 | pbrook | static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) |
83 | 502a5395 | pbrook | { |
84 | d2b59317 | pbrook | return (irq_num + (pci_dev->devfn >> 3)) & 3; |
85 | d2b59317 | pbrook | } |
86 | d2b59317 | pbrook | |
87 | d537cf6c | pbrook | static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level) |
88 | d2b59317 | pbrook | { |
89 | 3cbee15b | j_mayer | qemu_set_irq(pic[irq_num + 0x15], level);
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90 | 502a5395 | pbrook | } |
91 | 502a5395 | pbrook | |
92 | d537cf6c | pbrook | PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic) |
93 | 502a5395 | pbrook | { |
94 | 502a5395 | pbrook | GrackleState *s; |
95 | 502a5395 | pbrook | PCIDevice *d; |
96 | 502a5395 | pbrook | int pci_mem_config, pci_mem_data;
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97 | 502a5395 | pbrook | |
98 | 502a5395 | pbrook | s = qemu_mallocz(sizeof(GrackleState));
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99 | 80b3ada7 | pbrook | s->bus = pci_register_bus(pci_grackle_set_irq, pci_grackle_map_irq, |
100 | 3cbee15b | j_mayer | pic, 0, 4); |
101 | 502a5395 | pbrook | |
102 | 5fafdf24 | ths | pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
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103 | 502a5395 | pbrook | pci_grackle_config_write, s); |
104 | 502a5395 | pbrook | pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
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105 | 502a5395 | pbrook | pci_grackle_write, s); |
106 | 502a5395 | pbrook | cpu_register_physical_memory(base, 0x1000, pci_mem_config);
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107 | 502a5395 | pbrook | cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data); |
108 | 5fafdf24 | ths | d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice), |
109 | 502a5395 | pbrook | 0, NULL, NULL); |
110 | 502a5395 | pbrook | d->config[0x00] = 0x57; // vendor_id |
111 | 502a5395 | pbrook | d->config[0x01] = 0x10; |
112 | 502a5395 | pbrook | d->config[0x02] = 0x02; // device_id |
113 | 502a5395 | pbrook | d->config[0x03] = 0x00; |
114 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision |
115 | 502a5395 | pbrook | d->config[0x09] = 0x01; |
116 | 502a5395 | pbrook | d->config[0x0a] = 0x00; // class_sub = host |
117 | 502a5395 | pbrook | d->config[0x0b] = 0x06; // class_base = PCI_bridge |
118 | 502a5395 | pbrook | d->config[0x0e] = 0x00; // header_type |
119 | 502a5395 | pbrook | |
120 | 502a5395 | pbrook | #if 0
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121 | 502a5395 | pbrook | /* PCI2PCI bridge same values as PearPC - check this */
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122 | 502a5395 | pbrook | d->config[0x00] = 0x11; // vendor_id
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123 | 502a5395 | pbrook | d->config[0x01] = 0x10;
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124 | 502a5395 | pbrook | d->config[0x02] = 0x26; // device_id
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125 | 502a5395 | pbrook | d->config[0x03] = 0x00;
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126 | 502a5395 | pbrook | d->config[0x08] = 0x02; // revision
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127 | 502a5395 | pbrook | d->config[0x0a] = 0x04; // class_sub = pci2pci
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128 | 502a5395 | pbrook | d->config[0x0b] = 0x06; // class_base = PCI_bridge
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129 | 502a5395 | pbrook | d->config[0x0e] = 0x01; // header_type
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130 | 502a5395 | pbrook | |
131 | 502a5395 | pbrook | d->config[0x18] = 0x0; // primary_bus
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132 | 502a5395 | pbrook | d->config[0x19] = 0x1; // secondary_bus
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133 | 502a5395 | pbrook | d->config[0x1a] = 0x1; // subordinate_bus
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134 | 502a5395 | pbrook | d->config[0x1c] = 0x10; // io_base
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135 | 502a5395 | pbrook | d->config[0x1d] = 0x20; // io_limit
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136 | 3b46e624 | ths | |
137 | 502a5395 | pbrook | d->config[0x20] = 0x80; // memory_base
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138 | 502a5395 | pbrook | d->config[0x21] = 0x80;
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139 | 502a5395 | pbrook | d->config[0x22] = 0x90; // memory_limit
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140 | 502a5395 | pbrook | d->config[0x23] = 0x80;
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141 | 3b46e624 | ths | |
142 | 502a5395 | pbrook | d->config[0x24] = 0x00; // prefetchable_memory_base
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143 | 502a5395 | pbrook | d->config[0x25] = 0x84;
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144 | 502a5395 | pbrook | d->config[0x26] = 0x00; // prefetchable_memory_limit
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145 | 502a5395 | pbrook | d->config[0x27] = 0x85;
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146 | 502a5395 | pbrook | #endif
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147 | 502a5395 | pbrook | return s->bus;
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148 | 502a5395 | pbrook | } |