root / hw / m48t59.c @ 1ffc346f
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1 | a541f297 | bellard | /*
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2 | 819385c5 | bellard | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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3 | 5fafdf24 | ths | *
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4 | 3ccacc4a | blueswir1 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "nvram.h" |
26 | 87ecb68b | pbrook | #include "isa.h" |
27 | 87ecb68b | pbrook | #include "qemu-timer.h" |
28 | 87ecb68b | pbrook | #include "sysemu.h" |
29 | a541f297 | bellard | |
30 | 13ab5daa | bellard | //#define DEBUG_NVRAM
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31 | a541f297 | bellard | |
32 | 13ab5daa | bellard | #if defined(DEBUG_NVRAM)
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33 | a541f297 | bellard | #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0) |
34 | a541f297 | bellard | #else
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35 | a541f297 | bellard | #define NVRAM_PRINTF(fmt, args...) do { } while (0) |
36 | a541f297 | bellard | #endif
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37 | a541f297 | bellard | |
38 | 819385c5 | bellard | /*
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39 | 4aed2c33 | blueswir1 | * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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40 | 819385c5 | bellard | * alarm and a watchdog timer and related control registers. In the
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41 | 819385c5 | bellard | * PPC platform there is also a nvram lock function.
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42 | 819385c5 | bellard | */
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43 | c5df018e | bellard | struct m48t59_t {
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44 | 819385c5 | bellard | /* Model parameters */
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45 | 4aed2c33 | blueswir1 | int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59 |
46 | a541f297 | bellard | /* Hardware parameters */
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47 | d537cf6c | pbrook | qemu_irq IRQ; |
48 | e1bb04f7 | bellard | int mem_index;
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49 | 5dcb6b91 | blueswir1 | target_phys_addr_t mem_base; |
50 | a541f297 | bellard | uint32_t io_base; |
51 | a541f297 | bellard | uint16_t size; |
52 | a541f297 | bellard | /* RTC management */
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53 | a541f297 | bellard | time_t time_offset; |
54 | a541f297 | bellard | time_t stop_time; |
55 | a541f297 | bellard | /* Alarm & watchdog */
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56 | f6503059 | balrog | struct tm alarm;
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57 | a541f297 | bellard | struct QEMUTimer *alrm_timer;
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58 | a541f297 | bellard | struct QEMUTimer *wd_timer;
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59 | a541f297 | bellard | /* NVRAM storage */
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60 | 13ab5daa | bellard | uint8_t lock; |
61 | a541f297 | bellard | uint16_t addr; |
62 | a541f297 | bellard | uint8_t *buffer; |
63 | c5df018e | bellard | }; |
64 | a541f297 | bellard | |
65 | a541f297 | bellard | /* Fake timer functions */
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66 | a541f297 | bellard | /* Generic helpers for BCD */
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67 | a541f297 | bellard | static inline uint8_t toBCD (uint8_t value) |
68 | a541f297 | bellard | { |
69 | a541f297 | bellard | return (((value / 10) % 10) << 4) | (value % 10); |
70 | a541f297 | bellard | } |
71 | a541f297 | bellard | |
72 | a541f297 | bellard | static inline uint8_t fromBCD (uint8_t BCD) |
73 | a541f297 | bellard | { |
74 | a541f297 | bellard | return ((BCD >> 4) * 10) + (BCD & 0x0F); |
75 | a541f297 | bellard | } |
76 | a541f297 | bellard | |
77 | a541f297 | bellard | /* Alarm management */
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78 | a541f297 | bellard | static void alarm_cb (void *opaque) |
79 | a541f297 | bellard | { |
80 | f6503059 | balrog | struct tm tm;
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81 | a541f297 | bellard | uint64_t next_time; |
82 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
83 | a541f297 | bellard | |
84 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
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85 | 5fafdf24 | ths | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
86 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
87 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
88 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
89 | f6503059 | balrog | /* Repeat once a month */
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90 | f6503059 | balrog | qemu_get_timedate(&tm, NVRAM->time_offset); |
91 | f6503059 | balrog | tm.tm_mon++; |
92 | f6503059 | balrog | if (tm.tm_mon == 13) { |
93 | f6503059 | balrog | tm.tm_mon = 1;
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94 | f6503059 | balrog | tm.tm_year++; |
95 | f6503059 | balrog | } |
96 | f6503059 | balrog | next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; |
97 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
98 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
99 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
100 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
101 | f6503059 | balrog | /* Repeat once a day */
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102 | f6503059 | balrog | next_time = 24 * 60 * 60; |
103 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
104 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
105 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
106 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
107 | f6503059 | balrog | /* Repeat once an hour */
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108 | f6503059 | balrog | next_time = 60 * 60; |
109 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
110 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
111 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
112 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
113 | f6503059 | balrog | /* Repeat once a minute */
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114 | f6503059 | balrog | next_time = 60;
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115 | a541f297 | bellard | } else {
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116 | f6503059 | balrog | /* Repeat once a second */
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117 | f6503059 | balrog | next_time = 1;
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118 | a541f297 | bellard | } |
119 | f6503059 | balrog | qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) + |
120 | f6503059 | balrog | next_time * 1000);
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121 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
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122 | a541f297 | bellard | } |
123 | a541f297 | bellard | |
124 | f6503059 | balrog | static void set_alarm (m48t59_t *NVRAM) |
125 | f6503059 | balrog | { |
126 | f6503059 | balrog | int diff;
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127 | f6503059 | balrog | if (NVRAM->alrm_timer != NULL) { |
128 | f6503059 | balrog | qemu_del_timer(NVRAM->alrm_timer); |
129 | f6503059 | balrog | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
130 | f6503059 | balrog | if (diff > 0) |
131 | f6503059 | balrog | qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
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132 | f6503059 | balrog | } |
133 | f6503059 | balrog | } |
134 | a541f297 | bellard | |
135 | f6503059 | balrog | /* RTC management helpers */
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136 | f6503059 | balrog | static inline void get_time (m48t59_t *NVRAM, struct tm *tm) |
137 | a541f297 | bellard | { |
138 | f6503059 | balrog | qemu_get_timedate(tm, NVRAM->time_offset); |
139 | a541f297 | bellard | } |
140 | a541f297 | bellard | |
141 | f6503059 | balrog | static void set_time (m48t59_t *NVRAM, struct tm *tm) |
142 | a541f297 | bellard | { |
143 | f6503059 | balrog | NVRAM->time_offset = qemu_timedate_diff(tm); |
144 | f6503059 | balrog | set_alarm(NVRAM); |
145 | a541f297 | bellard | } |
146 | a541f297 | bellard | |
147 | a541f297 | bellard | /* Watchdog management */
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148 | a541f297 | bellard | static void watchdog_cb (void *opaque) |
149 | a541f297 | bellard | { |
150 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
151 | a541f297 | bellard | |
152 | a541f297 | bellard | NVRAM->buffer[0x1FF0] |= 0x80; |
153 | a541f297 | bellard | if (NVRAM->buffer[0x1FF7] & 0x80) { |
154 | a541f297 | bellard | NVRAM->buffer[0x1FF7] = 0x00; |
155 | a541f297 | bellard | NVRAM->buffer[0x1FFC] &= ~0x40; |
156 | 13ab5daa | bellard | /* May it be a hw CPU Reset instead ? */
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157 | d7d02e3c | bellard | qemu_system_reset_request(); |
158 | a541f297 | bellard | } else {
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159 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
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160 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
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161 | a541f297 | bellard | } |
162 | a541f297 | bellard | } |
163 | a541f297 | bellard | |
164 | a541f297 | bellard | static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) |
165 | a541f297 | bellard | { |
166 | a541f297 | bellard | uint64_t interval; /* in 1/16 seconds */
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167 | a541f297 | bellard | |
168 | 868d585a | j_mayer | NVRAM->buffer[0x1FF0] &= ~0x80; |
169 | a541f297 | bellard | if (NVRAM->wd_timer != NULL) { |
170 | a541f297 | bellard | qemu_del_timer(NVRAM->wd_timer); |
171 | 868d585a | j_mayer | if (value != 0) { |
172 | 868d585a | j_mayer | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
173 | 868d585a | j_mayer | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
174 | 868d585a | j_mayer | ((interval * 1000) >> 4)); |
175 | 868d585a | j_mayer | } |
176 | a541f297 | bellard | } |
177 | a541f297 | bellard | } |
178 | a541f297 | bellard | |
179 | a541f297 | bellard | /* Direct access to NVRAM */
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180 | 897b4c6c | j_mayer | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
181 | a541f297 | bellard | { |
182 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
183 | a541f297 | bellard | struct tm tm;
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184 | a541f297 | bellard | int tmp;
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185 | a541f297 | bellard | |
186 | 819385c5 | bellard | if (addr > 0x1FF8 && addr < 0x2000) |
187 | 819385c5 | bellard | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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188 | 4aed2c33 | blueswir1 | |
189 | 4aed2c33 | blueswir1 | /* check for NVRAM access */
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190 | 4aed2c33 | blueswir1 | if ((NVRAM->type == 2 && addr < 0x7f8) || |
191 | 4aed2c33 | blueswir1 | (NVRAM->type == 8 && addr < 0x1ff8) || |
192 | 4aed2c33 | blueswir1 | (NVRAM->type == 59 && addr < 0x1ff0)) |
193 | 819385c5 | bellard | goto do_write;
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194 | 4aed2c33 | blueswir1 | |
195 | 4aed2c33 | blueswir1 | /* TOD access */
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196 | 819385c5 | bellard | switch (addr) {
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197 | a541f297 | bellard | case 0x1FF0: |
198 | a541f297 | bellard | /* flags register : read-only */
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199 | a541f297 | bellard | break;
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200 | a541f297 | bellard | case 0x1FF1: |
201 | a541f297 | bellard | /* unused */
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202 | a541f297 | bellard | break;
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203 | a541f297 | bellard | case 0x1FF2: |
204 | a541f297 | bellard | /* alarm seconds */
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205 | 819385c5 | bellard | tmp = fromBCD(val & 0x7F);
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206 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
207 | f6503059 | balrog | NVRAM->alarm.tm_sec = tmp; |
208 | 819385c5 | bellard | NVRAM->buffer[0x1FF2] = val;
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209 | f6503059 | balrog | set_alarm(NVRAM); |
210 | 819385c5 | bellard | } |
211 | a541f297 | bellard | break;
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212 | a541f297 | bellard | case 0x1FF3: |
213 | a541f297 | bellard | /* alarm minutes */
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214 | 819385c5 | bellard | tmp = fromBCD(val & 0x7F);
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215 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
216 | f6503059 | balrog | NVRAM->alarm.tm_min = tmp; |
217 | 819385c5 | bellard | NVRAM->buffer[0x1FF3] = val;
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218 | f6503059 | balrog | set_alarm(NVRAM); |
219 | 819385c5 | bellard | } |
220 | a541f297 | bellard | break;
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221 | a541f297 | bellard | case 0x1FF4: |
222 | a541f297 | bellard | /* alarm hours */
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223 | 819385c5 | bellard | tmp = fromBCD(val & 0x3F);
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224 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 23) { |
225 | f6503059 | balrog | NVRAM->alarm.tm_hour = tmp; |
226 | 819385c5 | bellard | NVRAM->buffer[0x1FF4] = val;
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227 | f6503059 | balrog | set_alarm(NVRAM); |
228 | 819385c5 | bellard | } |
229 | a541f297 | bellard | break;
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230 | a541f297 | bellard | case 0x1FF5: |
231 | a541f297 | bellard | /* alarm date */
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232 | 819385c5 | bellard | tmp = fromBCD(val & 0x1F);
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233 | 819385c5 | bellard | if (tmp != 0) { |
234 | f6503059 | balrog | NVRAM->alarm.tm_mday = tmp; |
235 | 819385c5 | bellard | NVRAM->buffer[0x1FF5] = val;
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236 | f6503059 | balrog | set_alarm(NVRAM); |
237 | 819385c5 | bellard | } |
238 | a541f297 | bellard | break;
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239 | a541f297 | bellard | case 0x1FF6: |
240 | a541f297 | bellard | /* interrupts */
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241 | 819385c5 | bellard | NVRAM->buffer[0x1FF6] = val;
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242 | a541f297 | bellard | break;
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243 | a541f297 | bellard | case 0x1FF7: |
244 | a541f297 | bellard | /* watchdog */
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245 | 819385c5 | bellard | NVRAM->buffer[0x1FF7] = val;
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246 | 819385c5 | bellard | set_up_watchdog(NVRAM, val); |
247 | a541f297 | bellard | break;
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248 | a541f297 | bellard | case 0x1FF8: |
249 | 4aed2c33 | blueswir1 | case 0x07F8: |
250 | a541f297 | bellard | /* control */
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251 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
252 | a541f297 | bellard | break;
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253 | a541f297 | bellard | case 0x1FF9: |
254 | 4aed2c33 | blueswir1 | case 0x07F9: |
255 | a541f297 | bellard | /* seconds (BCD) */
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256 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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257 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
258 | a541f297 | bellard | get_time(NVRAM, &tm); |
259 | a541f297 | bellard | tm.tm_sec = tmp; |
260 | a541f297 | bellard | set_time(NVRAM, &tm); |
261 | a541f297 | bellard | } |
262 | f6503059 | balrog | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
263 | a541f297 | bellard | if (val & 0x80) { |
264 | a541f297 | bellard | NVRAM->stop_time = time(NULL);
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265 | a541f297 | bellard | } else {
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266 | a541f297 | bellard | NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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267 | a541f297 | bellard | NVRAM->stop_time = 0;
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268 | a541f297 | bellard | } |
269 | a541f297 | bellard | } |
270 | f6503059 | balrog | NVRAM->buffer[addr] = val & 0x80;
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271 | a541f297 | bellard | break;
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272 | a541f297 | bellard | case 0x1FFA: |
273 | 4aed2c33 | blueswir1 | case 0x07FA: |
274 | a541f297 | bellard | /* minutes (BCD) */
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275 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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276 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
277 | a541f297 | bellard | get_time(NVRAM, &tm); |
278 | a541f297 | bellard | tm.tm_min = tmp; |
279 | a541f297 | bellard | set_time(NVRAM, &tm); |
280 | a541f297 | bellard | } |
281 | a541f297 | bellard | break;
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282 | a541f297 | bellard | case 0x1FFB: |
283 | 4aed2c33 | blueswir1 | case 0x07FB: |
284 | a541f297 | bellard | /* hours (BCD) */
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285 | a541f297 | bellard | tmp = fromBCD(val & 0x3F);
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286 | a541f297 | bellard | if (tmp >= 0 && tmp <= 23) { |
287 | a541f297 | bellard | get_time(NVRAM, &tm); |
288 | a541f297 | bellard | tm.tm_hour = tmp; |
289 | a541f297 | bellard | set_time(NVRAM, &tm); |
290 | a541f297 | bellard | } |
291 | a541f297 | bellard | break;
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292 | a541f297 | bellard | case 0x1FFC: |
293 | 4aed2c33 | blueswir1 | case 0x07FC: |
294 | a541f297 | bellard | /* day of the week / century */
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295 | a541f297 | bellard | tmp = fromBCD(val & 0x07);
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296 | a541f297 | bellard | get_time(NVRAM, &tm); |
297 | a541f297 | bellard | tm.tm_wday = tmp; |
298 | a541f297 | bellard | set_time(NVRAM, &tm); |
299 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = val & 0x40;
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300 | a541f297 | bellard | break;
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301 | a541f297 | bellard | case 0x1FFD: |
302 | 4aed2c33 | blueswir1 | case 0x07FD: |
303 | a541f297 | bellard | /* date */
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304 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
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305 | a541f297 | bellard | if (tmp != 0) { |
306 | a541f297 | bellard | get_time(NVRAM, &tm); |
307 | a541f297 | bellard | tm.tm_mday = tmp; |
308 | a541f297 | bellard | set_time(NVRAM, &tm); |
309 | a541f297 | bellard | } |
310 | a541f297 | bellard | break;
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311 | a541f297 | bellard | case 0x1FFE: |
312 | 4aed2c33 | blueswir1 | case 0x07FE: |
313 | a541f297 | bellard | /* month */
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314 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
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315 | a541f297 | bellard | if (tmp >= 1 && tmp <= 12) { |
316 | a541f297 | bellard | get_time(NVRAM, &tm); |
317 | a541f297 | bellard | tm.tm_mon = tmp - 1;
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318 | a541f297 | bellard | set_time(NVRAM, &tm); |
319 | a541f297 | bellard | } |
320 | a541f297 | bellard | break;
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321 | a541f297 | bellard | case 0x1FFF: |
322 | 4aed2c33 | blueswir1 | case 0x07FF: |
323 | a541f297 | bellard | /* year */
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324 | a541f297 | bellard | tmp = fromBCD(val); |
325 | a541f297 | bellard | if (tmp >= 0 && tmp <= 99) { |
326 | a541f297 | bellard | get_time(NVRAM, &tm); |
327 | 180b700d | bellard | if (NVRAM->type == 8) |
328 | 180b700d | bellard | tm.tm_year = fromBCD(val) + 68; // Base year is 1968 |
329 | 180b700d | bellard | else
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330 | 180b700d | bellard | tm.tm_year = fromBCD(val); |
331 | a541f297 | bellard | set_time(NVRAM, &tm); |
332 | a541f297 | bellard | } |
333 | a541f297 | bellard | break;
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334 | a541f297 | bellard | default:
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335 | 13ab5daa | bellard | /* Check lock registers state */
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336 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
337 | 13ab5daa | bellard | break;
|
338 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
339 | 13ab5daa | bellard | break;
|
340 | 819385c5 | bellard | do_write:
|
341 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
342 | 819385c5 | bellard | NVRAM->buffer[addr] = val & 0xFF;
|
343 | a541f297 | bellard | } |
344 | a541f297 | bellard | break;
|
345 | a541f297 | bellard | } |
346 | a541f297 | bellard | } |
347 | a541f297 | bellard | |
348 | 897b4c6c | j_mayer | uint32_t m48t59_read (void *opaque, uint32_t addr)
|
349 | a541f297 | bellard | { |
350 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
351 | a541f297 | bellard | struct tm tm;
|
352 | a541f297 | bellard | uint32_t retval = 0xFF;
|
353 | a541f297 | bellard | |
354 | 4aed2c33 | blueswir1 | /* check for NVRAM access */
|
355 | 4aed2c33 | blueswir1 | if ((NVRAM->type == 2 && addr < 0x078f) || |
356 | 4aed2c33 | blueswir1 | (NVRAM->type == 8 && addr < 0x1ff8) || |
357 | 4aed2c33 | blueswir1 | (NVRAM->type == 59 && addr < 0x1ff0)) |
358 | 819385c5 | bellard | goto do_read;
|
359 | 4aed2c33 | blueswir1 | |
360 | 4aed2c33 | blueswir1 | /* TOD access */
|
361 | 819385c5 | bellard | switch (addr) {
|
362 | a541f297 | bellard | case 0x1FF0: |
363 | a541f297 | bellard | /* flags register */
|
364 | a541f297 | bellard | goto do_read;
|
365 | a541f297 | bellard | case 0x1FF1: |
366 | a541f297 | bellard | /* unused */
|
367 | a541f297 | bellard | retval = 0;
|
368 | a541f297 | bellard | break;
|
369 | a541f297 | bellard | case 0x1FF2: |
370 | a541f297 | bellard | /* alarm seconds */
|
371 | a541f297 | bellard | goto do_read;
|
372 | a541f297 | bellard | case 0x1FF3: |
373 | a541f297 | bellard | /* alarm minutes */
|
374 | a541f297 | bellard | goto do_read;
|
375 | a541f297 | bellard | case 0x1FF4: |
376 | a541f297 | bellard | /* alarm hours */
|
377 | a541f297 | bellard | goto do_read;
|
378 | a541f297 | bellard | case 0x1FF5: |
379 | a541f297 | bellard | /* alarm date */
|
380 | a541f297 | bellard | goto do_read;
|
381 | a541f297 | bellard | case 0x1FF6: |
382 | a541f297 | bellard | /* interrupts */
|
383 | a541f297 | bellard | goto do_read;
|
384 | a541f297 | bellard | case 0x1FF7: |
385 | a541f297 | bellard | /* A read resets the watchdog */
|
386 | a541f297 | bellard | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
387 | a541f297 | bellard | goto do_read;
|
388 | a541f297 | bellard | case 0x1FF8: |
389 | 4aed2c33 | blueswir1 | case 0x07F8: |
390 | a541f297 | bellard | /* control */
|
391 | a541f297 | bellard | goto do_read;
|
392 | a541f297 | bellard | case 0x1FF9: |
393 | 4aed2c33 | blueswir1 | case 0x07F9: |
394 | a541f297 | bellard | /* seconds (BCD) */
|
395 | a541f297 | bellard | get_time(NVRAM, &tm); |
396 | 4aed2c33 | blueswir1 | retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
|
397 | a541f297 | bellard | break;
|
398 | a541f297 | bellard | case 0x1FFA: |
399 | 4aed2c33 | blueswir1 | case 0x07FA: |
400 | a541f297 | bellard | /* minutes (BCD) */
|
401 | a541f297 | bellard | get_time(NVRAM, &tm); |
402 | a541f297 | bellard | retval = toBCD(tm.tm_min); |
403 | a541f297 | bellard | break;
|
404 | a541f297 | bellard | case 0x1FFB: |
405 | 4aed2c33 | blueswir1 | case 0x07FB: |
406 | a541f297 | bellard | /* hours (BCD) */
|
407 | a541f297 | bellard | get_time(NVRAM, &tm); |
408 | a541f297 | bellard | retval = toBCD(tm.tm_hour); |
409 | a541f297 | bellard | break;
|
410 | a541f297 | bellard | case 0x1FFC: |
411 | 4aed2c33 | blueswir1 | case 0x07FC: |
412 | a541f297 | bellard | /* day of the week / century */
|
413 | a541f297 | bellard | get_time(NVRAM, &tm); |
414 | 4aed2c33 | blueswir1 | retval = NVRAM->buffer[addr] | tm.tm_wday; |
415 | a541f297 | bellard | break;
|
416 | a541f297 | bellard | case 0x1FFD: |
417 | 4aed2c33 | blueswir1 | case 0x07FD: |
418 | a541f297 | bellard | /* date */
|
419 | a541f297 | bellard | get_time(NVRAM, &tm); |
420 | a541f297 | bellard | retval = toBCD(tm.tm_mday); |
421 | a541f297 | bellard | break;
|
422 | a541f297 | bellard | case 0x1FFE: |
423 | 4aed2c33 | blueswir1 | case 0x07FE: |
424 | a541f297 | bellard | /* month */
|
425 | a541f297 | bellard | get_time(NVRAM, &tm); |
426 | a541f297 | bellard | retval = toBCD(tm.tm_mon + 1);
|
427 | a541f297 | bellard | break;
|
428 | a541f297 | bellard | case 0x1FFF: |
429 | 4aed2c33 | blueswir1 | case 0x07FF: |
430 | a541f297 | bellard | /* year */
|
431 | a541f297 | bellard | get_time(NVRAM, &tm); |
432 | 5fafdf24 | ths | if (NVRAM->type == 8) |
433 | 180b700d | bellard | retval = toBCD(tm.tm_year - 68); // Base year is 1968 |
434 | 180b700d | bellard | else
|
435 | 180b700d | bellard | retval = toBCD(tm.tm_year); |
436 | a541f297 | bellard | break;
|
437 | a541f297 | bellard | default:
|
438 | 13ab5daa | bellard | /* Check lock registers state */
|
439 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
440 | 13ab5daa | bellard | break;
|
441 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
442 | 13ab5daa | bellard | break;
|
443 | 819385c5 | bellard | do_read:
|
444 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
445 | 819385c5 | bellard | retval = NVRAM->buffer[addr]; |
446 | a541f297 | bellard | } |
447 | a541f297 | bellard | break;
|
448 | a541f297 | bellard | } |
449 | 819385c5 | bellard | if (addr > 0x1FF9 && addr < 0x2000) |
450 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
451 | a541f297 | bellard | |
452 | a541f297 | bellard | return retval;
|
453 | a541f297 | bellard | } |
454 | a541f297 | bellard | |
455 | 897b4c6c | j_mayer | void m48t59_set_addr (void *opaque, uint32_t addr) |
456 | a541f297 | bellard | { |
457 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
458 | 897b4c6c | j_mayer | |
459 | a541f297 | bellard | NVRAM->addr = addr; |
460 | a541f297 | bellard | } |
461 | a541f297 | bellard | |
462 | 897b4c6c | j_mayer | void m48t59_toggle_lock (void *opaque, int lock) |
463 | 13ab5daa | bellard | { |
464 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
465 | 897b4c6c | j_mayer | |
466 | 13ab5daa | bellard | NVRAM->lock ^= 1 << lock;
|
467 | 13ab5daa | bellard | } |
468 | 13ab5daa | bellard | |
469 | a541f297 | bellard | /* IO access to NVRAM */
|
470 | a541f297 | bellard | static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
471 | a541f297 | bellard | { |
472 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
473 | a541f297 | bellard | |
474 | a541f297 | bellard | addr -= NVRAM->io_base; |
475 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
476 | a541f297 | bellard | switch (addr) {
|
477 | a541f297 | bellard | case 0: |
478 | a541f297 | bellard | NVRAM->addr &= ~0x00FF;
|
479 | a541f297 | bellard | NVRAM->addr |= val; |
480 | a541f297 | bellard | break;
|
481 | a541f297 | bellard | case 1: |
482 | a541f297 | bellard | NVRAM->addr &= ~0xFF00;
|
483 | a541f297 | bellard | NVRAM->addr |= val << 8;
|
484 | a541f297 | bellard | break;
|
485 | a541f297 | bellard | case 3: |
486 | 819385c5 | bellard | m48t59_write(NVRAM, val, NVRAM->addr); |
487 | a541f297 | bellard | NVRAM->addr = 0x0000;
|
488 | a541f297 | bellard | break;
|
489 | a541f297 | bellard | default:
|
490 | a541f297 | bellard | break;
|
491 | a541f297 | bellard | } |
492 | a541f297 | bellard | } |
493 | a541f297 | bellard | |
494 | a541f297 | bellard | static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
495 | a541f297 | bellard | { |
496 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
497 | 13ab5daa | bellard | uint32_t retval; |
498 | a541f297 | bellard | |
499 | 13ab5daa | bellard | addr -= NVRAM->io_base; |
500 | 13ab5daa | bellard | switch (addr) {
|
501 | 13ab5daa | bellard | case 3: |
502 | 819385c5 | bellard | retval = m48t59_read(NVRAM, NVRAM->addr); |
503 | 13ab5daa | bellard | break;
|
504 | 13ab5daa | bellard | default:
|
505 | 13ab5daa | bellard | retval = -1;
|
506 | 13ab5daa | bellard | break;
|
507 | 13ab5daa | bellard | } |
508 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
509 | a541f297 | bellard | |
510 | 13ab5daa | bellard | return retval;
|
511 | a541f297 | bellard | } |
512 | a541f297 | bellard | |
513 | e1bb04f7 | bellard | static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
514 | e1bb04f7 | bellard | { |
515 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
516 | 3b46e624 | ths | |
517 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
518 | 819385c5 | bellard | m48t59_write(NVRAM, addr, value & 0xff);
|
519 | e1bb04f7 | bellard | } |
520 | e1bb04f7 | bellard | |
521 | e1bb04f7 | bellard | static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
522 | e1bb04f7 | bellard | { |
523 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
524 | 3b46e624 | ths | |
525 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
526 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
527 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, value & 0xff); |
528 | e1bb04f7 | bellard | } |
529 | e1bb04f7 | bellard | |
530 | e1bb04f7 | bellard | static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
531 | e1bb04f7 | bellard | { |
532 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
533 | 3b46e624 | ths | |
534 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
535 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
536 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
537 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
538 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 3, value & 0xff); |
539 | e1bb04f7 | bellard | } |
540 | e1bb04f7 | bellard | |
541 | e1bb04f7 | bellard | static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
542 | e1bb04f7 | bellard | { |
543 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
544 | 819385c5 | bellard | uint32_t retval; |
545 | 3b46e624 | ths | |
546 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
547 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr); |
548 | e1bb04f7 | bellard | return retval;
|
549 | e1bb04f7 | bellard | } |
550 | e1bb04f7 | bellard | |
551 | e1bb04f7 | bellard | static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
552 | e1bb04f7 | bellard | { |
553 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
554 | 819385c5 | bellard | uint32_t retval; |
555 | 3b46e624 | ths | |
556 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
557 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 8;
|
558 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1);
|
559 | e1bb04f7 | bellard | return retval;
|
560 | e1bb04f7 | bellard | } |
561 | e1bb04f7 | bellard | |
562 | e1bb04f7 | bellard | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
563 | e1bb04f7 | bellard | { |
564 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
565 | 819385c5 | bellard | uint32_t retval; |
566 | e1bb04f7 | bellard | |
567 | 819385c5 | bellard | addr -= NVRAM->mem_base; |
568 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 24;
|
569 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1) << 16; |
570 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 2) << 8; |
571 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 3);
|
572 | e1bb04f7 | bellard | return retval;
|
573 | e1bb04f7 | bellard | } |
574 | e1bb04f7 | bellard | |
575 | e1bb04f7 | bellard | static CPUWriteMemoryFunc *nvram_write[] = {
|
576 | e1bb04f7 | bellard | &nvram_writeb, |
577 | e1bb04f7 | bellard | &nvram_writew, |
578 | e1bb04f7 | bellard | &nvram_writel, |
579 | e1bb04f7 | bellard | }; |
580 | e1bb04f7 | bellard | |
581 | e1bb04f7 | bellard | static CPUReadMemoryFunc *nvram_read[] = {
|
582 | e1bb04f7 | bellard | &nvram_readb, |
583 | e1bb04f7 | bellard | &nvram_readw, |
584 | e1bb04f7 | bellard | &nvram_readl, |
585 | e1bb04f7 | bellard | }; |
586 | 819385c5 | bellard | |
587 | 3ccacc4a | blueswir1 | static void m48t59_save(QEMUFile *f, void *opaque) |
588 | 3ccacc4a | blueswir1 | { |
589 | 3ccacc4a | blueswir1 | m48t59_t *s = opaque; |
590 | 3ccacc4a | blueswir1 | |
591 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->lock); |
592 | 3ccacc4a | blueswir1 | qemu_put_be16s(f, &s->addr); |
593 | 3ccacc4a | blueswir1 | qemu_put_buffer(f, s->buffer, s->size); |
594 | 3ccacc4a | blueswir1 | } |
595 | 3ccacc4a | blueswir1 | |
596 | 3ccacc4a | blueswir1 | static int m48t59_load(QEMUFile *f, void *opaque, int version_id) |
597 | 3ccacc4a | blueswir1 | { |
598 | 3ccacc4a | blueswir1 | m48t59_t *s = opaque; |
599 | 3ccacc4a | blueswir1 | |
600 | 3ccacc4a | blueswir1 | if (version_id != 1) |
601 | 3ccacc4a | blueswir1 | return -EINVAL;
|
602 | 3ccacc4a | blueswir1 | |
603 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->lock); |
604 | 3ccacc4a | blueswir1 | qemu_get_be16s(f, &s->addr); |
605 | 3ccacc4a | blueswir1 | qemu_get_buffer(f, s->buffer, s->size); |
606 | 3ccacc4a | blueswir1 | |
607 | 3ccacc4a | blueswir1 | return 0; |
608 | 3ccacc4a | blueswir1 | } |
609 | 3ccacc4a | blueswir1 | |
610 | 3ccacc4a | blueswir1 | static void m48t59_reset(void *opaque) |
611 | 3ccacc4a | blueswir1 | { |
612 | 3ccacc4a | blueswir1 | m48t59_t *NVRAM = opaque; |
613 | 3ccacc4a | blueswir1 | |
614 | 3ccacc4a | blueswir1 | if (NVRAM->alrm_timer != NULL) |
615 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->alrm_timer); |
616 | 3ccacc4a | blueswir1 | |
617 | 3ccacc4a | blueswir1 | if (NVRAM->wd_timer != NULL) |
618 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->wd_timer); |
619 | 3ccacc4a | blueswir1 | } |
620 | 3ccacc4a | blueswir1 | |
621 | a541f297 | bellard | /* Initialisation routine */
|
622 | 5dcb6b91 | blueswir1 | m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, |
623 | 819385c5 | bellard | uint32_t io_base, uint16_t size, |
624 | 819385c5 | bellard | int type)
|
625 | a541f297 | bellard | { |
626 | c5df018e | bellard | m48t59_t *s; |
627 | 5dcb6b91 | blueswir1 | target_phys_addr_t save_base; |
628 | a541f297 | bellard | |
629 | c5df018e | bellard | s = qemu_mallocz(sizeof(m48t59_t));
|
630 | c5df018e | bellard | if (!s)
|
631 | a541f297 | bellard | return NULL; |
632 | c5df018e | bellard | s->buffer = qemu_mallocz(size); |
633 | c5df018e | bellard | if (!s->buffer) {
|
634 | c5df018e | bellard | qemu_free(s); |
635 | c5df018e | bellard | return NULL; |
636 | c5df018e | bellard | } |
637 | c5df018e | bellard | s->IRQ = IRQ; |
638 | c5df018e | bellard | s->size = size; |
639 | e1bb04f7 | bellard | s->mem_base = mem_base; |
640 | c5df018e | bellard | s->io_base = io_base; |
641 | c5df018e | bellard | s->addr = 0;
|
642 | 819385c5 | bellard | s->type = type; |
643 | 819385c5 | bellard | if (io_base != 0) { |
644 | 819385c5 | bellard | register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
645 | 819385c5 | bellard | register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
646 | 819385c5 | bellard | } |
647 | e1bb04f7 | bellard | if (mem_base != 0) { |
648 | e1bb04f7 | bellard | s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
|
649 | 4aed2c33 | blueswir1 | cpu_register_physical_memory(mem_base, size, s->mem_index); |
650 | e1bb04f7 | bellard | } |
651 | 819385c5 | bellard | if (type == 59) { |
652 | 819385c5 | bellard | s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); |
653 | 819385c5 | bellard | s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); |
654 | 819385c5 | bellard | } |
655 | 13ab5daa | bellard | s->lock = 0;
|
656 | f6503059 | balrog | qemu_get_timedate(&s->alarm, 0);
|
657 | 13ab5daa | bellard | |
658 | 3ccacc4a | blueswir1 | qemu_register_reset(m48t59_reset, s); |
659 | 3ccacc4a | blueswir1 | save_base = mem_base ? mem_base : io_base; |
660 | 3ccacc4a | blueswir1 | register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s); |
661 | 3ccacc4a | blueswir1 | |
662 | c5df018e | bellard | return s;
|
663 | a541f297 | bellard | } |