root / hw / m48t59.c @ 1ffc346f
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/*
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* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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*
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* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "nvram.h" |
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#include "isa.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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//#define DEBUG_NVRAM
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#if defined(DEBUG_NVRAM)
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#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0) |
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#else
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#define NVRAM_PRINTF(fmt, args...) do { } while (0) |
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#endif
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/*
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* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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* alarm and a watchdog timer and related control registers. In the
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* PPC platform there is also a nvram lock function.
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*/
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struct m48t59_t {
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/* Model parameters */
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int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59 |
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/* Hardware parameters */
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qemu_irq IRQ; |
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int mem_index;
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target_phys_addr_t mem_base; |
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uint32_t io_base; |
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uint16_t size; |
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/* RTC management */
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time_t time_offset; |
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time_t stop_time; |
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/* Alarm & watchdog */
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struct tm alarm;
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struct QEMUTimer *alrm_timer;
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struct QEMUTimer *wd_timer;
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/* NVRAM storage */
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uint8_t lock; |
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uint16_t addr; |
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uint8_t *buffer; |
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}; |
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/* Fake timer functions */
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/* Generic helpers for BCD */
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static inline uint8_t toBCD (uint8_t value) |
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{ |
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return (((value / 10) % 10) << 4) | (value % 10); |
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} |
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|
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static inline uint8_t fromBCD (uint8_t BCD) |
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{ |
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return ((BCD >> 4) * 10) + (BCD & 0x0F); |
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} |
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|
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/* Alarm management */
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static void alarm_cb (void *opaque) |
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{ |
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struct tm tm;
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uint64_t next_time; |
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m48t59_t *NVRAM = opaque; |
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|
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qemu_set_irq(NVRAM->IRQ, 1);
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if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a month */
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qemu_get_timedate(&tm, NVRAM->time_offset); |
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tm.tm_mon++; |
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if (tm.tm_mon == 13) { |
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tm.tm_mon = 1;
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tm.tm_year++; |
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} |
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next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a day */
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next_time = 24 * 60 * 60; |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once an hour */
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next_time = 60 * 60; |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a minute */
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next_time = 60;
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} else {
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/* Repeat once a second */
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next_time = 1;
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} |
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qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) + |
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next_time * 1000);
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qemu_set_irq(NVRAM->IRQ, 0);
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} |
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static void set_alarm (m48t59_t *NVRAM) |
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{ |
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int diff;
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if (NVRAM->alrm_timer != NULL) { |
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qemu_del_timer(NVRAM->alrm_timer); |
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diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
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if (diff > 0) |
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qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
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} |
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} |
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/* RTC management helpers */
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static inline void get_time (m48t59_t *NVRAM, struct tm *tm) |
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{ |
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qemu_get_timedate(tm, NVRAM->time_offset); |
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} |
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static void set_time (m48t59_t *NVRAM, struct tm *tm) |
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{ |
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NVRAM->time_offset = qemu_timedate_diff(tm); |
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set_alarm(NVRAM); |
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} |
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/* Watchdog management */
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static void watchdog_cb (void *opaque) |
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{ |
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m48t59_t *NVRAM = opaque; |
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NVRAM->buffer[0x1FF0] |= 0x80; |
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if (NVRAM->buffer[0x1FF7] & 0x80) { |
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NVRAM->buffer[0x1FF7] = 0x00; |
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NVRAM->buffer[0x1FFC] &= ~0x40; |
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/* May it be a hw CPU Reset instead ? */
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qemu_system_reset_request(); |
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} else {
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qemu_set_irq(NVRAM->IRQ, 1);
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qemu_set_irq(NVRAM->IRQ, 0);
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} |
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} |
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static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) |
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{ |
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uint64_t interval; /* in 1/16 seconds */
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NVRAM->buffer[0x1FF0] &= ~0x80; |
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if (NVRAM->wd_timer != NULL) { |
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qemu_del_timer(NVRAM->wd_timer); |
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if (value != 0) { |
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interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
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qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
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((interval * 1000) >> 4)); |
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} |
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} |
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} |
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/* Direct access to NVRAM */
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void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
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{ |
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m48t59_t *NVRAM = opaque; |
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struct tm tm;
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int tmp;
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if (addr > 0x1FF8 && addr < 0x2000) |
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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/* check for NVRAM access */
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if ((NVRAM->type == 2 && addr < 0x7f8) || |
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(NVRAM->type == 8 && addr < 0x1ff8) || |
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(NVRAM->type == 59 && addr < 0x1ff0)) |
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goto do_write;
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/* TOD access */
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switch (addr) {
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case 0x1FF0: |
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/* flags register : read-only */
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break;
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case 0x1FF1: |
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/* unused */
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break;
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case 0x1FF2: |
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/* alarm seconds */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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NVRAM->alarm.tm_sec = tmp; |
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NVRAM->buffer[0x1FF2] = val;
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set_alarm(NVRAM); |
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} |
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break;
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case 0x1FF3: |
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/* alarm minutes */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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NVRAM->alarm.tm_min = tmp; |
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NVRAM->buffer[0x1FF3] = val;
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set_alarm(NVRAM); |
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} |
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break;
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case 0x1FF4: |
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/* alarm hours */
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tmp = fromBCD(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) { |
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NVRAM->alarm.tm_hour = tmp; |
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NVRAM->buffer[0x1FF4] = val;
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set_alarm(NVRAM); |
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} |
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break;
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case 0x1FF5: |
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/* alarm date */
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tmp = fromBCD(val & 0x1F);
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if (tmp != 0) { |
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NVRAM->alarm.tm_mday = tmp; |
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NVRAM->buffer[0x1FF5] = val;
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set_alarm(NVRAM); |
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} |
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break;
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case 0x1FF6: |
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/* interrupts */
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NVRAM->buffer[0x1FF6] = val;
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break;
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case 0x1FF7: |
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/* watchdog */
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NVRAM->buffer[0x1FF7] = val;
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set_up_watchdog(NVRAM, val); |
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break;
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case 0x1FF8: |
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case 0x07F8: |
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/* control */
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NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
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break;
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case 0x1FF9: |
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case 0x07F9: |
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/* seconds (BCD) */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
258 |
get_time(NVRAM, &tm); |
259 |
tm.tm_sec = tmp; |
260 |
set_time(NVRAM, &tm); |
261 |
} |
262 |
if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
263 |
if (val & 0x80) { |
264 |
NVRAM->stop_time = time(NULL);
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} else {
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NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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NVRAM->stop_time = 0;
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} |
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} |
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NVRAM->buffer[addr] = val & 0x80;
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break;
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case 0x1FFA: |
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case 0x07FA: |
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/* minutes (BCD) */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
277 |
get_time(NVRAM, &tm); |
278 |
tm.tm_min = tmp; |
279 |
set_time(NVRAM, &tm); |
280 |
} |
281 |
break;
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case 0x1FFB: |
283 |
case 0x07FB: |
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/* hours (BCD) */
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tmp = fromBCD(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) { |
287 |
get_time(NVRAM, &tm); |
288 |
tm.tm_hour = tmp; |
289 |
set_time(NVRAM, &tm); |
290 |
} |
291 |
break;
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case 0x1FFC: |
293 |
case 0x07FC: |
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/* day of the week / century */
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295 |
tmp = fromBCD(val & 0x07);
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get_time(NVRAM, &tm); |
297 |
tm.tm_wday = tmp; |
298 |
set_time(NVRAM, &tm); |
299 |
NVRAM->buffer[addr] = val & 0x40;
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break;
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case 0x1FFD: |
302 |
case 0x07FD: |
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/* date */
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304 |
tmp = fromBCD(val & 0x1F);
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305 |
if (tmp != 0) { |
306 |
get_time(NVRAM, &tm); |
307 |
tm.tm_mday = tmp; |
308 |
set_time(NVRAM, &tm); |
309 |
} |
310 |
break;
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311 |
case 0x1FFE: |
312 |
case 0x07FE: |
313 |
/* month */
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314 |
tmp = fromBCD(val & 0x1F);
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315 |
if (tmp >= 1 && tmp <= 12) { |
316 |
get_time(NVRAM, &tm); |
317 |
tm.tm_mon = tmp - 1;
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318 |
set_time(NVRAM, &tm); |
319 |
} |
320 |
break;
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321 |
case 0x1FFF: |
322 |
case 0x07FF: |
323 |
/* year */
|
324 |
tmp = fromBCD(val); |
325 |
if (tmp >= 0 && tmp <= 99) { |
326 |
get_time(NVRAM, &tm); |
327 |
if (NVRAM->type == 8) |
328 |
tm.tm_year = fromBCD(val) + 68; // Base year is 1968 |
329 |
else
|
330 |
tm.tm_year = fromBCD(val); |
331 |
set_time(NVRAM, &tm); |
332 |
} |
333 |
break;
|
334 |
default:
|
335 |
/* Check lock registers state */
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336 |
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
337 |
break;
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338 |
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
339 |
break;
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340 |
do_write:
|
341 |
if (addr < NVRAM->size) {
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342 |
NVRAM->buffer[addr] = val & 0xFF;
|
343 |
} |
344 |
break;
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345 |
} |
346 |
} |
347 |
|
348 |
uint32_t m48t59_read (void *opaque, uint32_t addr)
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349 |
{ |
350 |
m48t59_t *NVRAM = opaque; |
351 |
struct tm tm;
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352 |
uint32_t retval = 0xFF;
|
353 |
|
354 |
/* check for NVRAM access */
|
355 |
if ((NVRAM->type == 2 && addr < 0x078f) || |
356 |
(NVRAM->type == 8 && addr < 0x1ff8) || |
357 |
(NVRAM->type == 59 && addr < 0x1ff0)) |
358 |
goto do_read;
|
359 |
|
360 |
/* TOD access */
|
361 |
switch (addr) {
|
362 |
case 0x1FF0: |
363 |
/* flags register */
|
364 |
goto do_read;
|
365 |
case 0x1FF1: |
366 |
/* unused */
|
367 |
retval = 0;
|
368 |
break;
|
369 |
case 0x1FF2: |
370 |
/* alarm seconds */
|
371 |
goto do_read;
|
372 |
case 0x1FF3: |
373 |
/* alarm minutes */
|
374 |
goto do_read;
|
375 |
case 0x1FF4: |
376 |
/* alarm hours */
|
377 |
goto do_read;
|
378 |
case 0x1FF5: |
379 |
/* alarm date */
|
380 |
goto do_read;
|
381 |
case 0x1FF6: |
382 |
/* interrupts */
|
383 |
goto do_read;
|
384 |
case 0x1FF7: |
385 |
/* A read resets the watchdog */
|
386 |
set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
387 |
goto do_read;
|
388 |
case 0x1FF8: |
389 |
case 0x07F8: |
390 |
/* control */
|
391 |
goto do_read;
|
392 |
case 0x1FF9: |
393 |
case 0x07F9: |
394 |
/* seconds (BCD) */
|
395 |
get_time(NVRAM, &tm); |
396 |
retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
|
397 |
break;
|
398 |
case 0x1FFA: |
399 |
case 0x07FA: |
400 |
/* minutes (BCD) */
|
401 |
get_time(NVRAM, &tm); |
402 |
retval = toBCD(tm.tm_min); |
403 |
break;
|
404 |
case 0x1FFB: |
405 |
case 0x07FB: |
406 |
/* hours (BCD) */
|
407 |
get_time(NVRAM, &tm); |
408 |
retval = toBCD(tm.tm_hour); |
409 |
break;
|
410 |
case 0x1FFC: |
411 |
case 0x07FC: |
412 |
/* day of the week / century */
|
413 |
get_time(NVRAM, &tm); |
414 |
retval = NVRAM->buffer[addr] | tm.tm_wday; |
415 |
break;
|
416 |
case 0x1FFD: |
417 |
case 0x07FD: |
418 |
/* date */
|
419 |
get_time(NVRAM, &tm); |
420 |
retval = toBCD(tm.tm_mday); |
421 |
break;
|
422 |
case 0x1FFE: |
423 |
case 0x07FE: |
424 |
/* month */
|
425 |
get_time(NVRAM, &tm); |
426 |
retval = toBCD(tm.tm_mon + 1);
|
427 |
break;
|
428 |
case 0x1FFF: |
429 |
case 0x07FF: |
430 |
/* year */
|
431 |
get_time(NVRAM, &tm); |
432 |
if (NVRAM->type == 8) |
433 |
retval = toBCD(tm.tm_year - 68); // Base year is 1968 |
434 |
else
|
435 |
retval = toBCD(tm.tm_year); |
436 |
break;
|
437 |
default:
|
438 |
/* Check lock registers state */
|
439 |
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
440 |
break;
|
441 |
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
442 |
break;
|
443 |
do_read:
|
444 |
if (addr < NVRAM->size) {
|
445 |
retval = NVRAM->buffer[addr]; |
446 |
} |
447 |
break;
|
448 |
} |
449 |
if (addr > 0x1FF9 && addr < 0x2000) |
450 |
NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
451 |
|
452 |
return retval;
|
453 |
} |
454 |
|
455 |
void m48t59_set_addr (void *opaque, uint32_t addr) |
456 |
{ |
457 |
m48t59_t *NVRAM = opaque; |
458 |
|
459 |
NVRAM->addr = addr; |
460 |
} |
461 |
|
462 |
void m48t59_toggle_lock (void *opaque, int lock) |
463 |
{ |
464 |
m48t59_t *NVRAM = opaque; |
465 |
|
466 |
NVRAM->lock ^= 1 << lock;
|
467 |
} |
468 |
|
469 |
/* IO access to NVRAM */
|
470 |
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
471 |
{ |
472 |
m48t59_t *NVRAM = opaque; |
473 |
|
474 |
addr -= NVRAM->io_base; |
475 |
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
476 |
switch (addr) {
|
477 |
case 0: |
478 |
NVRAM->addr &= ~0x00FF;
|
479 |
NVRAM->addr |= val; |
480 |
break;
|
481 |
case 1: |
482 |
NVRAM->addr &= ~0xFF00;
|
483 |
NVRAM->addr |= val << 8;
|
484 |
break;
|
485 |
case 3: |
486 |
m48t59_write(NVRAM, val, NVRAM->addr); |
487 |
NVRAM->addr = 0x0000;
|
488 |
break;
|
489 |
default:
|
490 |
break;
|
491 |
} |
492 |
} |
493 |
|
494 |
static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
495 |
{ |
496 |
m48t59_t *NVRAM = opaque; |
497 |
uint32_t retval; |
498 |
|
499 |
addr -= NVRAM->io_base; |
500 |
switch (addr) {
|
501 |
case 3: |
502 |
retval = m48t59_read(NVRAM, NVRAM->addr); |
503 |
break;
|
504 |
default:
|
505 |
retval = -1;
|
506 |
break;
|
507 |
} |
508 |
NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
509 |
|
510 |
return retval;
|
511 |
} |
512 |
|
513 |
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
514 |
{ |
515 |
m48t59_t *NVRAM = opaque; |
516 |
|
517 |
addr -= NVRAM->mem_base; |
518 |
m48t59_write(NVRAM, addr, value & 0xff);
|
519 |
} |
520 |
|
521 |
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
522 |
{ |
523 |
m48t59_t *NVRAM = opaque; |
524 |
|
525 |
addr -= NVRAM->mem_base; |
526 |
m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
527 |
m48t59_write(NVRAM, addr + 1, value & 0xff); |
528 |
} |
529 |
|
530 |
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
531 |
{ |
532 |
m48t59_t *NVRAM = opaque; |
533 |
|
534 |
addr -= NVRAM->mem_base; |
535 |
m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
536 |
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
537 |
m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
538 |
m48t59_write(NVRAM, addr + 3, value & 0xff); |
539 |
} |
540 |
|
541 |
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
542 |
{ |
543 |
m48t59_t *NVRAM = opaque; |
544 |
uint32_t retval; |
545 |
|
546 |
addr -= NVRAM->mem_base; |
547 |
retval = m48t59_read(NVRAM, addr); |
548 |
return retval;
|
549 |
} |
550 |
|
551 |
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
552 |
{ |
553 |
m48t59_t *NVRAM = opaque; |
554 |
uint32_t retval; |
555 |
|
556 |
addr -= NVRAM->mem_base; |
557 |
retval = m48t59_read(NVRAM, addr) << 8;
|
558 |
retval |= m48t59_read(NVRAM, addr + 1);
|
559 |
return retval;
|
560 |
} |
561 |
|
562 |
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
563 |
{ |
564 |
m48t59_t *NVRAM = opaque; |
565 |
uint32_t retval; |
566 |
|
567 |
addr -= NVRAM->mem_base; |
568 |
retval = m48t59_read(NVRAM, addr) << 24;
|
569 |
retval |= m48t59_read(NVRAM, addr + 1) << 16; |
570 |
retval |= m48t59_read(NVRAM, addr + 2) << 8; |
571 |
retval |= m48t59_read(NVRAM, addr + 3);
|
572 |
return retval;
|
573 |
} |
574 |
|
575 |
static CPUWriteMemoryFunc *nvram_write[] = {
|
576 |
&nvram_writeb, |
577 |
&nvram_writew, |
578 |
&nvram_writel, |
579 |
}; |
580 |
|
581 |
static CPUReadMemoryFunc *nvram_read[] = {
|
582 |
&nvram_readb, |
583 |
&nvram_readw, |
584 |
&nvram_readl, |
585 |
}; |
586 |
|
587 |
static void m48t59_save(QEMUFile *f, void *opaque) |
588 |
{ |
589 |
m48t59_t *s = opaque; |
590 |
|
591 |
qemu_put_8s(f, &s->lock); |
592 |
qemu_put_be16s(f, &s->addr); |
593 |
qemu_put_buffer(f, s->buffer, s->size); |
594 |
} |
595 |
|
596 |
static int m48t59_load(QEMUFile *f, void *opaque, int version_id) |
597 |
{ |
598 |
m48t59_t *s = opaque; |
599 |
|
600 |
if (version_id != 1) |
601 |
return -EINVAL;
|
602 |
|
603 |
qemu_get_8s(f, &s->lock); |
604 |
qemu_get_be16s(f, &s->addr); |
605 |
qemu_get_buffer(f, s->buffer, s->size); |
606 |
|
607 |
return 0; |
608 |
} |
609 |
|
610 |
static void m48t59_reset(void *opaque) |
611 |
{ |
612 |
m48t59_t *NVRAM = opaque; |
613 |
|
614 |
if (NVRAM->alrm_timer != NULL) |
615 |
qemu_del_timer(NVRAM->alrm_timer); |
616 |
|
617 |
if (NVRAM->wd_timer != NULL) |
618 |
qemu_del_timer(NVRAM->wd_timer); |
619 |
} |
620 |
|
621 |
/* Initialisation routine */
|
622 |
m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, |
623 |
uint32_t io_base, uint16_t size, |
624 |
int type)
|
625 |
{ |
626 |
m48t59_t *s; |
627 |
target_phys_addr_t save_base; |
628 |
|
629 |
s = qemu_mallocz(sizeof(m48t59_t));
|
630 |
if (!s)
|
631 |
return NULL; |
632 |
s->buffer = qemu_mallocz(size); |
633 |
if (!s->buffer) {
|
634 |
qemu_free(s); |
635 |
return NULL; |
636 |
} |
637 |
s->IRQ = IRQ; |
638 |
s->size = size; |
639 |
s->mem_base = mem_base; |
640 |
s->io_base = io_base; |
641 |
s->addr = 0;
|
642 |
s->type = type; |
643 |
if (io_base != 0) { |
644 |
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
645 |
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
646 |
} |
647 |
if (mem_base != 0) { |
648 |
s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
|
649 |
cpu_register_physical_memory(mem_base, size, s->mem_index); |
650 |
} |
651 |
if (type == 59) { |
652 |
s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); |
653 |
s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); |
654 |
} |
655 |
s->lock = 0;
|
656 |
qemu_get_timedate(&s->alarm, 0);
|
657 |
|
658 |
qemu_register_reset(m48t59_reset, s); |
659 |
save_base = mem_base ? mem_base : io_base; |
660 |
register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s); |
661 |
|
662 |
return s;
|
663 |
} |