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target-sparc: Add accessors for single-precision fpr access.
Load, store, and "create destination". This version attempts tochange the behaviour of the translator as little as possible. Wepreviously used cpu_tmp32 as the temporary destination, and we...
Sparc: avoid AREG0 for division op helpers
Make [su]div{,cc} helpers take a parameter for CPUState insteadof relying on global env. Move the functions to helper.c.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Sparc: avoid AREG0 for softint op helpers and Leon cache control
Make softint op helpers and Leon cache irq manager take a parameterfor CPUState instead of relying on global env. Move the functionsto int{32,64}_helper.c.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
Sparc: avoid AREG0 for CWP and PSTATE helpers
Make CWP and PSTATE helpers take a parameter for CPUState insteadof relying on global env. Remove wrapper functions.
target-sparc: Fix order of function parameters
The MinGW-w64 gcc complains about wrong parameters forgen_helper_fpadd16_s and three other functions.
gen_helper_fpadd16_s is declared like this (hidden in lots of macros):
static inline void gen_helper_fpadd16s(TCGv_i32 retval, TCGv_ptr arg1,...
Sparc: avoid AREG0 for lazy condition code helpers
Make lazy condition code helpers take a parameter for CPUState insteadof relying on global env.
Sparc: avoid AREG0 for float and VIS ops
Make floating point and VIS ops take a parameter for CPUState insteadof relying on global env.
Sparc: avoid AREG0 for raise_exception and helper_debug
Make raise_exception() and helper_debug() take a parameter forCPUState instead of relying on global env. Move the functionsto helper.c.
Fix handling of conditional branches in delay slot of a conditional branch
Check whether dc->npc is dynamic before using its value for branch.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
SPARC64: fix fnor* and fnand*
Fix the problem that result values are not assigned to the destinationregisters.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
SPARC64: implement %fprs dirty bits
Implement %fprs.DU/DL bits.The FPU sets %fprs.DL and %fprs.DU when values are assigned to %f0-31and %f32-63 respectively.
SPARC64: add missing break on fmovdcc
"break" is missing on V9 fmovdcc (%icc).
SPARC64: fix VIS1 SIMD signed compare instructions
The destination registers of SIMD signed compare instructions(fcmp*<16|32>) are not FP registers but general purpose r registers.Comparisons should be freg_rs1 CMP freg_rs2, that were reversed.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>...
Sparc: fix FPU and AM enable checks for translation
Translation used incorrectly CPUState fields directly to checkfor FPU enable state and 32 bit address masking on Sparc64.
Fix by using TB flags instead.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
SPARC64: fp_disabled checks on stfa/stdfa/stqfa
stfa/stdfa/stqfa instructions should raise fp_disabled exceptionsif %pstate.PEF==0 or %fprs.FEF==0.
SPARC64: Implement stfa/stdfa/stqfa instrcutions properly
This patch implements sparcv9 stfa/stdfa/stqfa instructionswith non block-store ASIs.
SPARC64: fp_disabled checks on ldfa/lddfa/ldqfa
ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptionsif %pstate.PEF==0 or %fprs.FEF==0.
fix cpu_cc_src and cpu_cc_src2 corruption in udivx and sdivx
udivx and sdvix don't modify condition flags, so they shall notoverwrite cpu_cc_*
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Delete unused tb_invalidate_page_range
tb_invalidate_page_range() was intended to be used to invalidate anarea of a TB which the guest explicitly flushes from i-cache. However,QEMU detects writes to code areas where TBs have been generated, sohis has never been useful....
sparc64: fix incorrect BPcc target sign extension
Fix wrong number of bits used when sign extending the branch offset of BPccinstructions.
Reported-by: Artyom Tarasenko <atar4qemu@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64: fix wrpstate and wrtl on delay slot
Use TCG local to work around TCG register flush due to a branch.
Thanks to Artyom Tarasenko, Igor Kovalenko and Aurelien Jarno.
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
SPARC: Emulation of Leon3
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (moreinformation on http://www.gaisler.com).
Leon3 is made of multiple components available in the GrLib VHDL library.Three devices are implemented: uart, timers and IRQ manager....
SPARC: Add asr17 register support
This register is activated by CPU_FEATURE_ASR17 in the feature field.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: fix udiv(cc) and sdiv(cc)
Since commit 5a4bb580cdb10b066f9fd67658b31cac4a4ea5e5, Xorg crashes ona Debian Etch image. The commit itself is fine, but it triggers a bugdue to wrong computation of flags for udiv(cc) and sdiv(cc).
This patch only compute cc_src2 for the cc version of udiv/sdiv. It...
sparc64: fix umul and smul insns
- truncate and sign or zero extend operands before multiplication- factor out common code to gen_op_multiply() with parameter to sign/zero extend- call gen_op_multiply from gen_op_umul and gen_op_smul
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>...
sparc64: fix ldxfsr insn
- rearrange code to break from switch when appropriate- allow deprecated ldfsr insn
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64: fix missing address masking v1
- address masking for ldqf and stqf insns- address masking for lddf and stdf insns- address masking for translating ASI (Ultrasparc IIi)v0->v1:- move arch-specific code to helpers and drop more ifdefs at call sites...
sparc64: fix mmu context at trap levels above zero
- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero- cpu_get_tb_cpu_state: store trap level and primary context in flags this allows to restart code translation when address translation is changed...
sparc64: fix pstate privilege bits
- refactor code to handle hpstate only if available for current cpu- conditionally set hypervisor bit in hpstate register- reorder softmmu indices so user accessable ones go first, translation context macros supervisor() and hypervisor() adjusted as well...
target-sparc: Inline some generation of carry for ADDX/SUBX.
Computing carry is trivial for some inputs. By avoiding anexternal function call, we generate near-optimal code forthe common cases of add+addx (double-word arithmetic) andcmp+addx (a setcc pattern)....
sparc: lazy C flag calculation
Calculate only the carry flag for ADDX/SUBX instead of fullset of flags.
Thanks to Igor Kovalenko for spotting a bug with an earlierversion.
target-sparc: Fix -singlestep.
Single-stepping was not properly updating npc, resulting in someinstructions being executed twice. In addition, we were emittingdead code at the end of the TB.
Fix both by teaching gen_goto_tb to avoid goto_tb for single-step...
Fix harmless if statements with empty body, spotted by clang
These clang errors are harmless but worth fixing: CC ppc-softmmu/usb-ohci.o/src/qemu/hw/usb-ohci.c:1104:59: error: if statement has empty body [-Wempty-body] ohci->ctrl_head, ohci->ctrl_cur);...
target-sparc: Free instruction temporaries.
Rather than creating new temporaries for constants, use theones created in disas_sparc_insn. Remember the temps createdthere so that they can be freed at the end of the function.
Profile data collected by TCG while booting sparc-test kernel:...
Sparc: fix PC/NPC during FPU traps
All FPU instructions can trap, so save PC/NPC state beforeexecuting them.
Sparc: fix exceptions in delay slot
Fix a case where an exception happens with theinstruction in the delay slot.
Recovery of branch condition in the exception handlingcode was not converted to TCG. Because the conditionwas bogus, wrong NPC could be selected from the two...
remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-sparc: fix --enable-debug build for 64 bit host
b551ec04ca45d1925417dd2ec7c1b7f115c84f1d fixedthe compilation for 32 bit hosts, but introduceda new error for 64 bit hosts:
tcg_temp_new_ptr needs a matching tcg_temp_free_ptr.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
target-sparc: fix --enable-debug build
Use 32-bit arithmetic for the address offset calculation to fix abuild failure on 32-bit hosts.
Signed-off-by: Jay Foad <jay.foad@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64: use helper_wrpil to check pending irq on write
sparc64-8bit-asi
Sparc64 alternate space load/store helpers expect 8 bit ASI value,while wrasi implementation sign-extends ASI operand causingfor example 0x80 to appear as 0xFFFFFF80. Resulting value fallsout of switch in helpers and causes obscure load/store faults....
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
Sparc32/64: fix jmpl followed by branch
Fix a case where 'jmpl' instruction followed by a branch instruction washandled incorrectly.
Fix desynchronization of condition code state when a memory access traps
Sparc64: replace tsptr with helper routine
tl and tsptr of members sparc64 cpu state must be changedsimultaneously to keep trap state window in sync with currenttrap level. Currently translation of store to tl does not changetsptr, which leads to corrupt trap state on corresponding...
sparc64 flush pending conditional evaluations before exposing cpu state
If translation block is interrupted by e.g. mmu exceptionwe need to compute conditional flags for inclusion intosaved cpu state. Otherwise after return from trapconditional instructions would use stale psr/xcc data....
Update to a hopefully more future proof FSF address
Use correct type for SPARC cpu_cc_op
Signed-off-by: Paul Brook <paul@codesourcery.com>
Convert mulscc
Convert udiv/sdiv
Convert tagged ops
Convert logical operations and umul/smul
Convert sub
Convert subx
Convert addx
Convert add
Use dynamical computation for condition codes
Optimize cmp x, 0 case
Reindent
Improve instruction name comments for easier searching
Optimize operations with immediate parameters
Fix Sparc64 sign extension problems
Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and addsthis feature to targets which did not have a compile time option.
Add monitor command to enable or disable single step mode.
Modify monitor command "info status" to display single step mode....
Delete some unused macros detected with -Wp,-Wunused-macros use
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6856 c046a42c-6fe2-441c-8c8c-71466251a162
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying thecode and also fixing a use after release issue incpu_break/watchpoint_remove_all.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
Refactor and enhance break/watchpoint API (Jan Kiszka)
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow thesucceeding enhancements this series comes with.
First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switchingto dynamically allocated data structures that are kept in linked lists....
TCG variable type checking.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
Use TCG not op
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5663 c046a42c-6fe2-441c-8c8c-71466251a162
Use andc, orc, nor and nandAlso fix which argument gets negated in fandnot12 and fornot12
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5662 c046a42c-6fe2-441c-8c8c-71466251a162
Fix TCGv size mismatches
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5593 c046a42c-6fe2-441c-8c8c-71466251a162
Implement UA2005 hypervisor traps
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5327 c046a42c-6fe2-441c-8c8c-71466251a162
Add software and timer interrupt support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5299 c046a42c-6fe2-441c-8c8c-71466251a162
Use the new concat_tl_i64 op for std and stda
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5283 c046a42c-6fe2-441c-8c8c-71466251a162
Use the new concat_i32_i64 op for std and stda
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5281 c046a42c-6fe2-441c-8c8c-71466251a162
Fix mulscc with high bits set in either src1 or src2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5201 c046a42c-6fe2-441c-8c8c-71466251a162
Write zeros to high bits of y, based on patch by Vince Weaver
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5196 c046a42c-6fe2-441c-8c8c-71466251a162
Convert rest of ops using float32 to TCG, remove FT0 and FT1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
Partially convert float128 conversion ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162
Convert basic 64 bit VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162
Convert basic 32 bit VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162
Convert basic float32 ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5189 c046a42c-6fe2-441c-8c8c-71466251a162
Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
Fix a typo in fpsub32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5177 c046a42c-6fe2-441c-8c8c-71466251a162
Convert most env fields to TCG registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5176 c046a42c-6fe2-441c-8c8c-71466251a162
Silence gcc warning about constant overflow
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5175 c046a42c-6fe2-441c-8c8c-71466251a162
Fix sign extension problems with smul and umul (Vince Weaver)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5138 c046a42c-6fe2-441c-8c8c-71466251a162
Fix y register loads and stores
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5123 c046a42c-6fe2-441c-8c8c-71466251a162
Fix FCC handling for Sparc64 target, initial patch by Vince Weaver
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5110 c046a42c-6fe2-441c-8c8c-71466251a162
Fix wrwim masking (Luis Pureza)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5043 c046a42c-6fe2-441c-8c8c-71466251a162
Use initial CPU definition structure for some CPU fields instead of copyingthem around, based on patch by Luis Pureza.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5042 c046a42c-6fe2-441c-8c8c-71466251a162
Correct 32bit carry flag for add instruction (Igor Kovalenko)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5017 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc64 shifts
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4990 c046a42c-6fe2-441c-8c8c-71466251a162
Fix offset handling for ASI loads and stores (Vince Weaver)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4988 c046a42c-6fe2-441c-8c8c-71466251a162
Fix cmp/subcc/addcc op bugs reported by Vince Weaver
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4970 c046a42c-6fe2-441c-8c8c-71466251a162