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net/cadence_gem: Don't assert against 0 buffer address
This has no real hardware analog and asserting correctness of DMAaddresses is not a perhiperal level problem. Delete.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Message-id: fc02417eb1874cb05e4f20531c6203c5a00110f1.1386136219.git.peter.crosthwaite@xilinx.com...
net/cadence_gem: simplify rx buf descriptor walking
There was a replication of the rx descriptor address walking logic.Reorder the flow control to remove. This refactoring also obsoletesthe local variables packet_desc_addr and last_desc_addr.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
net/cadence_gem: Prefetch rx descriptors ASAP
The real hardware prefetches rx buffer descriptors ASAP andpotentially throws relevant interrupts following the fetcheven in the absence of a received packet.
Reported-by: Deepika Dhamija <deepika@xilinx.com>...
net/cadence_gem: Implement RX descriptor match mode flags
The various Rx packet address matching mode flags were not being set inthe rx descriptor. Implement.
Reported-by: Deepika Dhamija <deepika@xilinx.com>Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
net/cadence_gem: Implement SAR match bit in rx desc
Bit 27 of the RX buffer desc word 1 should be set when the packet wasaccepted due to specific address register match. Implement.
This feature is absent from the Xilinx documentation (UG585) but thebehaviour is tested as accurate on real hardware....
net/cadence_gem: Implement SAR (de)activation
The Specific address registers can be enabled or disabled by software.QEMU was assuming they were always enabled. Implement thedisable/enable feature. SARs are disabled by writing to the lower halfregister. They are re-enabled by then writing the upper half....
net/cadence_gem: Add missing VMSTATE_END_OF_LIST
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Message-id: 8f8c2bfb15f40fb5f0d5766aa4cd3d54c596de6a.1386136219.git.peter.crosthwaite@xilinx.comSigned-off-by: Peter Maydell <peter.maydell@linaro.org>
net/cadence_gem: Fix rx multi-fragment packets
Bytes_to_copy was being updated before its final use where itadvances the rx buffer pointer. This was causing total mayhem,where packet data for any subsequent fragments was being fetchedfrom the wrong place....
net/cadence_gem: Fix small packet FCS stripping
The minimum packet size is 64, however this is before FCS strippingoccurs. So when FCS stripping the minimum packet size is 60. Fix.
net/cadence_gem: Fix register w1c logic
This write-1-clear logic was incorrect. It was always clearing w1cbits regardless of whether the written value was 1 or not. i.e. itwas implementing a write-anything-to-clear strategy.
net/cadence_gem: Improve can_receive debug printfery
Currently this just floods indicating that can_receive has been calledby the net framework. Instead, save the result of the most recentcan_receive callback as state and only print a message if the result...
net/cadence_gem: Don't rx packets when no rx buffer available
Return false from can_receive() when no valid buffer descriptor isavailable. Ensures against mass packet droppage in some applications.
net/cadence_gem: Implement mac level loopback mode
Cadence GEM has a MAC level loopback mode. Implement. Use the same basicoperation as the already implemented PHY loopback.
net/cadence_gem: Update DMA rx descriptors as we process them
We were updating the ownership bit of all descriptors if packetsget split and written through several descriptors.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
cadence_gem: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
hw/n*: pass owner to memory_region_init* functions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
memory: add owner argument to initialization functions
hw: move target-independent files to subdirectories
This patch tackles all files that are compiled once, movingthem to subdirectories of hw/.