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1 | e8af50a3 | bellard | /*
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2 | e8af50a3 | bellard | * sparc helpers
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3 | 5fafdf24 | ths | *
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4 | 83469015 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | e8af50a3 | bellard | *
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6 | e8af50a3 | bellard | * This library is free software; you can redistribute it and/or
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7 | e8af50a3 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | e8af50a3 | bellard | * License as published by the Free Software Foundation; either
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9 | e8af50a3 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | e8af50a3 | bellard | *
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11 | e8af50a3 | bellard | * This library is distributed in the hope that it will be useful,
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12 | e8af50a3 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | e8af50a3 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | e8af50a3 | bellard | * Lesser General Public License for more details.
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15 | e8af50a3 | bellard | *
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16 | e8af50a3 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | e8af50a3 | bellard | * License along with this library; if not, write to the Free Software
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18 | e8af50a3 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | e8af50a3 | bellard | */
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20 | ee5bbe38 | bellard | #include <stdarg.h> |
21 | ee5bbe38 | bellard | #include <stdlib.h> |
22 | ee5bbe38 | bellard | #include <stdio.h> |
23 | ee5bbe38 | bellard | #include <string.h> |
24 | ee5bbe38 | bellard | #include <inttypes.h> |
25 | ee5bbe38 | bellard | #include <signal.h> |
26 | ee5bbe38 | bellard | #include <assert.h> |
27 | ee5bbe38 | bellard | |
28 | ee5bbe38 | bellard | #include "cpu.h" |
29 | ee5bbe38 | bellard | #include "exec-all.h" |
30 | ca10f867 | aurel32 | #include "qemu-common.h" |
31 | e8af50a3 | bellard | |
32 | e80cfcfc | bellard | //#define DEBUG_MMU
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33 | e8af50a3 | bellard | |
34 | c48fcb47 | blueswir1 | typedef struct sparc_def_t sparc_def_t; |
35 | c48fcb47 | blueswir1 | |
36 | c48fcb47 | blueswir1 | struct sparc_def_t {
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37 | c48fcb47 | blueswir1 | const unsigned char *name; |
38 | c48fcb47 | blueswir1 | target_ulong iu_version; |
39 | c48fcb47 | blueswir1 | uint32_t fpu_version; |
40 | c48fcb47 | blueswir1 | uint32_t mmu_version; |
41 | c48fcb47 | blueswir1 | uint32_t mmu_bm; |
42 | c48fcb47 | blueswir1 | uint32_t mmu_ctpr_mask; |
43 | c48fcb47 | blueswir1 | uint32_t mmu_cxr_mask; |
44 | c48fcb47 | blueswir1 | uint32_t mmu_sfsr_mask; |
45 | c48fcb47 | blueswir1 | uint32_t mmu_trcr_mask; |
46 | c48fcb47 | blueswir1 | }; |
47 | c48fcb47 | blueswir1 | |
48 | c48fcb47 | blueswir1 | static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name); |
49 | c48fcb47 | blueswir1 | |
50 | e8af50a3 | bellard | /* Sparc MMU emulation */
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51 | e8af50a3 | bellard | |
52 | e8af50a3 | bellard | /* thread support */
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53 | e8af50a3 | bellard | |
54 | e8af50a3 | bellard | spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
55 | e8af50a3 | bellard | |
56 | e8af50a3 | bellard | void cpu_lock(void) |
57 | e8af50a3 | bellard | { |
58 | e8af50a3 | bellard | spin_lock(&global_cpu_lock); |
59 | e8af50a3 | bellard | } |
60 | e8af50a3 | bellard | |
61 | e8af50a3 | bellard | void cpu_unlock(void) |
62 | e8af50a3 | bellard | { |
63 | e8af50a3 | bellard | spin_unlock(&global_cpu_lock); |
64 | e8af50a3 | bellard | } |
65 | e8af50a3 | bellard | |
66 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
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67 | 9d893301 | bellard | |
68 | 9d893301 | bellard | int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
69 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
70 | 9d893301 | bellard | { |
71 | 878d3096 | bellard | if (rw & 2) |
72 | 878d3096 | bellard | env->exception_index = TT_TFAULT; |
73 | 878d3096 | bellard | else
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74 | 878d3096 | bellard | env->exception_index = TT_DFAULT; |
75 | 9d893301 | bellard | return 1; |
76 | 9d893301 | bellard | } |
77 | 9d893301 | bellard | |
78 | 9d893301 | bellard | #else
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79 | e8af50a3 | bellard | |
80 | 3475187d | bellard | #ifndef TARGET_SPARC64
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81 | 83469015 | bellard | /*
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82 | 83469015 | bellard | * Sparc V8 Reference MMU (SRMMU)
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83 | 83469015 | bellard | */
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84 | e8af50a3 | bellard | static const int access_table[8][8] = { |
85 | e8af50a3 | bellard | { 0, 0, 0, 0, 2, 0, 3, 3 }, |
86 | e8af50a3 | bellard | { 0, 0, 0, 0, 2, 0, 0, 0 }, |
87 | e8af50a3 | bellard | { 2, 2, 0, 0, 0, 2, 3, 3 }, |
88 | e8af50a3 | bellard | { 2, 2, 0, 0, 0, 2, 0, 0 }, |
89 | e8af50a3 | bellard | { 2, 0, 2, 0, 2, 2, 3, 3 }, |
90 | e8af50a3 | bellard | { 2, 0, 2, 0, 2, 0, 2, 0 }, |
91 | e8af50a3 | bellard | { 2, 2, 2, 0, 2, 2, 3, 3 }, |
92 | e8af50a3 | bellard | { 2, 2, 2, 0, 2, 2, 2, 0 } |
93 | e8af50a3 | bellard | }; |
94 | e8af50a3 | bellard | |
95 | 227671c9 | bellard | static const int perm_table[2][8] = { |
96 | 227671c9 | bellard | { |
97 | 227671c9 | bellard | PAGE_READ, |
98 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE, |
99 | 227671c9 | bellard | PAGE_READ | PAGE_EXEC, |
100 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
101 | 227671c9 | bellard | PAGE_EXEC, |
102 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE, |
103 | 227671c9 | bellard | PAGE_READ | PAGE_EXEC, |
104 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE | PAGE_EXEC |
105 | 227671c9 | bellard | }, |
106 | 227671c9 | bellard | { |
107 | 227671c9 | bellard | PAGE_READ, |
108 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE, |
109 | 227671c9 | bellard | PAGE_READ | PAGE_EXEC, |
110 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
111 | 227671c9 | bellard | PAGE_EXEC, |
112 | 227671c9 | bellard | PAGE_READ, |
113 | 227671c9 | bellard | 0,
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114 | 227671c9 | bellard | 0,
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115 | 227671c9 | bellard | } |
116 | e8af50a3 | bellard | }; |
117 | e8af50a3 | bellard | |
118 | c48fcb47 | blueswir1 | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
119 | c48fcb47 | blueswir1 | int *prot, int *access_index, |
120 | c48fcb47 | blueswir1 | target_ulong address, int rw, int mmu_idx) |
121 | e8af50a3 | bellard | { |
122 | e80cfcfc | bellard | int access_perms = 0; |
123 | e80cfcfc | bellard | target_phys_addr_t pde_ptr; |
124 | af7bf89b | bellard | uint32_t pde; |
125 | af7bf89b | bellard | target_ulong virt_addr; |
126 | 6ebbf390 | j_mayer | int error_code = 0, is_dirty, is_user; |
127 | e80cfcfc | bellard | unsigned long page_offset; |
128 | e8af50a3 | bellard | |
129 | 6ebbf390 | j_mayer | is_user = mmu_idx == MMU_USER_IDX; |
130 | e8af50a3 | bellard | virt_addr = address & TARGET_PAGE_MASK; |
131 | 40ce0a9a | blueswir1 | |
132 | e8af50a3 | bellard | if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
133 | 40ce0a9a | blueswir1 | // Boot mode: instruction fetches are taken from PROM
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134 | 6d5f237a | blueswir1 | if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) { |
135 | 58a770f3 | blueswir1 | *physical = env->prom_addr | (address & 0x7ffffULL);
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136 | 40ce0a9a | blueswir1 | *prot = PAGE_READ | PAGE_EXEC; |
137 | 40ce0a9a | blueswir1 | return 0; |
138 | 40ce0a9a | blueswir1 | } |
139 | 0f8a249a | blueswir1 | *physical = address; |
140 | 227671c9 | bellard | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
141 | e80cfcfc | bellard | return 0; |
142 | e8af50a3 | bellard | } |
143 | e8af50a3 | bellard | |
144 | 7483750d | bellard | *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
145 | 5dcb6b91 | blueswir1 | *physical = 0xffffffffffff0000ULL;
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146 | 7483750d | bellard | |
147 | e8af50a3 | bellard | /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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148 | e8af50a3 | bellard | /* Context base + context number */
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149 | 3deaeab7 | blueswir1 | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
150 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
151 | e8af50a3 | bellard | |
152 | e8af50a3 | bellard | /* Ctx pde */
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153 | e8af50a3 | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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154 | e80cfcfc | bellard | default:
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155 | e8af50a3 | bellard | case 0: /* Invalid */ |
156 | 0f8a249a | blueswir1 | return 1 << 2; |
157 | e80cfcfc | bellard | case 2: /* L0 PTE, maybe should not happen? */ |
158 | e8af50a3 | bellard | case 3: /* Reserved */ |
159 | 7483750d | bellard | return 4 << 2; |
160 | e80cfcfc | bellard | case 1: /* L0 PDE */ |
161 | 0f8a249a | blueswir1 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
162 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
163 | e8af50a3 | bellard | |
164 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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165 | 0f8a249a | blueswir1 | default:
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166 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
167 | 0f8a249a | blueswir1 | return (1 << 8) | (1 << 2); |
168 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
169 | 0f8a249a | blueswir1 | return (1 << 8) | (4 << 2); |
170 | 0f8a249a | blueswir1 | case 1: /* L1 PDE */ |
171 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
172 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
173 | e8af50a3 | bellard | |
174 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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175 | 0f8a249a | blueswir1 | default:
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176 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
177 | 0f8a249a | blueswir1 | return (2 << 8) | (1 << 2); |
178 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
179 | 0f8a249a | blueswir1 | return (2 << 8) | (4 << 2); |
180 | 0f8a249a | blueswir1 | case 1: /* L2 PDE */ |
181 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
182 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
183 | e8af50a3 | bellard | |
184 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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185 | 0f8a249a | blueswir1 | default:
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186 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
187 | 0f8a249a | blueswir1 | return (3 << 8) | (1 << 2); |
188 | 0f8a249a | blueswir1 | case 1: /* PDE, should not happen */ |
189 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
190 | 0f8a249a | blueswir1 | return (3 << 8) | (4 << 2); |
191 | 0f8a249a | blueswir1 | case 2: /* L3 PTE */ |
192 | 0f8a249a | blueswir1 | virt_addr = address & TARGET_PAGE_MASK; |
193 | 0f8a249a | blueswir1 | page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
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194 | 0f8a249a | blueswir1 | } |
195 | 0f8a249a | blueswir1 | break;
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196 | 0f8a249a | blueswir1 | case 2: /* L2 PTE */ |
197 | 0f8a249a | blueswir1 | virt_addr = address & ~0x3ffff;
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198 | 0f8a249a | blueswir1 | page_offset = address & 0x3ffff;
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199 | 0f8a249a | blueswir1 | } |
200 | 0f8a249a | blueswir1 | break;
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201 | 0f8a249a | blueswir1 | case 2: /* L1 PTE */ |
202 | 0f8a249a | blueswir1 | virt_addr = address & ~0xffffff;
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203 | 0f8a249a | blueswir1 | page_offset = address & 0xffffff;
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204 | 0f8a249a | blueswir1 | } |
205 | e8af50a3 | bellard | } |
206 | e8af50a3 | bellard | |
207 | e8af50a3 | bellard | /* update page modified and dirty bits */
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208 | b769d8fe | bellard | is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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209 | e8af50a3 | bellard | if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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210 | 0f8a249a | blueswir1 | pde |= PG_ACCESSED_MASK; |
211 | 0f8a249a | blueswir1 | if (is_dirty)
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212 | 0f8a249a | blueswir1 | pde |= PG_MODIFIED_MASK; |
213 | 49be8030 | bellard | stl_phys_notdirty(pde_ptr, pde); |
214 | e8af50a3 | bellard | } |
215 | e8af50a3 | bellard | /* check access */
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216 | e8af50a3 | bellard | access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
217 | e80cfcfc | bellard | error_code = access_table[*access_index][access_perms]; |
218 | d8e3326c | bellard | if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) |
219 | 0f8a249a | blueswir1 | return error_code;
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220 | e8af50a3 | bellard | |
221 | e8af50a3 | bellard | /* the page can be put in the TLB */
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222 | 227671c9 | bellard | *prot = perm_table[is_user][access_perms]; |
223 | 227671c9 | bellard | if (!(pde & PG_MODIFIED_MASK)) {
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224 | e8af50a3 | bellard | /* only set write access if already dirty... otherwise wait
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225 | e8af50a3 | bellard | for dirty access */
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226 | 227671c9 | bellard | *prot &= ~PAGE_WRITE; |
227 | e8af50a3 | bellard | } |
228 | e8af50a3 | bellard | |
229 | e8af50a3 | bellard | /* Even if large ptes, we map only one 4KB page in the cache to
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230 | e8af50a3 | bellard | avoid filling it too fast */
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231 | 5dcb6b91 | blueswir1 | *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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232 | 6f7e9aec | bellard | return error_code;
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233 | e80cfcfc | bellard | } |
234 | e80cfcfc | bellard | |
235 | e80cfcfc | bellard | /* Perform address translation */
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236 | af7bf89b | bellard | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
237 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
238 | e80cfcfc | bellard | { |
239 | af7bf89b | bellard | target_phys_addr_t paddr; |
240 | 5dcb6b91 | blueswir1 | target_ulong vaddr; |
241 | e80cfcfc | bellard | int error_code = 0, prot, ret = 0, access_index; |
242 | e8af50a3 | bellard | |
243 | 6ebbf390 | j_mayer | error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx); |
244 | e80cfcfc | bellard | if (error_code == 0) { |
245 | 0f8a249a | blueswir1 | vaddr = address & TARGET_PAGE_MASK; |
246 | 0f8a249a | blueswir1 | paddr &= TARGET_PAGE_MASK; |
247 | 9e61bde5 | bellard | #ifdef DEBUG_MMU
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248 | 0f8a249a | blueswir1 | printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
249 | 5dcb6b91 | blueswir1 | TARGET_FMT_lx "\n", address, paddr, vaddr);
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250 | 9e61bde5 | bellard | #endif
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251 | 6ebbf390 | j_mayer | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
252 | 0f8a249a | blueswir1 | return ret;
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253 | e80cfcfc | bellard | } |
254 | e8af50a3 | bellard | |
255 | e8af50a3 | bellard | if (env->mmuregs[3]) /* Fault status register */ |
256 | 0f8a249a | blueswir1 | env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
257 | 7483750d | bellard | env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
258 | e8af50a3 | bellard | env->mmuregs[4] = address; /* Fault address register */ |
259 | e8af50a3 | bellard | |
260 | 878d3096 | bellard | if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
261 | 6f7e9aec | bellard | // No fault mode: if a mapping is available, just override
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262 | 6f7e9aec | bellard | // permissions. If no mapping is available, redirect accesses to
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263 | 6f7e9aec | bellard | // neverland. Fake/overridden mappings will be flushed when
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264 | 6f7e9aec | bellard | // switching to normal mode.
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265 | 0f8a249a | blueswir1 | vaddr = address & TARGET_PAGE_MASK; |
266 | 227671c9 | bellard | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
267 | 6ebbf390 | j_mayer | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
268 | 0f8a249a | blueswir1 | return ret;
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269 | 7483750d | bellard | } else {
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270 | 7483750d | bellard | if (rw & 2) |
271 | 7483750d | bellard | env->exception_index = TT_TFAULT; |
272 | 7483750d | bellard | else
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273 | 7483750d | bellard | env->exception_index = TT_DFAULT; |
274 | 7483750d | bellard | return 1; |
275 | 878d3096 | bellard | } |
276 | e8af50a3 | bellard | } |
277 | 24741ef3 | bellard | |
278 | 24741ef3 | bellard | target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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279 | 24741ef3 | bellard | { |
280 | 24741ef3 | bellard | target_phys_addr_t pde_ptr; |
281 | 24741ef3 | bellard | uint32_t pde; |
282 | 24741ef3 | bellard | |
283 | 24741ef3 | bellard | /* Context base + context number */
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284 | 5dcb6b91 | blueswir1 | pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
285 | 5dcb6b91 | blueswir1 | (env->mmuregs[2] << 2); |
286 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
287 | 24741ef3 | bellard | |
288 | 24741ef3 | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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289 | 24741ef3 | bellard | default:
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290 | 24741ef3 | bellard | case 0: /* Invalid */ |
291 | 24741ef3 | bellard | case 2: /* PTE, maybe should not happen? */ |
292 | 24741ef3 | bellard | case 3: /* Reserved */ |
293 | 0f8a249a | blueswir1 | return 0; |
294 | 24741ef3 | bellard | case 1: /* L1 PDE */ |
295 | 0f8a249a | blueswir1 | if (mmulev == 3) |
296 | 0f8a249a | blueswir1 | return pde;
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297 | 0f8a249a | blueswir1 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
298 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
299 | 24741ef3 | bellard | |
300 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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301 | 0f8a249a | blueswir1 | default:
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302 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
303 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
304 | 0f8a249a | blueswir1 | return 0; |
305 | 0f8a249a | blueswir1 | case 2: /* L1 PTE */ |
306 | 0f8a249a | blueswir1 | return pde;
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307 | 0f8a249a | blueswir1 | case 1: /* L2 PDE */ |
308 | 0f8a249a | blueswir1 | if (mmulev == 2) |
309 | 0f8a249a | blueswir1 | return pde;
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310 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
311 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
312 | 24741ef3 | bellard | |
313 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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314 | 0f8a249a | blueswir1 | default:
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315 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
316 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
317 | 0f8a249a | blueswir1 | return 0; |
318 | 0f8a249a | blueswir1 | case 2: /* L2 PTE */ |
319 | 0f8a249a | blueswir1 | return pde;
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320 | 0f8a249a | blueswir1 | case 1: /* L3 PDE */ |
321 | 0f8a249a | blueswir1 | if (mmulev == 1) |
322 | 0f8a249a | blueswir1 | return pde;
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323 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
324 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
325 | 24741ef3 | bellard | |
326 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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327 | 0f8a249a | blueswir1 | default:
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328 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
329 | 0f8a249a | blueswir1 | case 1: /* PDE, should not happen */ |
330 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
331 | 0f8a249a | blueswir1 | return 0; |
332 | 0f8a249a | blueswir1 | case 2: /* L3 PTE */ |
333 | 0f8a249a | blueswir1 | return pde;
|
334 | 0f8a249a | blueswir1 | } |
335 | 0f8a249a | blueswir1 | } |
336 | 0f8a249a | blueswir1 | } |
337 | 24741ef3 | bellard | } |
338 | 24741ef3 | bellard | return 0; |
339 | 24741ef3 | bellard | } |
340 | 24741ef3 | bellard | |
341 | 24741ef3 | bellard | #ifdef DEBUG_MMU
|
342 | 24741ef3 | bellard | void dump_mmu(CPUState *env)
|
343 | 24741ef3 | bellard | { |
344 | 5dcb6b91 | blueswir1 | target_ulong va, va1, va2; |
345 | 5dcb6b91 | blueswir1 | unsigned int n, m, o; |
346 | 5dcb6b91 | blueswir1 | target_phys_addr_t pde_ptr, pa; |
347 | 24741ef3 | bellard | uint32_t pde; |
348 | 24741ef3 | bellard | |
349 | 24741ef3 | bellard | printf("MMU dump:\n");
|
350 | 24741ef3 | bellard | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
351 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
352 | 5dcb6b91 | blueswir1 | printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
353 | 5dcb6b91 | blueswir1 | (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); |
354 | 24741ef3 | bellard | for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
355 | 0f8a249a | blueswir1 | pde = mmu_probe(env, va, 2);
|
356 | 0f8a249a | blueswir1 | if (pde) {
|
357 | 0f8a249a | blueswir1 | pa = cpu_get_phys_page_debug(env, va); |
358 | 0f8a249a | blueswir1 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
359 | 5dcb6b91 | blueswir1 | " PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
360 | 0f8a249a | blueswir1 | for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
361 | 0f8a249a | blueswir1 | pde = mmu_probe(env, va1, 1);
|
362 | 0f8a249a | blueswir1 | if (pde) {
|
363 | 0f8a249a | blueswir1 | pa = cpu_get_phys_page_debug(env, va1); |
364 | 0f8a249a | blueswir1 | printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
365 | 5dcb6b91 | blueswir1 | " PDE: " TARGET_FMT_lx "\n", va1, pa, pde); |
366 | 0f8a249a | blueswir1 | for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
367 | 0f8a249a | blueswir1 | pde = mmu_probe(env, va2, 0);
|
368 | 0f8a249a | blueswir1 | if (pde) {
|
369 | 0f8a249a | blueswir1 | pa = cpu_get_phys_page_debug(env, va2); |
370 | 0f8a249a | blueswir1 | printf(" VA: " TARGET_FMT_lx ", PA: " |
371 | 5dcb6b91 | blueswir1 | TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", |
372 | 5dcb6b91 | blueswir1 | va2, pa, pde); |
373 | 0f8a249a | blueswir1 | } |
374 | 0f8a249a | blueswir1 | } |
375 | 0f8a249a | blueswir1 | } |
376 | 0f8a249a | blueswir1 | } |
377 | 0f8a249a | blueswir1 | } |
378 | 24741ef3 | bellard | } |
379 | 24741ef3 | bellard | printf("MMU dump ends\n");
|
380 | 24741ef3 | bellard | } |
381 | 24741ef3 | bellard | #endif /* DEBUG_MMU */ |
382 | 24741ef3 | bellard | |
383 | 24741ef3 | bellard | #else /* !TARGET_SPARC64 */ |
384 | 83469015 | bellard | /*
|
385 | 83469015 | bellard | * UltraSparc IIi I/DMMUs
|
386 | 83469015 | bellard | */
|
387 | 3475187d | bellard | static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot, |
388 | 0f8a249a | blueswir1 | int *access_index, target_ulong address, int rw, |
389 | 0f8a249a | blueswir1 | int is_user)
|
390 | 3475187d | bellard | { |
391 | 3475187d | bellard | target_ulong mask; |
392 | 3475187d | bellard | unsigned int i; |
393 | 3475187d | bellard | |
394 | 3475187d | bellard | if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ |
395 | 0f8a249a | blueswir1 | *physical = address; |
396 | 0f8a249a | blueswir1 | *prot = PAGE_READ | PAGE_WRITE; |
397 | 3475187d | bellard | return 0; |
398 | 3475187d | bellard | } |
399 | 3475187d | bellard | |
400 | 3475187d | bellard | for (i = 0; i < 64; i++) { |
401 | 0f8a249a | blueswir1 | switch ((env->dtlb_tte[i] >> 61) & 3) { |
402 | 0f8a249a | blueswir1 | default:
|
403 | 0f8a249a | blueswir1 | case 0x0: // 8k |
404 | 0f8a249a | blueswir1 | mask = 0xffffffffffffe000ULL;
|
405 | 0f8a249a | blueswir1 | break;
|
406 | 0f8a249a | blueswir1 | case 0x1: // 64k |
407 | 0f8a249a | blueswir1 | mask = 0xffffffffffff0000ULL;
|
408 | 0f8a249a | blueswir1 | break;
|
409 | 0f8a249a | blueswir1 | case 0x2: // 512k |
410 | 0f8a249a | blueswir1 | mask = 0xfffffffffff80000ULL;
|
411 | 0f8a249a | blueswir1 | break;
|
412 | 0f8a249a | blueswir1 | case 0x3: // 4M |
413 | 0f8a249a | blueswir1 | mask = 0xffffffffffc00000ULL;
|
414 | 0f8a249a | blueswir1 | break;
|
415 | 0f8a249a | blueswir1 | } |
416 | 0f8a249a | blueswir1 | // ctx match, vaddr match?
|
417 | 0f8a249a | blueswir1 | if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
418 | 0f8a249a | blueswir1 | (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
|
419 | 0f8a249a | blueswir1 | // valid, access ok?
|
420 | 0f8a249a | blueswir1 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 || |
421 | 0f8a249a | blueswir1 | ((env->dtlb_tte[i] & 0x4) && is_user) ||
|
422 | 0f8a249a | blueswir1 | (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { |
423 | 0f8a249a | blueswir1 | if (env->dmmuregs[3]) /* Fault status register */ |
424 | 0f8a249a | blueswir1 | env->dmmuregs[3] = 2; /* overflow (not read before another fault) */ |
425 | 0f8a249a | blueswir1 | env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; |
426 | 0f8a249a | blueswir1 | env->dmmuregs[4] = address; /* Fault address register */ |
427 | 0f8a249a | blueswir1 | env->exception_index = TT_DFAULT; |
428 | 83469015 | bellard | #ifdef DEBUG_MMU
|
429 | 0f8a249a | blueswir1 | printf("DFAULT at 0x%" PRIx64 "\n", address); |
430 | 83469015 | bellard | #endif
|
431 | 0f8a249a | blueswir1 | return 1; |
432 | 0f8a249a | blueswir1 | } |
433 | 0f8a249a | blueswir1 | *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
434 | 0f8a249a | blueswir1 | *prot = PAGE_READ; |
435 | 0f8a249a | blueswir1 | if (env->dtlb_tte[i] & 0x2) |
436 | 0f8a249a | blueswir1 | *prot |= PAGE_WRITE; |
437 | 0f8a249a | blueswir1 | return 0; |
438 | 0f8a249a | blueswir1 | } |
439 | 3475187d | bellard | } |
440 | 83469015 | bellard | #ifdef DEBUG_MMU
|
441 | 26a76461 | bellard | printf("DMISS at 0x%" PRIx64 "\n", address); |
442 | 83469015 | bellard | #endif
|
443 | 83469015 | bellard | env->exception_index = TT_DMISS; |
444 | 3475187d | bellard | return 1; |
445 | 3475187d | bellard | } |
446 | 3475187d | bellard | |
447 | 3475187d | bellard | static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot, |
448 | 0f8a249a | blueswir1 | int *access_index, target_ulong address, int rw, |
449 | 0f8a249a | blueswir1 | int is_user)
|
450 | 3475187d | bellard | { |
451 | 3475187d | bellard | target_ulong mask; |
452 | 3475187d | bellard | unsigned int i; |
453 | 3475187d | bellard | |
454 | 3475187d | bellard | if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */ |
455 | 0f8a249a | blueswir1 | *physical = address; |
456 | 0f8a249a | blueswir1 | *prot = PAGE_EXEC; |
457 | 3475187d | bellard | return 0; |
458 | 3475187d | bellard | } |
459 | 83469015 | bellard | |
460 | 3475187d | bellard | for (i = 0; i < 64; i++) { |
461 | 0f8a249a | blueswir1 | switch ((env->itlb_tte[i] >> 61) & 3) { |
462 | 0f8a249a | blueswir1 | default:
|
463 | 0f8a249a | blueswir1 | case 0x0: // 8k |
464 | 0f8a249a | blueswir1 | mask = 0xffffffffffffe000ULL;
|
465 | 0f8a249a | blueswir1 | break;
|
466 | 0f8a249a | blueswir1 | case 0x1: // 64k |
467 | 0f8a249a | blueswir1 | mask = 0xffffffffffff0000ULL;
|
468 | 0f8a249a | blueswir1 | break;
|
469 | 0f8a249a | blueswir1 | case 0x2: // 512k |
470 | 0f8a249a | blueswir1 | mask = 0xfffffffffff80000ULL;
|
471 | 0f8a249a | blueswir1 | break;
|
472 | 0f8a249a | blueswir1 | case 0x3: // 4M |
473 | 0f8a249a | blueswir1 | mask = 0xffffffffffc00000ULL;
|
474 | 0f8a249a | blueswir1 | break;
|
475 | 0f8a249a | blueswir1 | } |
476 | 0f8a249a | blueswir1 | // ctx match, vaddr match?
|
477 | 0f8a249a | blueswir1 | if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
478 | 0f8a249a | blueswir1 | (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
|
479 | 0f8a249a | blueswir1 | // valid, access ok?
|
480 | 0f8a249a | blueswir1 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 || |
481 | 0f8a249a | blueswir1 | ((env->itlb_tte[i] & 0x4) && is_user)) {
|
482 | 0f8a249a | blueswir1 | if (env->immuregs[3]) /* Fault status register */ |
483 | 0f8a249a | blueswir1 | env->immuregs[3] = 2; /* overflow (not read before another fault) */ |
484 | 0f8a249a | blueswir1 | env->immuregs[3] |= (is_user << 3) | 1; |
485 | 0f8a249a | blueswir1 | env->exception_index = TT_TFAULT; |
486 | 83469015 | bellard | #ifdef DEBUG_MMU
|
487 | 0f8a249a | blueswir1 | printf("TFAULT at 0x%" PRIx64 "\n", address); |
488 | 83469015 | bellard | #endif
|
489 | 0f8a249a | blueswir1 | return 1; |
490 | 0f8a249a | blueswir1 | } |
491 | 0f8a249a | blueswir1 | *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
492 | 0f8a249a | blueswir1 | *prot = PAGE_EXEC; |
493 | 0f8a249a | blueswir1 | return 0; |
494 | 0f8a249a | blueswir1 | } |
495 | 3475187d | bellard | } |
496 | 83469015 | bellard | #ifdef DEBUG_MMU
|
497 | 26a76461 | bellard | printf("TMISS at 0x%" PRIx64 "\n", address); |
498 | 83469015 | bellard | #endif
|
499 | 83469015 | bellard | env->exception_index = TT_TMISS; |
500 | 3475187d | bellard | return 1; |
501 | 3475187d | bellard | } |
502 | 3475187d | bellard | |
503 | c48fcb47 | blueswir1 | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
504 | c48fcb47 | blueswir1 | int *prot, int *access_index, |
505 | c48fcb47 | blueswir1 | target_ulong address, int rw, int mmu_idx) |
506 | 3475187d | bellard | { |
507 | 6ebbf390 | j_mayer | int is_user = mmu_idx == MMU_USER_IDX;
|
508 | 6ebbf390 | j_mayer | |
509 | 3475187d | bellard | if (rw == 2) |
510 | 0f8a249a | blueswir1 | return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
|
511 | 3475187d | bellard | else
|
512 | 0f8a249a | blueswir1 | return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
|
513 | 3475187d | bellard | } |
514 | 3475187d | bellard | |
515 | 3475187d | bellard | /* Perform address translation */
|
516 | 3475187d | bellard | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
517 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
518 | 3475187d | bellard | { |
519 | 83469015 | bellard | target_ulong virt_addr, vaddr; |
520 | 3475187d | bellard | target_phys_addr_t paddr; |
521 | 3475187d | bellard | int error_code = 0, prot, ret = 0, access_index; |
522 | 3475187d | bellard | |
523 | 6ebbf390 | j_mayer | error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx); |
524 | 3475187d | bellard | if (error_code == 0) { |
525 | 0f8a249a | blueswir1 | virt_addr = address & TARGET_PAGE_MASK; |
526 | 0f8a249a | blueswir1 | vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
|
527 | 83469015 | bellard | #ifdef DEBUG_MMU
|
528 | 0f8a249a | blueswir1 | printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr); |
529 | 83469015 | bellard | #endif
|
530 | 6ebbf390 | j_mayer | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
531 | 0f8a249a | blueswir1 | return ret;
|
532 | 3475187d | bellard | } |
533 | 3475187d | bellard | // XXX
|
534 | 3475187d | bellard | return 1; |
535 | 3475187d | bellard | } |
536 | 3475187d | bellard | |
537 | 83469015 | bellard | #ifdef DEBUG_MMU
|
538 | 83469015 | bellard | void dump_mmu(CPUState *env)
|
539 | 83469015 | bellard | { |
540 | 83469015 | bellard | unsigned int i; |
541 | 83469015 | bellard | const char *mask; |
542 | 83469015 | bellard | |
543 | 26a76461 | bellard | printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]); |
544 | 83469015 | bellard | if ((env->lsu & DMMU_E) == 0) { |
545 | 0f8a249a | blueswir1 | printf("DMMU disabled\n");
|
546 | 83469015 | bellard | } else {
|
547 | 0f8a249a | blueswir1 | printf("DMMU dump:\n");
|
548 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
549 | 0f8a249a | blueswir1 | switch ((env->dtlb_tte[i] >> 61) & 3) { |
550 | 0f8a249a | blueswir1 | default:
|
551 | 0f8a249a | blueswir1 | case 0x0: |
552 | 0f8a249a | blueswir1 | mask = " 8k";
|
553 | 0f8a249a | blueswir1 | break;
|
554 | 0f8a249a | blueswir1 | case 0x1: |
555 | 0f8a249a | blueswir1 | mask = " 64k";
|
556 | 0f8a249a | blueswir1 | break;
|
557 | 0f8a249a | blueswir1 | case 0x2: |
558 | 0f8a249a | blueswir1 | mask = "512k";
|
559 | 0f8a249a | blueswir1 | break;
|
560 | 0f8a249a | blueswir1 | case 0x3: |
561 | 0f8a249a | blueswir1 | mask = " 4M";
|
562 | 0f8a249a | blueswir1 | break;
|
563 | 0f8a249a | blueswir1 | } |
564 | 0f8a249a | blueswir1 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { |
565 | 0f8a249a | blueswir1 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n", |
566 | 0f8a249a | blueswir1 | env->dtlb_tag[i] & ~0x1fffULL,
|
567 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x1ffffffe000ULL,
|
568 | 0f8a249a | blueswir1 | mask, |
569 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x4? "priv": "user", |
570 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x2? "RW": "RO", |
571 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x40? "locked": "unlocked", |
572 | 0f8a249a | blueswir1 | env->dtlb_tag[i] & 0x1fffULL);
|
573 | 0f8a249a | blueswir1 | } |
574 | 0f8a249a | blueswir1 | } |
575 | 83469015 | bellard | } |
576 | 83469015 | bellard | if ((env->lsu & IMMU_E) == 0) { |
577 | 0f8a249a | blueswir1 | printf("IMMU disabled\n");
|
578 | 83469015 | bellard | } else {
|
579 | 0f8a249a | blueswir1 | printf("IMMU dump:\n");
|
580 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
581 | 0f8a249a | blueswir1 | switch ((env->itlb_tte[i] >> 61) & 3) { |
582 | 0f8a249a | blueswir1 | default:
|
583 | 0f8a249a | blueswir1 | case 0x0: |
584 | 0f8a249a | blueswir1 | mask = " 8k";
|
585 | 0f8a249a | blueswir1 | break;
|
586 | 0f8a249a | blueswir1 | case 0x1: |
587 | 0f8a249a | blueswir1 | mask = " 64k";
|
588 | 0f8a249a | blueswir1 | break;
|
589 | 0f8a249a | blueswir1 | case 0x2: |
590 | 0f8a249a | blueswir1 | mask = "512k";
|
591 | 0f8a249a | blueswir1 | break;
|
592 | 0f8a249a | blueswir1 | case 0x3: |
593 | 0f8a249a | blueswir1 | mask = " 4M";
|
594 | 0f8a249a | blueswir1 | break;
|
595 | 0f8a249a | blueswir1 | } |
596 | 0f8a249a | blueswir1 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { |
597 | 0f8a249a | blueswir1 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n", |
598 | 0f8a249a | blueswir1 | env->itlb_tag[i] & ~0x1fffULL,
|
599 | 0f8a249a | blueswir1 | env->itlb_tte[i] & 0x1ffffffe000ULL,
|
600 | 0f8a249a | blueswir1 | mask, |
601 | 0f8a249a | blueswir1 | env->itlb_tte[i] & 0x4? "priv": "user", |
602 | 0f8a249a | blueswir1 | env->itlb_tte[i] & 0x40? "locked": "unlocked", |
603 | 0f8a249a | blueswir1 | env->itlb_tag[i] & 0x1fffULL);
|
604 | 0f8a249a | blueswir1 | } |
605 | 0f8a249a | blueswir1 | } |
606 | 83469015 | bellard | } |
607 | 83469015 | bellard | } |
608 | 24741ef3 | bellard | #endif /* DEBUG_MMU */ |
609 | 24741ef3 | bellard | |
610 | 24741ef3 | bellard | #endif /* TARGET_SPARC64 */ |
611 | 24741ef3 | bellard | #endif /* !CONFIG_USER_ONLY */ |
612 | 24741ef3 | bellard | |
613 | c48fcb47 | blueswir1 | |
614 | c48fcb47 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
615 | c48fcb47 | blueswir1 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
616 | c48fcb47 | blueswir1 | { |
617 | c48fcb47 | blueswir1 | return addr;
|
618 | c48fcb47 | blueswir1 | } |
619 | c48fcb47 | blueswir1 | |
620 | c48fcb47 | blueswir1 | #else
|
621 | c48fcb47 | blueswir1 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
622 | c48fcb47 | blueswir1 | { |
623 | c48fcb47 | blueswir1 | target_phys_addr_t phys_addr; |
624 | c48fcb47 | blueswir1 | int prot, access_index;
|
625 | c48fcb47 | blueswir1 | |
626 | c48fcb47 | blueswir1 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, |
627 | c48fcb47 | blueswir1 | MMU_KERNEL_IDX) != 0)
|
628 | c48fcb47 | blueswir1 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
|
629 | c48fcb47 | blueswir1 | 0, MMU_KERNEL_IDX) != 0) |
630 | c48fcb47 | blueswir1 | return -1; |
631 | c48fcb47 | blueswir1 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
|
632 | c48fcb47 | blueswir1 | return -1; |
633 | c48fcb47 | blueswir1 | return phys_addr;
|
634 | c48fcb47 | blueswir1 | } |
635 | c48fcb47 | blueswir1 | #endif
|
636 | c48fcb47 | blueswir1 | |
637 | 24741ef3 | bellard | void memcpy32(target_ulong *dst, const target_ulong *src) |
638 | 24741ef3 | bellard | { |
639 | 24741ef3 | bellard | dst[0] = src[0]; |
640 | 24741ef3 | bellard | dst[1] = src[1]; |
641 | 24741ef3 | bellard | dst[2] = src[2]; |
642 | 24741ef3 | bellard | dst[3] = src[3]; |
643 | 24741ef3 | bellard | dst[4] = src[4]; |
644 | 24741ef3 | bellard | dst[5] = src[5]; |
645 | 24741ef3 | bellard | dst[6] = src[6]; |
646 | 24741ef3 | bellard | dst[7] = src[7]; |
647 | 24741ef3 | bellard | } |
648 | 87ecb68b | pbrook | |
649 | c48fcb47 | blueswir1 | void helper_flush(target_ulong addr)
|
650 | c48fcb47 | blueswir1 | { |
651 | c48fcb47 | blueswir1 | addr &= ~7;
|
652 | c48fcb47 | blueswir1 | tb_invalidate_page_range(addr, addr + 8);
|
653 | c48fcb47 | blueswir1 | } |
654 | c48fcb47 | blueswir1 | |
655 | c48fcb47 | blueswir1 | void cpu_reset(CPUSPARCState *env)
|
656 | c48fcb47 | blueswir1 | { |
657 | c48fcb47 | blueswir1 | tlb_flush(env, 1);
|
658 | c48fcb47 | blueswir1 | env->cwp = 0;
|
659 | c48fcb47 | blueswir1 | env->wim = 1;
|
660 | c48fcb47 | blueswir1 | env->regwptr = env->regbase + (env->cwp * 16);
|
661 | c48fcb47 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
662 | c48fcb47 | blueswir1 | env->user_mode_only = 1;
|
663 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
664 | c48fcb47 | blueswir1 | env->cleanwin = NWINDOWS - 2;
|
665 | c48fcb47 | blueswir1 | env->cansave = NWINDOWS - 2;
|
666 | c48fcb47 | blueswir1 | env->pstate = PS_RMO | PS_PEF | PS_IE; |
667 | c48fcb47 | blueswir1 | env->asi = 0x82; // Primary no-fault |
668 | c48fcb47 | blueswir1 | #endif
|
669 | c48fcb47 | blueswir1 | #else
|
670 | c48fcb47 | blueswir1 | env->psret = 0;
|
671 | c48fcb47 | blueswir1 | env->psrs = 1;
|
672 | c48fcb47 | blueswir1 | env->psrps = 1;
|
673 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
674 | c48fcb47 | blueswir1 | env->pstate = PS_PRIV; |
675 | c48fcb47 | blueswir1 | env->hpstate = HS_PRIV; |
676 | c48fcb47 | blueswir1 | env->pc = 0x1fff0000000ULL;
|
677 | c48fcb47 | blueswir1 | env->tsptr = &env->ts[env->tl]; |
678 | c48fcb47 | blueswir1 | #else
|
679 | c48fcb47 | blueswir1 | env->pc = 0;
|
680 | c48fcb47 | blueswir1 | env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
681 | c48fcb47 | blueswir1 | env->mmuregs[0] |= env->mmu_bm;
|
682 | c48fcb47 | blueswir1 | #endif
|
683 | c48fcb47 | blueswir1 | env->npc = env->pc + 4;
|
684 | c48fcb47 | blueswir1 | #endif
|
685 | c48fcb47 | blueswir1 | } |
686 | c48fcb47 | blueswir1 | |
687 | c48fcb47 | blueswir1 | CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
688 | c48fcb47 | blueswir1 | { |
689 | c48fcb47 | blueswir1 | CPUSPARCState *env; |
690 | c48fcb47 | blueswir1 | const sparc_def_t *def;
|
691 | c48fcb47 | blueswir1 | |
692 | c48fcb47 | blueswir1 | def = cpu_sparc_find_by_name(cpu_model); |
693 | c48fcb47 | blueswir1 | if (!def)
|
694 | c48fcb47 | blueswir1 | return NULL; |
695 | c48fcb47 | blueswir1 | |
696 | c48fcb47 | blueswir1 | env = qemu_mallocz(sizeof(CPUSPARCState));
|
697 | c48fcb47 | blueswir1 | if (!env)
|
698 | c48fcb47 | blueswir1 | return NULL; |
699 | c48fcb47 | blueswir1 | cpu_exec_init(env); |
700 | c48fcb47 | blueswir1 | env->cpu_model_str = cpu_model; |
701 | c48fcb47 | blueswir1 | env->version = def->iu_version; |
702 | c48fcb47 | blueswir1 | env->fsr = def->fpu_version; |
703 | c48fcb47 | blueswir1 | #if !defined(TARGET_SPARC64)
|
704 | c48fcb47 | blueswir1 | env->mmu_bm = def->mmu_bm; |
705 | c48fcb47 | blueswir1 | env->mmu_ctpr_mask = def->mmu_ctpr_mask; |
706 | c48fcb47 | blueswir1 | env->mmu_cxr_mask = def->mmu_cxr_mask; |
707 | c48fcb47 | blueswir1 | env->mmu_sfsr_mask = def->mmu_sfsr_mask; |
708 | c48fcb47 | blueswir1 | env->mmu_trcr_mask = def->mmu_trcr_mask; |
709 | c48fcb47 | blueswir1 | env->mmuregs[0] |= def->mmu_version;
|
710 | c48fcb47 | blueswir1 | cpu_sparc_set_id(env, 0);
|
711 | c48fcb47 | blueswir1 | #endif
|
712 | c48fcb47 | blueswir1 | |
713 | c48fcb47 | blueswir1 | gen_intermediate_code_init(env); |
714 | c48fcb47 | blueswir1 | |
715 | c48fcb47 | blueswir1 | cpu_reset(env); |
716 | c48fcb47 | blueswir1 | |
717 | c48fcb47 | blueswir1 | return env;
|
718 | c48fcb47 | blueswir1 | } |
719 | c48fcb47 | blueswir1 | |
720 | c48fcb47 | blueswir1 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
721 | c48fcb47 | blueswir1 | { |
722 | c48fcb47 | blueswir1 | #if !defined(TARGET_SPARC64)
|
723 | c48fcb47 | blueswir1 | env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
724 | c48fcb47 | blueswir1 | #endif
|
725 | c48fcb47 | blueswir1 | } |
726 | c48fcb47 | blueswir1 | |
727 | c48fcb47 | blueswir1 | static const sparc_def_t sparc_defs[] = { |
728 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
729 | c48fcb47 | blueswir1 | { |
730 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64",
|
731 | c48fcb47 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) |
732 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
733 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
734 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
735 | c48fcb47 | blueswir1 | }, |
736 | c48fcb47 | blueswir1 | { |
737 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64 III",
|
738 | c48fcb47 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) |
739 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
740 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
741 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
742 | c48fcb47 | blueswir1 | }, |
743 | c48fcb47 | blueswir1 | { |
744 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64 IV",
|
745 | c48fcb47 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) |
746 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
747 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
748 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
749 | c48fcb47 | blueswir1 | }, |
750 | c48fcb47 | blueswir1 | { |
751 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64 V",
|
752 | c48fcb47 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) |
753 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
754 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
755 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
756 | c48fcb47 | blueswir1 | }, |
757 | c48fcb47 | blueswir1 | { |
758 | c48fcb47 | blueswir1 | .name = "TI UltraSparc I",
|
759 | c48fcb47 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
760 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
761 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
762 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
763 | c48fcb47 | blueswir1 | }, |
764 | c48fcb47 | blueswir1 | { |
765 | c48fcb47 | blueswir1 | .name = "TI UltraSparc II",
|
766 | c48fcb47 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) |
767 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
768 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
769 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
770 | c48fcb47 | blueswir1 | }, |
771 | c48fcb47 | blueswir1 | { |
772 | c48fcb47 | blueswir1 | .name = "TI UltraSparc IIi",
|
773 | c48fcb47 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) |
774 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
775 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
776 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
777 | c48fcb47 | blueswir1 | }, |
778 | c48fcb47 | blueswir1 | { |
779 | c48fcb47 | blueswir1 | .name = "TI UltraSparc IIe",
|
780 | c48fcb47 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) |
781 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
782 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
783 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
784 | c48fcb47 | blueswir1 | }, |
785 | c48fcb47 | blueswir1 | { |
786 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc III",
|
787 | c48fcb47 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) |
788 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
789 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
790 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
791 | c48fcb47 | blueswir1 | }, |
792 | c48fcb47 | blueswir1 | { |
793 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc III Cu",
|
794 | c48fcb47 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) |
795 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
796 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
797 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
798 | c48fcb47 | blueswir1 | }, |
799 | c48fcb47 | blueswir1 | { |
800 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IIIi",
|
801 | c48fcb47 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) |
802 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
803 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
804 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
805 | c48fcb47 | blueswir1 | }, |
806 | c48fcb47 | blueswir1 | { |
807 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IV",
|
808 | c48fcb47 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) |
809 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
810 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
811 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
812 | c48fcb47 | blueswir1 | }, |
813 | c48fcb47 | blueswir1 | { |
814 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IV+",
|
815 | c48fcb47 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) |
816 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
817 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
818 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
819 | c48fcb47 | blueswir1 | }, |
820 | c48fcb47 | blueswir1 | { |
821 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IIIi+",
|
822 | c48fcb47 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) |
823 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
824 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
825 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
826 | c48fcb47 | blueswir1 | }, |
827 | c48fcb47 | blueswir1 | { |
828 | c48fcb47 | blueswir1 | .name = "NEC UltraSparc I",
|
829 | c48fcb47 | blueswir1 | .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
830 | c48fcb47 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
831 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
832 | c48fcb47 | blueswir1 | .mmu_version = 0,
|
833 | c48fcb47 | blueswir1 | }, |
834 | c48fcb47 | blueswir1 | #else
|
835 | c48fcb47 | blueswir1 | { |
836 | c48fcb47 | blueswir1 | .name = "Fujitsu MB86900",
|
837 | c48fcb47 | blueswir1 | .iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
838 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
839 | c48fcb47 | blueswir1 | .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
840 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
841 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
842 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
843 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
844 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
845 | c48fcb47 | blueswir1 | }, |
846 | c48fcb47 | blueswir1 | { |
847 | c48fcb47 | blueswir1 | .name = "Fujitsu MB86904",
|
848 | c48fcb47 | blueswir1 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
849 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
850 | c48fcb47 | blueswir1 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
851 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
852 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
853 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
854 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
855 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
856 | c48fcb47 | blueswir1 | }, |
857 | c48fcb47 | blueswir1 | { |
858 | c48fcb47 | blueswir1 | .name = "Fujitsu MB86907",
|
859 | c48fcb47 | blueswir1 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
860 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
861 | c48fcb47 | blueswir1 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
862 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
863 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
864 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
865 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
866 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
867 | c48fcb47 | blueswir1 | }, |
868 | c48fcb47 | blueswir1 | { |
869 | c48fcb47 | blueswir1 | .name = "LSI L64811",
|
870 | c48fcb47 | blueswir1 | .iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
871 | c48fcb47 | blueswir1 | .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
872 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
873 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
874 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
875 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
876 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
877 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
878 | c48fcb47 | blueswir1 | }, |
879 | c48fcb47 | blueswir1 | { |
880 | c48fcb47 | blueswir1 | .name = "Cypress CY7C601",
|
881 | c48fcb47 | blueswir1 | .iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
882 | c48fcb47 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
883 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
884 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
885 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
886 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
887 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
888 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
889 | c48fcb47 | blueswir1 | }, |
890 | c48fcb47 | blueswir1 | { |
891 | c48fcb47 | blueswir1 | .name = "Cypress CY7C611",
|
892 | c48fcb47 | blueswir1 | .iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
893 | c48fcb47 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
894 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
895 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
896 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
897 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
898 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
899 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
900 | c48fcb47 | blueswir1 | }, |
901 | c48fcb47 | blueswir1 | { |
902 | c48fcb47 | blueswir1 | .name = "TI SuperSparc II",
|
903 | c48fcb47 | blueswir1 | .iu_version = 0x40000000,
|
904 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
905 | c48fcb47 | blueswir1 | .mmu_version = 0x04000000,
|
906 | c48fcb47 | blueswir1 | .mmu_bm = 0x00002000,
|
907 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
908 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
909 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
910 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
911 | c48fcb47 | blueswir1 | }, |
912 | c48fcb47 | blueswir1 | { |
913 | c48fcb47 | blueswir1 | .name = "TI MicroSparc I",
|
914 | c48fcb47 | blueswir1 | .iu_version = 0x41000000,
|
915 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, |
916 | c48fcb47 | blueswir1 | .mmu_version = 0x41000000,
|
917 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
918 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
919 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
920 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
921 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x0000003f,
|
922 | c48fcb47 | blueswir1 | }, |
923 | c48fcb47 | blueswir1 | { |
924 | c48fcb47 | blueswir1 | .name = "TI MicroSparc II",
|
925 | c48fcb47 | blueswir1 | .iu_version = 0x42000000,
|
926 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, |
927 | c48fcb47 | blueswir1 | .mmu_version = 0x02000000,
|
928 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
929 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
930 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
931 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
932 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
933 | c48fcb47 | blueswir1 | }, |
934 | c48fcb47 | blueswir1 | { |
935 | c48fcb47 | blueswir1 | .name = "TI MicroSparc IIep",
|
936 | c48fcb47 | blueswir1 | .iu_version = 0x42000000,
|
937 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, |
938 | c48fcb47 | blueswir1 | .mmu_version = 0x04000000,
|
939 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
940 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
941 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
942 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016bff,
|
943 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
944 | c48fcb47 | blueswir1 | }, |
945 | c48fcb47 | blueswir1 | { |
946 | c48fcb47 | blueswir1 | .name = "TI SuperSparc 51",
|
947 | c48fcb47 | blueswir1 | .iu_version = 0x43000000,
|
948 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
949 | c48fcb47 | blueswir1 | .mmu_version = 0x04000000,
|
950 | c48fcb47 | blueswir1 | .mmu_bm = 0x00002000,
|
951 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
952 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
953 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
954 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
955 | c48fcb47 | blueswir1 | }, |
956 | c48fcb47 | blueswir1 | { |
957 | c48fcb47 | blueswir1 | .name = "TI SuperSparc 61",
|
958 | c48fcb47 | blueswir1 | .iu_version = 0x44000000,
|
959 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
960 | c48fcb47 | blueswir1 | .mmu_version = 0x04000000,
|
961 | c48fcb47 | blueswir1 | .mmu_bm = 0x00002000,
|
962 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
963 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
964 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
965 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
966 | c48fcb47 | blueswir1 | }, |
967 | c48fcb47 | blueswir1 | { |
968 | c48fcb47 | blueswir1 | .name = "Ross RT625",
|
969 | c48fcb47 | blueswir1 | .iu_version = 0x1e000000,
|
970 | c48fcb47 | blueswir1 | .fpu_version = 1 << 17, |
971 | c48fcb47 | blueswir1 | .mmu_version = 0x1e000000,
|
972 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
973 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
974 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
975 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
976 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
977 | c48fcb47 | blueswir1 | }, |
978 | c48fcb47 | blueswir1 | { |
979 | c48fcb47 | blueswir1 | .name = "Ross RT620",
|
980 | c48fcb47 | blueswir1 | .iu_version = 0x1f000000,
|
981 | c48fcb47 | blueswir1 | .fpu_version = 1 << 17, |
982 | c48fcb47 | blueswir1 | .mmu_version = 0x1f000000,
|
983 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
984 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
985 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
986 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
987 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
988 | c48fcb47 | blueswir1 | }, |
989 | c48fcb47 | blueswir1 | { |
990 | c48fcb47 | blueswir1 | .name = "BIT B5010",
|
991 | c48fcb47 | blueswir1 | .iu_version = 0x20000000,
|
992 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
993 | c48fcb47 | blueswir1 | .mmu_version = 0x20000000,
|
994 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
995 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
996 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
997 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
998 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
999 | c48fcb47 | blueswir1 | }, |
1000 | c48fcb47 | blueswir1 | { |
1001 | c48fcb47 | blueswir1 | .name = "Matsushita MN10501",
|
1002 | c48fcb47 | blueswir1 | .iu_version = 0x50000000,
|
1003 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
1004 | c48fcb47 | blueswir1 | .mmu_version = 0x50000000,
|
1005 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1006 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1007 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1008 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1009 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1010 | c48fcb47 | blueswir1 | }, |
1011 | c48fcb47 | blueswir1 | { |
1012 | c48fcb47 | blueswir1 | .name = "Weitek W8601",
|
1013 | c48fcb47 | blueswir1 | .iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
1014 | c48fcb47 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
1015 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
1016 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1017 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1018 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1019 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1020 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1021 | c48fcb47 | blueswir1 | }, |
1022 | c48fcb47 | blueswir1 | { |
1023 | c48fcb47 | blueswir1 | .name = "LEON2",
|
1024 | c48fcb47 | blueswir1 | .iu_version = 0xf2000000,
|
1025 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1026 | c48fcb47 | blueswir1 | .mmu_version = 0xf2000000,
|
1027 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1028 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1029 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1030 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1031 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1032 | c48fcb47 | blueswir1 | }, |
1033 | c48fcb47 | blueswir1 | { |
1034 | c48fcb47 | blueswir1 | .name = "LEON3",
|
1035 | c48fcb47 | blueswir1 | .iu_version = 0xf3000000,
|
1036 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1037 | c48fcb47 | blueswir1 | .mmu_version = 0xf3000000,
|
1038 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1039 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1040 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1041 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1042 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1043 | c48fcb47 | blueswir1 | }, |
1044 | c48fcb47 | blueswir1 | #endif
|
1045 | c48fcb47 | blueswir1 | }; |
1046 | c48fcb47 | blueswir1 | |
1047 | c48fcb47 | blueswir1 | static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name) |
1048 | c48fcb47 | blueswir1 | { |
1049 | c48fcb47 | blueswir1 | unsigned int i; |
1050 | c48fcb47 | blueswir1 | |
1051 | c48fcb47 | blueswir1 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
1052 | c48fcb47 | blueswir1 | if (strcasecmp(name, sparc_defs[i].name) == 0) { |
1053 | c48fcb47 | blueswir1 | return &sparc_defs[i];
|
1054 | c48fcb47 | blueswir1 | } |
1055 | c48fcb47 | blueswir1 | } |
1056 | c48fcb47 | blueswir1 | return NULL; |
1057 | c48fcb47 | blueswir1 | } |
1058 | c48fcb47 | blueswir1 | |
1059 | c48fcb47 | blueswir1 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
1060 | c48fcb47 | blueswir1 | { |
1061 | c48fcb47 | blueswir1 | unsigned int i; |
1062 | c48fcb47 | blueswir1 | |
1063 | c48fcb47 | blueswir1 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
1064 | c48fcb47 | blueswir1 | (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n", |
1065 | c48fcb47 | blueswir1 | sparc_defs[i].name, |
1066 | c48fcb47 | blueswir1 | sparc_defs[i].iu_version, |
1067 | c48fcb47 | blueswir1 | sparc_defs[i].fpu_version, |
1068 | c48fcb47 | blueswir1 | sparc_defs[i].mmu_version); |
1069 | c48fcb47 | blueswir1 | } |
1070 | c48fcb47 | blueswir1 | } |
1071 | c48fcb47 | blueswir1 | |
1072 | c48fcb47 | blueswir1 | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
1073 | c48fcb47 | blueswir1 | |
1074 | c48fcb47 | blueswir1 | void cpu_dump_state(CPUState *env, FILE *f,
|
1075 | c48fcb47 | blueswir1 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
1076 | c48fcb47 | blueswir1 | int flags)
|
1077 | c48fcb47 | blueswir1 | { |
1078 | c48fcb47 | blueswir1 | int i, x;
|
1079 | c48fcb47 | blueswir1 | |
1080 | c48fcb47 | blueswir1 | cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); |
1081 | c48fcb47 | blueswir1 | cpu_fprintf(f, "General Registers:\n");
|
1082 | c48fcb47 | blueswir1 | for (i = 0; i < 4; i++) |
1083 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
1084 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1085 | c48fcb47 | blueswir1 | for (; i < 8; i++) |
1086 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
1087 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\nCurrent Register Window:\n");
|
1088 | c48fcb47 | blueswir1 | for (x = 0; x < 3; x++) { |
1089 | c48fcb47 | blueswir1 | for (i = 0; i < 4; i++) |
1090 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
1091 | c48fcb47 | blueswir1 | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
1092 | c48fcb47 | blueswir1 | env->regwptr[i + x * 8]);
|
1093 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1094 | c48fcb47 | blueswir1 | for (; i < 8; i++) |
1095 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
1096 | c48fcb47 | blueswir1 | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
1097 | c48fcb47 | blueswir1 | env->regwptr[i + x * 8]);
|
1098 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1099 | c48fcb47 | blueswir1 | } |
1100 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\nFloating Point Registers:\n");
|
1101 | c48fcb47 | blueswir1 | for (i = 0; i < 32; i++) { |
1102 | c48fcb47 | blueswir1 | if ((i & 3) == 0) |
1103 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%f%02d:", i);
|
1104 | c48fcb47 | blueswir1 | cpu_fprintf(f, " %016lf", env->fpr[i]);
|
1105 | c48fcb47 | blueswir1 | if ((i & 3) == 3) |
1106 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1107 | c48fcb47 | blueswir1 | } |
1108 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
1109 | c48fcb47 | blueswir1 | cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
|
1110 | c48fcb47 | blueswir1 | env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
1111 | c48fcb47 | blueswir1 | cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
|
1112 | c48fcb47 | blueswir1 | env->cansave, env->canrestore, env->otherwin, env->wstate, |
1113 | c48fcb47 | blueswir1 | env->cleanwin, NWINDOWS - 1 - env->cwp);
|
1114 | c48fcb47 | blueswir1 | #else
|
1115 | c48fcb47 | blueswir1 | cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
|
1116 | c48fcb47 | blueswir1 | GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
1117 | c48fcb47 | blueswir1 | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
1118 | c48fcb47 | blueswir1 | env->psrs?'S':'-', env->psrps?'P':'-', |
1119 | c48fcb47 | blueswir1 | env->psret?'E':'-', env->wim); |
1120 | c48fcb47 | blueswir1 | #endif
|
1121 | c48fcb47 | blueswir1 | cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
|
1122 | c48fcb47 | blueswir1 | } |
1123 | c48fcb47 | blueswir1 | |
1124 | 87ecb68b | pbrook | #ifdef TARGET_SPARC64
|
1125 | 87ecb68b | pbrook | #if !defined(CONFIG_USER_ONLY)
|
1126 | 87ecb68b | pbrook | #include "qemu-common.h" |
1127 | 87ecb68b | pbrook | #include "hw/irq.h" |
1128 | 87ecb68b | pbrook | #include "qemu-timer.h" |
1129 | 87ecb68b | pbrook | #endif
|
1130 | 87ecb68b | pbrook | |
1131 | ccd4a219 | blueswir1 | void helper_tick_set_count(void *opaque, uint64_t count) |
1132 | 87ecb68b | pbrook | { |
1133 | 87ecb68b | pbrook | #if !defined(CONFIG_USER_ONLY)
|
1134 | 87ecb68b | pbrook | ptimer_set_count(opaque, -count); |
1135 | 87ecb68b | pbrook | #endif
|
1136 | 87ecb68b | pbrook | } |
1137 | 87ecb68b | pbrook | |
1138 | ccd4a219 | blueswir1 | uint64_t helper_tick_get_count(void *opaque)
|
1139 | 87ecb68b | pbrook | { |
1140 | 87ecb68b | pbrook | #if !defined(CONFIG_USER_ONLY)
|
1141 | 87ecb68b | pbrook | return -ptimer_get_count(opaque);
|
1142 | 87ecb68b | pbrook | #else
|
1143 | 87ecb68b | pbrook | return 0; |
1144 | 87ecb68b | pbrook | #endif
|
1145 | 87ecb68b | pbrook | } |
1146 | 87ecb68b | pbrook | |
1147 | ccd4a219 | blueswir1 | void helper_tick_set_limit(void *opaque, uint64_t limit) |
1148 | 87ecb68b | pbrook | { |
1149 | 87ecb68b | pbrook | #if !defined(CONFIG_USER_ONLY)
|
1150 | 87ecb68b | pbrook | ptimer_set_limit(opaque, -limit, 0);
|
1151 | 87ecb68b | pbrook | #endif
|
1152 | 87ecb68b | pbrook | } |
1153 | 87ecb68b | pbrook | #endif |