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/*
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* sparc helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include <assert.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "qemu-common.h" |
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//#define DEBUG_MMU
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typedef struct sparc_def_t sparc_def_t; |
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struct sparc_def_t {
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const unsigned char *name; |
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target_ulong iu_version; |
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uint32_t fpu_version; |
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uint32_t mmu_version; |
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uint32_t mmu_bm; |
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uint32_t mmu_ctpr_mask; |
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uint32_t mmu_cxr_mask; |
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uint32_t mmu_sfsr_mask; |
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uint32_t mmu_trcr_mask; |
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}; |
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static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name); |
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|
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/* Sparc MMU emulation */
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|
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/* thread support */
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spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
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void cpu_lock(void) |
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{ |
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spin_lock(&global_cpu_lock); |
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} |
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void cpu_unlock(void) |
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{ |
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spin_unlock(&global_cpu_lock); |
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} |
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#if defined(CONFIG_USER_ONLY)
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int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{ |
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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#else
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#ifndef TARGET_SPARC64
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/*
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* Sparc V8 Reference MMU (SRMMU)
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*/
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static const int access_table[8][8] = { |
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{ 0, 0, 0, 0, 2, 0, 3, 3 }, |
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{ 0, 0, 0, 0, 2, 0, 0, 0 }, |
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{ 2, 2, 0, 0, 0, 2, 3, 3 }, |
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{ 2, 2, 0, 0, 0, 2, 0, 0 }, |
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{ 2, 0, 2, 0, 2, 2, 3, 3 }, |
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{ 2, 0, 2, 0, 2, 0, 2, 0 }, |
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{ 2, 2, 2, 0, 2, 2, 3, 3 }, |
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{ 2, 2, 2, 0, 2, 2, 2, 0 } |
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}; |
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static const int perm_table[2][8] = { |
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{ |
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC |
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}, |
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{ |
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ, |
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0,
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0,
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} |
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}; |
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static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
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int *prot, int *access_index, |
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target_ulong address, int rw, int mmu_idx) |
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{ |
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int access_perms = 0; |
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
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target_ulong virt_addr; |
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int error_code = 0, is_dirty, is_user; |
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unsigned long page_offset; |
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is_user = mmu_idx == MMU_USER_IDX; |
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virt_addr = address & TARGET_PAGE_MASK; |
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if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
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// Boot mode: instruction fetches are taken from PROM
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if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) { |
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*physical = env->prom_addr | (address & 0x7ffffULL);
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*prot = PAGE_READ | PAGE_EXEC; |
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return 0; |
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} |
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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return 0; |
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} |
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
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*physical = 0xffffffffffff0000ULL;
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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/* Ctx pde */
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return 1 << 2; |
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case 2: /* L0 PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 4 << 2; |
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case 1: /* L0 PDE */ |
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (1 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (1 << 8) | (4 << 2); |
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case 1: /* L1 PDE */ |
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (2 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (2 << 8) | (4 << 2); |
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case 1: /* L2 PDE */ |
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (3 << 8) | (1 << 2); |
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case 1: /* PDE, should not happen */ |
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case 3: /* Reserved */ |
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return (3 << 8) | (4 << 2); |
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case 2: /* L3 PTE */ |
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virt_addr = address & TARGET_PAGE_MASK; |
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page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
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} |
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break;
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case 2: /* L2 PTE */ |
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virt_addr = address & ~0x3ffff;
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page_offset = address & 0x3ffff;
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} |
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break;
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case 2: /* L1 PTE */ |
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virt_addr = address & ~0xffffff;
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page_offset = address & 0xffffff;
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} |
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} |
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/* update page modified and dirty bits */
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is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK; |
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if (is_dirty)
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pde |= PG_MODIFIED_MASK; |
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stl_phys_notdirty(pde_ptr, pde); |
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} |
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/* check access */
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
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error_code = access_table[*access_index][access_perms]; |
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if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) |
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return error_code;
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/* the page can be put in the TLB */
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*prot = perm_table[is_user][access_perms]; |
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if (!(pde & PG_MODIFIED_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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*prot &= ~PAGE_WRITE; |
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} |
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/* Even if large ptes, we map only one 4KB page in the cache to
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avoid filling it too fast */
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*physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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return error_code;
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} |
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/* Perform address translation */
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{ |
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target_phys_addr_t paddr; |
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target_ulong vaddr; |
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int error_code = 0, prot, ret = 0, access_index; |
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx); |
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if (error_code == 0) { |
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vaddr = address & TARGET_PAGE_MASK; |
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paddr &= TARGET_PAGE_MASK; |
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#ifdef DEBUG_MMU
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printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
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TARGET_FMT_lx "\n", address, paddr, vaddr);
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#endif
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
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return ret;
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} |
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if (env->mmuregs[3]) /* Fault status register */ |
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
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env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
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env->mmuregs[4] = address; /* Fault address register */ |
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
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// No fault mode: if a mapping is available, just override
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// permissions. If no mapping is available, redirect accesses to
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// neverland. Fake/overridden mappings will be flushed when
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// switching to normal mode.
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vaddr = address & TARGET_PAGE_MASK; |
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
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return ret;
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} else {
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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} |
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target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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{ |
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
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/* Context base + context number */
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pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
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(env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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case 2: /* PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 0; |
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case 1: /* L1 PDE */ |
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if (mmulev == 3) |
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return pde;
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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case 3: /* Reserved */ |
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return 0; |
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case 2: /* L1 PTE */ |
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return pde;
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case 1: /* L2 PDE */ |
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if (mmulev == 2) |
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return pde;
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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case 3: /* Reserved */ |
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return 0; |
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case 2: /* L2 PTE */ |
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return pde;
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case 1: /* L3 PDE */ |
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if (mmulev == 1) |
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return pde;
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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case 1: /* PDE, should not happen */ |
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case 3: /* Reserved */ |
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return 0; |
332 |
case 2: /* L3 PTE */ |
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return pde;
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} |
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} |
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} |
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} |
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return 0; |
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} |
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|
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#ifdef DEBUG_MMU
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void dump_mmu(CPUState *env)
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{ |
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target_ulong va, va1, va2; |
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unsigned int n, m, o; |
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target_phys_addr_t pde_ptr, pa; |
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uint32_t pde; |
348 |
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printf("MMU dump:\n");
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
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(target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); |
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for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
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pde = mmu_probe(env, va, 2);
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if (pde) {
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pa = cpu_get_phys_page_debug(env, va); |
358 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
359 |
" PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
360 |
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
361 |
pde = mmu_probe(env, va1, 1);
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if (pde) {
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pa = cpu_get_phys_page_debug(env, va1); |
364 |
printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
365 |
" PDE: " TARGET_FMT_lx "\n", va1, pa, pde); |
366 |
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
367 |
pde = mmu_probe(env, va2, 0);
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368 |
if (pde) {
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pa = cpu_get_phys_page_debug(env, va2); |
370 |
printf(" VA: " TARGET_FMT_lx ", PA: " |
371 |
TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", |
372 |
va2, pa, pde); |
373 |
} |
374 |
} |
375 |
} |
376 |
} |
377 |
} |
378 |
} |
379 |
printf("MMU dump ends\n");
|
380 |
} |
381 |
#endif /* DEBUG_MMU */ |
382 |
|
383 |
#else /* !TARGET_SPARC64 */ |
384 |
/*
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385 |
* UltraSparc IIi I/DMMUs
|
386 |
*/
|
387 |
static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot, |
388 |
int *access_index, target_ulong address, int rw, |
389 |
int is_user)
|
390 |
{ |
391 |
target_ulong mask; |
392 |
unsigned int i; |
393 |
|
394 |
if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ |
395 |
*physical = address; |
396 |
*prot = PAGE_READ | PAGE_WRITE; |
397 |
return 0; |
398 |
} |
399 |
|
400 |
for (i = 0; i < 64; i++) { |
401 |
switch ((env->dtlb_tte[i] >> 61) & 3) { |
402 |
default:
|
403 |
case 0x0: // 8k |
404 |
mask = 0xffffffffffffe000ULL;
|
405 |
break;
|
406 |
case 0x1: // 64k |
407 |
mask = 0xffffffffffff0000ULL;
|
408 |
break;
|
409 |
case 0x2: // 512k |
410 |
mask = 0xfffffffffff80000ULL;
|
411 |
break;
|
412 |
case 0x3: // 4M |
413 |
mask = 0xffffffffffc00000ULL;
|
414 |
break;
|
415 |
} |
416 |
// ctx match, vaddr match?
|
417 |
if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
418 |
(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
|
419 |
// valid, access ok?
|
420 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 || |
421 |
((env->dtlb_tte[i] & 0x4) && is_user) ||
|
422 |
(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { |
423 |
if (env->dmmuregs[3]) /* Fault status register */ |
424 |
env->dmmuregs[3] = 2; /* overflow (not read before another fault) */ |
425 |
env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; |
426 |
env->dmmuregs[4] = address; /* Fault address register */ |
427 |
env->exception_index = TT_DFAULT; |
428 |
#ifdef DEBUG_MMU
|
429 |
printf("DFAULT at 0x%" PRIx64 "\n", address); |
430 |
#endif
|
431 |
return 1; |
432 |
} |
433 |
*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
434 |
*prot = PAGE_READ; |
435 |
if (env->dtlb_tte[i] & 0x2) |
436 |
*prot |= PAGE_WRITE; |
437 |
return 0; |
438 |
} |
439 |
} |
440 |
#ifdef DEBUG_MMU
|
441 |
printf("DMISS at 0x%" PRIx64 "\n", address); |
442 |
#endif
|
443 |
env->exception_index = TT_DMISS; |
444 |
return 1; |
445 |
} |
446 |
|
447 |
static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot, |
448 |
int *access_index, target_ulong address, int rw, |
449 |
int is_user)
|
450 |
{ |
451 |
target_ulong mask; |
452 |
unsigned int i; |
453 |
|
454 |
if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */ |
455 |
*physical = address; |
456 |
*prot = PAGE_EXEC; |
457 |
return 0; |
458 |
} |
459 |
|
460 |
for (i = 0; i < 64; i++) { |
461 |
switch ((env->itlb_tte[i] >> 61) & 3) { |
462 |
default:
|
463 |
case 0x0: // 8k |
464 |
mask = 0xffffffffffffe000ULL;
|
465 |
break;
|
466 |
case 0x1: // 64k |
467 |
mask = 0xffffffffffff0000ULL;
|
468 |
break;
|
469 |
case 0x2: // 512k |
470 |
mask = 0xfffffffffff80000ULL;
|
471 |
break;
|
472 |
case 0x3: // 4M |
473 |
mask = 0xffffffffffc00000ULL;
|
474 |
break;
|
475 |
} |
476 |
// ctx match, vaddr match?
|
477 |
if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
478 |
(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
|
479 |
// valid, access ok?
|
480 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 || |
481 |
((env->itlb_tte[i] & 0x4) && is_user)) {
|
482 |
if (env->immuregs[3]) /* Fault status register */ |
483 |
env->immuregs[3] = 2; /* overflow (not read before another fault) */ |
484 |
env->immuregs[3] |= (is_user << 3) | 1; |
485 |
env->exception_index = TT_TFAULT; |
486 |
#ifdef DEBUG_MMU
|
487 |
printf("TFAULT at 0x%" PRIx64 "\n", address); |
488 |
#endif
|
489 |
return 1; |
490 |
} |
491 |
*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
492 |
*prot = PAGE_EXEC; |
493 |
return 0; |
494 |
} |
495 |
} |
496 |
#ifdef DEBUG_MMU
|
497 |
printf("TMISS at 0x%" PRIx64 "\n", address); |
498 |
#endif
|
499 |
env->exception_index = TT_TMISS; |
500 |
return 1; |
501 |
} |
502 |
|
503 |
static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
504 |
int *prot, int *access_index, |
505 |
target_ulong address, int rw, int mmu_idx) |
506 |
{ |
507 |
int is_user = mmu_idx == MMU_USER_IDX;
|
508 |
|
509 |
if (rw == 2) |
510 |
return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
|
511 |
else
|
512 |
return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
|
513 |
} |
514 |
|
515 |
/* Perform address translation */
|
516 |
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
517 |
int mmu_idx, int is_softmmu) |
518 |
{ |
519 |
target_ulong virt_addr, vaddr; |
520 |
target_phys_addr_t paddr; |
521 |
int error_code = 0, prot, ret = 0, access_index; |
522 |
|
523 |
error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx); |
524 |
if (error_code == 0) { |
525 |
virt_addr = address & TARGET_PAGE_MASK; |
526 |
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
|
527 |
#ifdef DEBUG_MMU
|
528 |
printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr); |
529 |
#endif
|
530 |
ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
531 |
return ret;
|
532 |
} |
533 |
// XXX
|
534 |
return 1; |
535 |
} |
536 |
|
537 |
#ifdef DEBUG_MMU
|
538 |
void dump_mmu(CPUState *env)
|
539 |
{ |
540 |
unsigned int i; |
541 |
const char *mask; |
542 |
|
543 |
printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]); |
544 |
if ((env->lsu & DMMU_E) == 0) { |
545 |
printf("DMMU disabled\n");
|
546 |
} else {
|
547 |
printf("DMMU dump:\n");
|
548 |
for (i = 0; i < 64; i++) { |
549 |
switch ((env->dtlb_tte[i] >> 61) & 3) { |
550 |
default:
|
551 |
case 0x0: |
552 |
mask = " 8k";
|
553 |
break;
|
554 |
case 0x1: |
555 |
mask = " 64k";
|
556 |
break;
|
557 |
case 0x2: |
558 |
mask = "512k";
|
559 |
break;
|
560 |
case 0x3: |
561 |
mask = " 4M";
|
562 |
break;
|
563 |
} |
564 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { |
565 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n", |
566 |
env->dtlb_tag[i] & ~0x1fffULL,
|
567 |
env->dtlb_tte[i] & 0x1ffffffe000ULL,
|
568 |
mask, |
569 |
env->dtlb_tte[i] & 0x4? "priv": "user", |
570 |
env->dtlb_tte[i] & 0x2? "RW": "RO", |
571 |
env->dtlb_tte[i] & 0x40? "locked": "unlocked", |
572 |
env->dtlb_tag[i] & 0x1fffULL);
|
573 |
} |
574 |
} |
575 |
} |
576 |
if ((env->lsu & IMMU_E) == 0) { |
577 |
printf("IMMU disabled\n");
|
578 |
} else {
|
579 |
printf("IMMU dump:\n");
|
580 |
for (i = 0; i < 64; i++) { |
581 |
switch ((env->itlb_tte[i] >> 61) & 3) { |
582 |
default:
|
583 |
case 0x0: |
584 |
mask = " 8k";
|
585 |
break;
|
586 |
case 0x1: |
587 |
mask = " 64k";
|
588 |
break;
|
589 |
case 0x2: |
590 |
mask = "512k";
|
591 |
break;
|
592 |
case 0x3: |
593 |
mask = " 4M";
|
594 |
break;
|
595 |
} |
596 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { |
597 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n", |
598 |
env->itlb_tag[i] & ~0x1fffULL,
|
599 |
env->itlb_tte[i] & 0x1ffffffe000ULL,
|
600 |
mask, |
601 |
env->itlb_tte[i] & 0x4? "priv": "user", |
602 |
env->itlb_tte[i] & 0x40? "locked": "unlocked", |
603 |
env->itlb_tag[i] & 0x1fffULL);
|
604 |
} |
605 |
} |
606 |
} |
607 |
} |
608 |
#endif /* DEBUG_MMU */ |
609 |
|
610 |
#endif /* TARGET_SPARC64 */ |
611 |
#endif /* !CONFIG_USER_ONLY */ |
612 |
|
613 |
|
614 |
#if defined(CONFIG_USER_ONLY)
|
615 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
616 |
{ |
617 |
return addr;
|
618 |
} |
619 |
|
620 |
#else
|
621 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
622 |
{ |
623 |
target_phys_addr_t phys_addr; |
624 |
int prot, access_index;
|
625 |
|
626 |
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, |
627 |
MMU_KERNEL_IDX) != 0)
|
628 |
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
|
629 |
0, MMU_KERNEL_IDX) != 0) |
630 |
return -1; |
631 |
if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
|
632 |
return -1; |
633 |
return phys_addr;
|
634 |
} |
635 |
#endif
|
636 |
|
637 |
void memcpy32(target_ulong *dst, const target_ulong *src) |
638 |
{ |
639 |
dst[0] = src[0]; |
640 |
dst[1] = src[1]; |
641 |
dst[2] = src[2]; |
642 |
dst[3] = src[3]; |
643 |
dst[4] = src[4]; |
644 |
dst[5] = src[5]; |
645 |
dst[6] = src[6]; |
646 |
dst[7] = src[7]; |
647 |
} |
648 |
|
649 |
void helper_flush(target_ulong addr)
|
650 |
{ |
651 |
addr &= ~7;
|
652 |
tb_invalidate_page_range(addr, addr + 8);
|
653 |
} |
654 |
|
655 |
void cpu_reset(CPUSPARCState *env)
|
656 |
{ |
657 |
tlb_flush(env, 1);
|
658 |
env->cwp = 0;
|
659 |
env->wim = 1;
|
660 |
env->regwptr = env->regbase + (env->cwp * 16);
|
661 |
#if defined(CONFIG_USER_ONLY)
|
662 |
env->user_mode_only = 1;
|
663 |
#ifdef TARGET_SPARC64
|
664 |
env->cleanwin = NWINDOWS - 2;
|
665 |
env->cansave = NWINDOWS - 2;
|
666 |
env->pstate = PS_RMO | PS_PEF | PS_IE; |
667 |
env->asi = 0x82; // Primary no-fault |
668 |
#endif
|
669 |
#else
|
670 |
env->psret = 0;
|
671 |
env->psrs = 1;
|
672 |
env->psrps = 1;
|
673 |
#ifdef TARGET_SPARC64
|
674 |
env->pstate = PS_PRIV; |
675 |
env->hpstate = HS_PRIV; |
676 |
env->pc = 0x1fff0000000ULL;
|
677 |
env->tsptr = &env->ts[env->tl]; |
678 |
#else
|
679 |
env->pc = 0;
|
680 |
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
681 |
env->mmuregs[0] |= env->mmu_bm;
|
682 |
#endif
|
683 |
env->npc = env->pc + 4;
|
684 |
#endif
|
685 |
} |
686 |
|
687 |
CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
688 |
{ |
689 |
CPUSPARCState *env; |
690 |
const sparc_def_t *def;
|
691 |
|
692 |
def = cpu_sparc_find_by_name(cpu_model); |
693 |
if (!def)
|
694 |
return NULL; |
695 |
|
696 |
env = qemu_mallocz(sizeof(CPUSPARCState));
|
697 |
if (!env)
|
698 |
return NULL; |
699 |
cpu_exec_init(env); |
700 |
env->cpu_model_str = cpu_model; |
701 |
env->version = def->iu_version; |
702 |
env->fsr = def->fpu_version; |
703 |
#if !defined(TARGET_SPARC64)
|
704 |
env->mmu_bm = def->mmu_bm; |
705 |
env->mmu_ctpr_mask = def->mmu_ctpr_mask; |
706 |
env->mmu_cxr_mask = def->mmu_cxr_mask; |
707 |
env->mmu_sfsr_mask = def->mmu_sfsr_mask; |
708 |
env->mmu_trcr_mask = def->mmu_trcr_mask; |
709 |
env->mmuregs[0] |= def->mmu_version;
|
710 |
cpu_sparc_set_id(env, 0);
|
711 |
#endif
|
712 |
|
713 |
gen_intermediate_code_init(env); |
714 |
|
715 |
cpu_reset(env); |
716 |
|
717 |
return env;
|
718 |
} |
719 |
|
720 |
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
721 |
{ |
722 |
#if !defined(TARGET_SPARC64)
|
723 |
env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
724 |
#endif
|
725 |
} |
726 |
|
727 |
static const sparc_def_t sparc_defs[] = { |
728 |
#ifdef TARGET_SPARC64
|
729 |
{ |
730 |
.name = "Fujitsu Sparc64",
|
731 |
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) |
732 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
733 |
.fpu_version = 0x00000000,
|
734 |
.mmu_version = 0,
|
735 |
}, |
736 |
{ |
737 |
.name = "Fujitsu Sparc64 III",
|
738 |
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) |
739 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
740 |
.fpu_version = 0x00000000,
|
741 |
.mmu_version = 0,
|
742 |
}, |
743 |
{ |
744 |
.name = "Fujitsu Sparc64 IV",
|
745 |
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) |
746 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
747 |
.fpu_version = 0x00000000,
|
748 |
.mmu_version = 0,
|
749 |
}, |
750 |
{ |
751 |
.name = "Fujitsu Sparc64 V",
|
752 |
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) |
753 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
754 |
.fpu_version = 0x00000000,
|
755 |
.mmu_version = 0,
|
756 |
}, |
757 |
{ |
758 |
.name = "TI UltraSparc I",
|
759 |
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
760 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
761 |
.fpu_version = 0x00000000,
|
762 |
.mmu_version = 0,
|
763 |
}, |
764 |
{ |
765 |
.name = "TI UltraSparc II",
|
766 |
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) |
767 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
768 |
.fpu_version = 0x00000000,
|
769 |
.mmu_version = 0,
|
770 |
}, |
771 |
{ |
772 |
.name = "TI UltraSparc IIi",
|
773 |
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) |
774 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
775 |
.fpu_version = 0x00000000,
|
776 |
.mmu_version = 0,
|
777 |
}, |
778 |
{ |
779 |
.name = "TI UltraSparc IIe",
|
780 |
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) |
781 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
782 |
.fpu_version = 0x00000000,
|
783 |
.mmu_version = 0,
|
784 |
}, |
785 |
{ |
786 |
.name = "Sun UltraSparc III",
|
787 |
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) |
788 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
789 |
.fpu_version = 0x00000000,
|
790 |
.mmu_version = 0,
|
791 |
}, |
792 |
{ |
793 |
.name = "Sun UltraSparc III Cu",
|
794 |
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) |
795 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
796 |
.fpu_version = 0x00000000,
|
797 |
.mmu_version = 0,
|
798 |
}, |
799 |
{ |
800 |
.name = "Sun UltraSparc IIIi",
|
801 |
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) |
802 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
803 |
.fpu_version = 0x00000000,
|
804 |
.mmu_version = 0,
|
805 |
}, |
806 |
{ |
807 |
.name = "Sun UltraSparc IV",
|
808 |
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) |
809 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
810 |
.fpu_version = 0x00000000,
|
811 |
.mmu_version = 0,
|
812 |
}, |
813 |
{ |
814 |
.name = "Sun UltraSparc IV+",
|
815 |
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) |
816 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
817 |
.fpu_version = 0x00000000,
|
818 |
.mmu_version = 0,
|
819 |
}, |
820 |
{ |
821 |
.name = "Sun UltraSparc IIIi+",
|
822 |
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) |
823 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
824 |
.fpu_version = 0x00000000,
|
825 |
.mmu_version = 0,
|
826 |
}, |
827 |
{ |
828 |
.name = "NEC UltraSparc I",
|
829 |
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
830 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
831 |
.fpu_version = 0x00000000,
|
832 |
.mmu_version = 0,
|
833 |
}, |
834 |
#else
|
835 |
{ |
836 |
.name = "Fujitsu MB86900",
|
837 |
.iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
838 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
839 |
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
840 |
.mmu_bm = 0x00004000,
|
841 |
.mmu_ctpr_mask = 0x007ffff0,
|
842 |
.mmu_cxr_mask = 0x0000003f,
|
843 |
.mmu_sfsr_mask = 0xffffffff,
|
844 |
.mmu_trcr_mask = 0xffffffff,
|
845 |
}, |
846 |
{ |
847 |
.name = "Fujitsu MB86904",
|
848 |
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
849 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
850 |
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
851 |
.mmu_bm = 0x00004000,
|
852 |
.mmu_ctpr_mask = 0x00ffffc0,
|
853 |
.mmu_cxr_mask = 0x000000ff,
|
854 |
.mmu_sfsr_mask = 0x00016fff,
|
855 |
.mmu_trcr_mask = 0x00ffffff,
|
856 |
}, |
857 |
{ |
858 |
.name = "Fujitsu MB86907",
|
859 |
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
860 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
861 |
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
862 |
.mmu_bm = 0x00004000,
|
863 |
.mmu_ctpr_mask = 0xffffffc0,
|
864 |
.mmu_cxr_mask = 0x000000ff,
|
865 |
.mmu_sfsr_mask = 0x00016fff,
|
866 |
.mmu_trcr_mask = 0xffffffff,
|
867 |
}, |
868 |
{ |
869 |
.name = "LSI L64811",
|
870 |
.iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
871 |
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
872 |
.mmu_version = 0x10 << 24, |
873 |
.mmu_bm = 0x00004000,
|
874 |
.mmu_ctpr_mask = 0x007ffff0,
|
875 |
.mmu_cxr_mask = 0x0000003f,
|
876 |
.mmu_sfsr_mask = 0xffffffff,
|
877 |
.mmu_trcr_mask = 0xffffffff,
|
878 |
}, |
879 |
{ |
880 |
.name = "Cypress CY7C601",
|
881 |
.iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
882 |
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
883 |
.mmu_version = 0x10 << 24, |
884 |
.mmu_bm = 0x00004000,
|
885 |
.mmu_ctpr_mask = 0x007ffff0,
|
886 |
.mmu_cxr_mask = 0x0000003f,
|
887 |
.mmu_sfsr_mask = 0xffffffff,
|
888 |
.mmu_trcr_mask = 0xffffffff,
|
889 |
}, |
890 |
{ |
891 |
.name = "Cypress CY7C611",
|
892 |
.iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
893 |
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
894 |
.mmu_version = 0x10 << 24, |
895 |
.mmu_bm = 0x00004000,
|
896 |
.mmu_ctpr_mask = 0x007ffff0,
|
897 |
.mmu_cxr_mask = 0x0000003f,
|
898 |
.mmu_sfsr_mask = 0xffffffff,
|
899 |
.mmu_trcr_mask = 0xffffffff,
|
900 |
}, |
901 |
{ |
902 |
.name = "TI SuperSparc II",
|
903 |
.iu_version = 0x40000000,
|
904 |
.fpu_version = 0 << 17, |
905 |
.mmu_version = 0x04000000,
|
906 |
.mmu_bm = 0x00002000,
|
907 |
.mmu_ctpr_mask = 0xffffffc0,
|
908 |
.mmu_cxr_mask = 0x0000ffff,
|
909 |
.mmu_sfsr_mask = 0xffffffff,
|
910 |
.mmu_trcr_mask = 0xffffffff,
|
911 |
}, |
912 |
{ |
913 |
.name = "TI MicroSparc I",
|
914 |
.iu_version = 0x41000000,
|
915 |
.fpu_version = 4 << 17, |
916 |
.mmu_version = 0x41000000,
|
917 |
.mmu_bm = 0x00004000,
|
918 |
.mmu_ctpr_mask = 0x007ffff0,
|
919 |
.mmu_cxr_mask = 0x0000003f,
|
920 |
.mmu_sfsr_mask = 0x00016fff,
|
921 |
.mmu_trcr_mask = 0x0000003f,
|
922 |
}, |
923 |
{ |
924 |
.name = "TI MicroSparc II",
|
925 |
.iu_version = 0x42000000,
|
926 |
.fpu_version = 4 << 17, |
927 |
.mmu_version = 0x02000000,
|
928 |
.mmu_bm = 0x00004000,
|
929 |
.mmu_ctpr_mask = 0x00ffffc0,
|
930 |
.mmu_cxr_mask = 0x000000ff,
|
931 |
.mmu_sfsr_mask = 0x00016fff,
|
932 |
.mmu_trcr_mask = 0x00ffffff,
|
933 |
}, |
934 |
{ |
935 |
.name = "TI MicroSparc IIep",
|
936 |
.iu_version = 0x42000000,
|
937 |
.fpu_version = 4 << 17, |
938 |
.mmu_version = 0x04000000,
|
939 |
.mmu_bm = 0x00004000,
|
940 |
.mmu_ctpr_mask = 0x00ffffc0,
|
941 |
.mmu_cxr_mask = 0x000000ff,
|
942 |
.mmu_sfsr_mask = 0x00016bff,
|
943 |
.mmu_trcr_mask = 0x00ffffff,
|
944 |
}, |
945 |
{ |
946 |
.name = "TI SuperSparc 51",
|
947 |
.iu_version = 0x43000000,
|
948 |
.fpu_version = 0 << 17, |
949 |
.mmu_version = 0x04000000,
|
950 |
.mmu_bm = 0x00002000,
|
951 |
.mmu_ctpr_mask = 0xffffffc0,
|
952 |
.mmu_cxr_mask = 0x0000ffff,
|
953 |
.mmu_sfsr_mask = 0xffffffff,
|
954 |
.mmu_trcr_mask = 0xffffffff,
|
955 |
}, |
956 |
{ |
957 |
.name = "TI SuperSparc 61",
|
958 |
.iu_version = 0x44000000,
|
959 |
.fpu_version = 0 << 17, |
960 |
.mmu_version = 0x04000000,
|
961 |
.mmu_bm = 0x00002000,
|
962 |
.mmu_ctpr_mask = 0xffffffc0,
|
963 |
.mmu_cxr_mask = 0x0000ffff,
|
964 |
.mmu_sfsr_mask = 0xffffffff,
|
965 |
.mmu_trcr_mask = 0xffffffff,
|
966 |
}, |
967 |
{ |
968 |
.name = "Ross RT625",
|
969 |
.iu_version = 0x1e000000,
|
970 |
.fpu_version = 1 << 17, |
971 |
.mmu_version = 0x1e000000,
|
972 |
.mmu_bm = 0x00004000,
|
973 |
.mmu_ctpr_mask = 0x007ffff0,
|
974 |
.mmu_cxr_mask = 0x0000003f,
|
975 |
.mmu_sfsr_mask = 0xffffffff,
|
976 |
.mmu_trcr_mask = 0xffffffff,
|
977 |
}, |
978 |
{ |
979 |
.name = "Ross RT620",
|
980 |
.iu_version = 0x1f000000,
|
981 |
.fpu_version = 1 << 17, |
982 |
.mmu_version = 0x1f000000,
|
983 |
.mmu_bm = 0x00004000,
|
984 |
.mmu_ctpr_mask = 0x007ffff0,
|
985 |
.mmu_cxr_mask = 0x0000003f,
|
986 |
.mmu_sfsr_mask = 0xffffffff,
|
987 |
.mmu_trcr_mask = 0xffffffff,
|
988 |
}, |
989 |
{ |
990 |
.name = "BIT B5010",
|
991 |
.iu_version = 0x20000000,
|
992 |
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
993 |
.mmu_version = 0x20000000,
|
994 |
.mmu_bm = 0x00004000,
|
995 |
.mmu_ctpr_mask = 0x007ffff0,
|
996 |
.mmu_cxr_mask = 0x0000003f,
|
997 |
.mmu_sfsr_mask = 0xffffffff,
|
998 |
.mmu_trcr_mask = 0xffffffff,
|
999 |
}, |
1000 |
{ |
1001 |
.name = "Matsushita MN10501",
|
1002 |
.iu_version = 0x50000000,
|
1003 |
.fpu_version = 0 << 17, |
1004 |
.mmu_version = 0x50000000,
|
1005 |
.mmu_bm = 0x00004000,
|
1006 |
.mmu_ctpr_mask = 0x007ffff0,
|
1007 |
.mmu_cxr_mask = 0x0000003f,
|
1008 |
.mmu_sfsr_mask = 0xffffffff,
|
1009 |
.mmu_trcr_mask = 0xffffffff,
|
1010 |
}, |
1011 |
{ |
1012 |
.name = "Weitek W8601",
|
1013 |
.iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
1014 |
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
1015 |
.mmu_version = 0x10 << 24, |
1016 |
.mmu_bm = 0x00004000,
|
1017 |
.mmu_ctpr_mask = 0x007ffff0,
|
1018 |
.mmu_cxr_mask = 0x0000003f,
|
1019 |
.mmu_sfsr_mask = 0xffffffff,
|
1020 |
.mmu_trcr_mask = 0xffffffff,
|
1021 |
}, |
1022 |
{ |
1023 |
.name = "LEON2",
|
1024 |
.iu_version = 0xf2000000,
|
1025 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1026 |
.mmu_version = 0xf2000000,
|
1027 |
.mmu_bm = 0x00004000,
|
1028 |
.mmu_ctpr_mask = 0x007ffff0,
|
1029 |
.mmu_cxr_mask = 0x0000003f,
|
1030 |
.mmu_sfsr_mask = 0xffffffff,
|
1031 |
.mmu_trcr_mask = 0xffffffff,
|
1032 |
}, |
1033 |
{ |
1034 |
.name = "LEON3",
|
1035 |
.iu_version = 0xf3000000,
|
1036 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1037 |
.mmu_version = 0xf3000000,
|
1038 |
.mmu_bm = 0x00004000,
|
1039 |
.mmu_ctpr_mask = 0x007ffff0,
|
1040 |
.mmu_cxr_mask = 0x0000003f,
|
1041 |
.mmu_sfsr_mask = 0xffffffff,
|
1042 |
.mmu_trcr_mask = 0xffffffff,
|
1043 |
}, |
1044 |
#endif
|
1045 |
}; |
1046 |
|
1047 |
static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name) |
1048 |
{ |
1049 |
unsigned int i; |
1050 |
|
1051 |
for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
1052 |
if (strcasecmp(name, sparc_defs[i].name) == 0) { |
1053 |
return &sparc_defs[i];
|
1054 |
} |
1055 |
} |
1056 |
return NULL; |
1057 |
} |
1058 |
|
1059 |
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
1060 |
{ |
1061 |
unsigned int i; |
1062 |
|
1063 |
for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
1064 |
(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n", |
1065 |
sparc_defs[i].name, |
1066 |
sparc_defs[i].iu_version, |
1067 |
sparc_defs[i].fpu_version, |
1068 |
sparc_defs[i].mmu_version); |
1069 |
} |
1070 |
} |
1071 |
|
1072 |
#define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
1073 |
|
1074 |
void cpu_dump_state(CPUState *env, FILE *f,
|
1075 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
1076 |
int flags)
|
1077 |
{ |
1078 |
int i, x;
|
1079 |
|
1080 |
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); |
1081 |
cpu_fprintf(f, "General Registers:\n");
|
1082 |
for (i = 0; i < 4; i++) |
1083 |
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
1084 |
cpu_fprintf(f, "\n");
|
1085 |
for (; i < 8; i++) |
1086 |
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
1087 |
cpu_fprintf(f, "\nCurrent Register Window:\n");
|
1088 |
for (x = 0; x < 3; x++) { |
1089 |
for (i = 0; i < 4; i++) |
1090 |
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
1091 |
(x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
1092 |
env->regwptr[i + x * 8]);
|
1093 |
cpu_fprintf(f, "\n");
|
1094 |
for (; i < 8; i++) |
1095 |
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
1096 |
(x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
1097 |
env->regwptr[i + x * 8]);
|
1098 |
cpu_fprintf(f, "\n");
|
1099 |
} |
1100 |
cpu_fprintf(f, "\nFloating Point Registers:\n");
|
1101 |
for (i = 0; i < 32; i++) { |
1102 |
if ((i & 3) == 0) |
1103 |
cpu_fprintf(f, "%%f%02d:", i);
|
1104 |
cpu_fprintf(f, " %016lf", env->fpr[i]);
|
1105 |
if ((i & 3) == 3) |
1106 |
cpu_fprintf(f, "\n");
|
1107 |
} |
1108 |
#ifdef TARGET_SPARC64
|
1109 |
cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
|
1110 |
env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
1111 |
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
|
1112 |
env->cansave, env->canrestore, env->otherwin, env->wstate, |
1113 |
env->cleanwin, NWINDOWS - 1 - env->cwp);
|
1114 |
#else
|
1115 |
cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
|
1116 |
GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
1117 |
GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
1118 |
env->psrs?'S':'-', env->psrps?'P':'-', |
1119 |
env->psret?'E':'-', env->wim); |
1120 |
#endif
|
1121 |
cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
|
1122 |
} |
1123 |
|
1124 |
#ifdef TARGET_SPARC64
|
1125 |
#if !defined(CONFIG_USER_ONLY)
|
1126 |
#include "qemu-common.h" |
1127 |
#include "hw/irq.h" |
1128 |
#include "qemu-timer.h" |
1129 |
#endif
|
1130 |
|
1131 |
void helper_tick_set_count(void *opaque, uint64_t count) |
1132 |
{ |
1133 |
#if !defined(CONFIG_USER_ONLY)
|
1134 |
ptimer_set_count(opaque, -count); |
1135 |
#endif
|
1136 |
} |
1137 |
|
1138 |
uint64_t helper_tick_get_count(void *opaque)
|
1139 |
{ |
1140 |
#if !defined(CONFIG_USER_ONLY)
|
1141 |
return -ptimer_get_count(opaque);
|
1142 |
#else
|
1143 |
return 0; |
1144 |
#endif
|
1145 |
} |
1146 |
|
1147 |
void helper_tick_set_limit(void *opaque, uint64_t limit) |
1148 |
{ |
1149 |
#if !defined(CONFIG_USER_ONLY)
|
1150 |
ptimer_set_limit(opaque, -limit, 0);
|
1151 |
#endif
|
1152 |
} |
1153 |
#endif
|