root / hw / spapr.c @ 25f8e2f5
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1 | 9fdf0c29 | David Gibson | /*
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2 | 9fdf0c29 | David Gibson | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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3 | 9fdf0c29 | David Gibson | *
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4 | 9fdf0c29 | David Gibson | * Copyright (c) 2004-2007 Fabrice Bellard
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5 | 9fdf0c29 | David Gibson | * Copyright (c) 2007 Jocelyn Mayer
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6 | 9fdf0c29 | David Gibson | * Copyright (c) 2010 David Gibson, IBM Corporation.
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7 | 9fdf0c29 | David Gibson | *
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8 | 9fdf0c29 | David Gibson | * Permission is hereby granted, free of charge, to any person obtaining a copy
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9 | 9fdf0c29 | David Gibson | * of this software and associated documentation files (the "Software"), to deal
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10 | 9fdf0c29 | David Gibson | * in the Software without restriction, including without limitation the rights
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11 | 9fdf0c29 | David Gibson | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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12 | 9fdf0c29 | David Gibson | * copies of the Software, and to permit persons to whom the Software is
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13 | 9fdf0c29 | David Gibson | * furnished to do so, subject to the following conditions:
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14 | 9fdf0c29 | David Gibson | *
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15 | 9fdf0c29 | David Gibson | * The above copyright notice and this permission notice shall be included in
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16 | 9fdf0c29 | David Gibson | * all copies or substantial portions of the Software.
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17 | 9fdf0c29 | David Gibson | *
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18 | 9fdf0c29 | David Gibson | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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19 | 9fdf0c29 | David Gibson | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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20 | 9fdf0c29 | David Gibson | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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21 | 9fdf0c29 | David Gibson | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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22 | 9fdf0c29 | David Gibson | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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23 | 9fdf0c29 | David Gibson | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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24 | 9fdf0c29 | David Gibson | * THE SOFTWARE.
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25 | 9fdf0c29 | David Gibson | *
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26 | 9fdf0c29 | David Gibson | */
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27 | 9fdf0c29 | David Gibson | #include "sysemu.h" |
28 | 9fdf0c29 | David Gibson | #include "hw.h" |
29 | 9fdf0c29 | David Gibson | #include "elf.h" |
30 | 8d90ad90 | David Gibson | #include "net.h" |
31 | 6e270446 | Ben Herrenschmidt | #include "blockdev.h" |
32 | 9fdf0c29 | David Gibson | |
33 | 9fdf0c29 | David Gibson | #include "hw/boards.h" |
34 | 9fdf0c29 | David Gibson | #include "hw/ppc.h" |
35 | 9fdf0c29 | David Gibson | #include "hw/loader.h" |
36 | 9fdf0c29 | David Gibson | |
37 | 9fdf0c29 | David Gibson | #include "hw/spapr.h" |
38 | 4040ab72 | David Gibson | #include "hw/spapr_vio.h" |
39 | b5cec4c5 | David Gibson | #include "hw/xics.h" |
40 | 9fdf0c29 | David Gibson | |
41 | 9fdf0c29 | David Gibson | #include <libfdt.h> |
42 | 9fdf0c29 | David Gibson | |
43 | 9fdf0c29 | David Gibson | #define KERNEL_LOAD_ADDR 0x00000000 |
44 | 9fdf0c29 | David Gibson | #define INITRD_LOAD_ADDR 0x02800000 |
45 | 9fdf0c29 | David Gibson | #define FDT_MAX_SIZE 0x10000 |
46 | 39ac8455 | David Gibson | #define RTAS_MAX_SIZE 0x10000 |
47 | a9f8ad8f | David Gibson | #define FW_MAX_SIZE 0x400000 |
48 | a9f8ad8f | David Gibson | #define FW_FILE_NAME "slof.bin" |
49 | a9f8ad8f | David Gibson | |
50 | a9f8ad8f | David Gibson | #define MIN_RAM_SLOF 512UL |
51 | 9fdf0c29 | David Gibson | |
52 | 9fdf0c29 | David Gibson | #define TIMEBASE_FREQ 512000000ULL |
53 | 9fdf0c29 | David Gibson | |
54 | 9fdf0c29 | David Gibson | #define MAX_CPUS 32 |
55 | b5cec4c5 | David Gibson | #define XICS_IRQS 1024 |
56 | 9fdf0c29 | David Gibson | |
57 | 9fdf0c29 | David Gibson | sPAPREnvironment *spapr; |
58 | 9fdf0c29 | David Gibson | |
59 | a3467baa | David Gibson | static void *spapr_create_fdt_skel(const char *cpu_model, |
60 | a3467baa | David Gibson | target_phys_addr_t initrd_base, |
61 | a3467baa | David Gibson | target_phys_addr_t initrd_size, |
62 | a3467baa | David Gibson | const char *boot_device, |
63 | a3467baa | David Gibson | const char *kernel_cmdline, |
64 | a3467baa | David Gibson | long hash_shift)
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65 | 9fdf0c29 | David Gibson | { |
66 | 9fdf0c29 | David Gibson | void *fdt;
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67 | c7a5c0c9 | David Gibson | CPUState *env; |
68 | a3467baa | David Gibson | uint64_t mem_reg_property[] = { 0, cpu_to_be64(ram_size) };
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69 | 9fdf0c29 | David Gibson | uint32_t start_prop = cpu_to_be32(initrd_base); |
70 | 9fdf0c29 | David Gibson | uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); |
71 | f43e3525 | David Gibson | uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
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72 | ee86dfee | David Gibson | char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" |
73 | ed120055 | David Gibson | "\0hcall-tce\0hcall-vio\0hcall-splpar";
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74 | b5cec4c5 | David Gibson | uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
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75 | 9fdf0c29 | David Gibson | int i;
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76 | 9fdf0c29 | David Gibson | char *modelname;
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77 | 9fdf0c29 | David Gibson | |
78 | 9fdf0c29 | David Gibson | #define _FDT(exp) \
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79 | 9fdf0c29 | David Gibson | do { \
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80 | 9fdf0c29 | David Gibson | int ret = (exp); \
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81 | 9fdf0c29 | David Gibson | if (ret < 0) { \ |
82 | 9fdf0c29 | David Gibson | fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
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83 | 9fdf0c29 | David Gibson | #exp, fdt_strerror(ret)); \
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84 | 9fdf0c29 | David Gibson | exit(1); \
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85 | 9fdf0c29 | David Gibson | } \ |
86 | 9fdf0c29 | David Gibson | } while (0) |
87 | 9fdf0c29 | David Gibson | |
88 | 9fdf0c29 | David Gibson | fdt = qemu_mallocz(FDT_MAX_SIZE); |
89 | 9fdf0c29 | David Gibson | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
90 | 9fdf0c29 | David Gibson | |
91 | 9fdf0c29 | David Gibson | _FDT((fdt_finish_reservemap(fdt))); |
92 | 9fdf0c29 | David Gibson | |
93 | 9fdf0c29 | David Gibson | /* Root node */
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94 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, "")));
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95 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); |
96 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "model", "qemu,emulated-pSeries-LPAR"))); |
97 | 9fdf0c29 | David Gibson | |
98 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); |
99 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); |
100 | 9fdf0c29 | David Gibson | |
101 | 9fdf0c29 | David Gibson | /* /chosen */
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102 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, "chosen")));
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103 | 9fdf0c29 | David Gibson | |
104 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
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105 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "linux,initrd-start",
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106 | 9fdf0c29 | David Gibson | &start_prop, sizeof(start_prop))));
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107 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "linux,initrd-end",
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108 | 9fdf0c29 | David Gibson | &end_prop, sizeof(end_prop))));
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109 | a9f8ad8f | David Gibson | _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
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110 | 9fdf0c29 | David Gibson | |
111 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); |
112 | 9fdf0c29 | David Gibson | |
113 | 9fdf0c29 | David Gibson | /* memory node */
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114 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, "memory@0")));
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115 | 9fdf0c29 | David Gibson | |
116 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "device_type", "memory"))); |
117 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "reg",
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118 | 9fdf0c29 | David Gibson | mem_reg_property, sizeof(mem_reg_property))));
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119 | 9fdf0c29 | David Gibson | |
120 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); |
121 | 9fdf0c29 | David Gibson | |
122 | 9fdf0c29 | David Gibson | /* cpus */
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123 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, "cpus")));
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124 | 9fdf0c29 | David Gibson | |
125 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); |
126 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); |
127 | 9fdf0c29 | David Gibson | |
128 | 9fdf0c29 | David Gibson | modelname = qemu_strdup(cpu_model); |
129 | 9fdf0c29 | David Gibson | |
130 | 9fdf0c29 | David Gibson | for (i = 0; i < strlen(modelname); i++) { |
131 | 9fdf0c29 | David Gibson | modelname[i] = toupper(modelname[i]); |
132 | 9fdf0c29 | David Gibson | } |
133 | 9fdf0c29 | David Gibson | |
134 | c7a5c0c9 | David Gibson | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
135 | c7a5c0c9 | David Gibson | int index = env->cpu_index;
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136 | c7a5c0c9 | David Gibson | uint32_t gserver_prop[] = {cpu_to_be32(index), 0}; /* HACK! */ |
137 | 9fdf0c29 | David Gibson | char *nodename;
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138 | 9fdf0c29 | David Gibson | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), |
139 | 9fdf0c29 | David Gibson | 0xffffffff, 0xffffffff}; |
140 | 9fdf0c29 | David Gibson | |
141 | c7a5c0c9 | David Gibson | if (asprintf(&nodename, "%s@%x", modelname, index) < 0) { |
142 | 9fdf0c29 | David Gibson | fprintf(stderr, "Allocation failure\n");
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143 | 9fdf0c29 | David Gibson | exit(1);
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144 | 9fdf0c29 | David Gibson | } |
145 | 9fdf0c29 | David Gibson | |
146 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, nodename))); |
147 | 9fdf0c29 | David Gibson | |
148 | 9fdf0c29 | David Gibson | free(nodename); |
149 | 9fdf0c29 | David Gibson | |
150 | c7a5c0c9 | David Gibson | _FDT((fdt_property_cell(fdt, "reg", index)));
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151 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "device_type", "cpu"))); |
152 | 9fdf0c29 | David Gibson | |
153 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
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154 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "dcache-block-size",
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155 | 9fdf0c29 | David Gibson | env->dcache_line_size))); |
156 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "icache-block-size",
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157 | 9fdf0c29 | David Gibson | env->icache_line_size))); |
158 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "timebase-frequency", TIMEBASE_FREQ)));
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159 | 9fdf0c29 | David Gibson | /* Hardcode CPU frequency for now. It's kind of arbitrary on
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160 | 9fdf0c29 | David Gibson | * full emu, for kvm we should copy it from the host */
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161 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "clock-frequency", 1000000000))); |
162 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
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163 | f43e3525 | David Gibson | _FDT((fdt_property(fdt, "ibm,pft-size",
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164 | f43e3525 | David Gibson | pft_size_prop, sizeof(pft_size_prop))));
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165 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "status", "okay"))); |
166 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "64-bit", NULL, 0))); |
167 | c7a5c0c9 | David Gibson | _FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", index)));
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168 | b5cec4c5 | David Gibson | _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
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169 | b5cec4c5 | David Gibson | gserver_prop, sizeof(gserver_prop))));
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170 | 9fdf0c29 | David Gibson | |
171 | c7a5c0c9 | David Gibson | if (env->mmu_model & POWERPC_MMU_1TSEG) {
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172 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
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173 | 9fdf0c29 | David Gibson | segs, sizeof(segs))));
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174 | 9fdf0c29 | David Gibson | } |
175 | 9fdf0c29 | David Gibson | |
176 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); |
177 | 9fdf0c29 | David Gibson | } |
178 | 9fdf0c29 | David Gibson | |
179 | 9fdf0c29 | David Gibson | qemu_free(modelname); |
180 | 9fdf0c29 | David Gibson | |
181 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); |
182 | 9fdf0c29 | David Gibson | |
183 | f43e3525 | David Gibson | /* RTAS */
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184 | f43e3525 | David Gibson | _FDT((fdt_begin_node(fdt, "rtas")));
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185 | f43e3525 | David Gibson | |
186 | f43e3525 | David Gibson | _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
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187 | f43e3525 | David Gibson | sizeof(hypertas_prop))));
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188 | f43e3525 | David Gibson | |
189 | f43e3525 | David Gibson | _FDT((fdt_end_node(fdt))); |
190 | f43e3525 | David Gibson | |
191 | b5cec4c5 | David Gibson | /* interrupt controller */
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192 | b5cec4c5 | David Gibson | _FDT((fdt_begin_node(fdt, "interrupt-controller@0")));
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193 | b5cec4c5 | David Gibson | |
194 | b5cec4c5 | David Gibson | _FDT((fdt_property_string(fdt, "device_type",
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195 | b5cec4c5 | David Gibson | "PowerPC-External-Interrupt-Presentation")));
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196 | b5cec4c5 | David Gibson | _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); |
197 | b5cec4c5 | David Gibson | _FDT((fdt_property_cell(fdt, "reg", 0))); |
198 | b5cec4c5 | David Gibson | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
199 | b5cec4c5 | David Gibson | _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
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200 | b5cec4c5 | David Gibson | interrupt_server_ranges_prop, |
201 | b5cec4c5 | David Gibson | sizeof(interrupt_server_ranges_prop))));
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202 | b5cec4c5 | David Gibson | |
203 | b5cec4c5 | David Gibson | _FDT((fdt_end_node(fdt))); |
204 | b5cec4c5 | David Gibson | |
205 | 4040ab72 | David Gibson | /* vdevice */
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206 | 4040ab72 | David Gibson | _FDT((fdt_begin_node(fdt, "vdevice")));
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207 | 4040ab72 | David Gibson | |
208 | 4040ab72 | David Gibson | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); |
209 | 4040ab72 | David Gibson | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); |
210 | 4040ab72 | David Gibson | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); |
211 | 4040ab72 | David Gibson | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); |
212 | b5cec4c5 | David Gibson | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
213 | b5cec4c5 | David Gibson | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
214 | 4040ab72 | David Gibson | |
215 | 4040ab72 | David Gibson | _FDT((fdt_end_node(fdt))); |
216 | 4040ab72 | David Gibson | |
217 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); /* close root node */
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218 | 9fdf0c29 | David Gibson | _FDT((fdt_finish(fdt))); |
219 | 9fdf0c29 | David Gibson | |
220 | a3467baa | David Gibson | return fdt;
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221 | a3467baa | David Gibson | } |
222 | a3467baa | David Gibson | |
223 | a3467baa | David Gibson | static void spapr_finalize_fdt(sPAPREnvironment *spapr, |
224 | a3467baa | David Gibson | target_phys_addr_t fdt_addr, |
225 | a3467baa | David Gibson | target_phys_addr_t rtas_addr, |
226 | a3467baa | David Gibson | target_phys_addr_t rtas_size) |
227 | a3467baa | David Gibson | { |
228 | a3467baa | David Gibson | int ret;
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229 | a3467baa | David Gibson | void *fdt;
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230 | a3467baa | David Gibson | |
231 | a3467baa | David Gibson | fdt = qemu_malloc(FDT_MAX_SIZE); |
232 | a3467baa | David Gibson | |
233 | a3467baa | David Gibson | /* open out the base tree into a temp buffer for the final tweaks */
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234 | a3467baa | David Gibson | _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); |
235 | 4040ab72 | David Gibson | |
236 | 4040ab72 | David Gibson | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); |
237 | 4040ab72 | David Gibson | if (ret < 0) { |
238 | 4040ab72 | David Gibson | fprintf(stderr, "couldn't setup vio devices in fdt\n");
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239 | 4040ab72 | David Gibson | exit(1);
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240 | 4040ab72 | David Gibson | } |
241 | 4040ab72 | David Gibson | |
242 | 39ac8455 | David Gibson | /* RTAS */
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243 | 39ac8455 | David Gibson | ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); |
244 | 39ac8455 | David Gibson | if (ret < 0) { |
245 | 39ac8455 | David Gibson | fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
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246 | 39ac8455 | David Gibson | } |
247 | 39ac8455 | David Gibson | |
248 | 4040ab72 | David Gibson | _FDT((fdt_pack(fdt))); |
249 | 4040ab72 | David Gibson | |
250 | a3467baa | David Gibson | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
251 | 9fdf0c29 | David Gibson | |
252 | a3467baa | David Gibson | qemu_free(fdt); |
253 | 9fdf0c29 | David Gibson | } |
254 | 9fdf0c29 | David Gibson | |
255 | 9fdf0c29 | David Gibson | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
256 | 9fdf0c29 | David Gibson | { |
257 | 9fdf0c29 | David Gibson | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; |
258 | 9fdf0c29 | David Gibson | } |
259 | 9fdf0c29 | David Gibson | |
260 | 9fdf0c29 | David Gibson | static void emulate_spapr_hypercall(CPUState *env) |
261 | 9fdf0c29 | David Gibson | { |
262 | 9fdf0c29 | David Gibson | env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]); |
263 | 9fdf0c29 | David Gibson | } |
264 | 9fdf0c29 | David Gibson | |
265 | a3467baa | David Gibson | static void spapr_reset(void *opaque) |
266 | a3467baa | David Gibson | { |
267 | a3467baa | David Gibson | sPAPREnvironment *spapr = (sPAPREnvironment *)opaque; |
268 | a3467baa | David Gibson | |
269 | a3467baa | David Gibson | fprintf(stderr, "sPAPR reset\n");
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270 | a3467baa | David Gibson | |
271 | a3467baa | David Gibson | /* flush out the hash table */
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272 | a3467baa | David Gibson | memset(spapr->htab, 0, spapr->htab_size);
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273 | a3467baa | David Gibson | |
274 | a3467baa | David Gibson | /* Load the fdt */
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275 | a3467baa | David Gibson | spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, |
276 | a3467baa | David Gibson | spapr->rtas_size); |
277 | a3467baa | David Gibson | |
278 | a3467baa | David Gibson | /* Set up the entry state */
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279 | a3467baa | David Gibson | first_cpu->gpr[3] = spapr->fdt_addr;
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280 | a3467baa | David Gibson | first_cpu->gpr[5] = 0; |
281 | a3467baa | David Gibson | first_cpu->halted = 0;
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282 | a3467baa | David Gibson | first_cpu->nip = spapr->entry_point; |
283 | a3467baa | David Gibson | |
284 | a3467baa | David Gibson | } |
285 | a3467baa | David Gibson | |
286 | 9fdf0c29 | David Gibson | /* pSeries LPAR / sPAPR hardware init */
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287 | 9fdf0c29 | David Gibson | static void ppc_spapr_init(ram_addr_t ram_size, |
288 | 9fdf0c29 | David Gibson | const char *boot_device, |
289 | 9fdf0c29 | David Gibson | const char *kernel_filename, |
290 | 9fdf0c29 | David Gibson | const char *kernel_cmdline, |
291 | 9fdf0c29 | David Gibson | const char *initrd_filename, |
292 | 9fdf0c29 | David Gibson | const char *cpu_model) |
293 | 9fdf0c29 | David Gibson | { |
294 | c7a5c0c9 | David Gibson | CPUState *env; |
295 | 9fdf0c29 | David Gibson | int i;
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296 | 9fdf0c29 | David Gibson | ram_addr_t ram_offset; |
297 | a3467baa | David Gibson | uint32_t initrd_base; |
298 | a3467baa | David Gibson | long kernel_size, initrd_size, fw_size;
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299 | f43e3525 | David Gibson | long pteg_shift = 17; |
300 | 39ac8455 | David Gibson | char *filename;
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301 | 0201e2da | David Gibson | int irq = 16; |
302 | 9fdf0c29 | David Gibson | |
303 | 9fdf0c29 | David Gibson | spapr = qemu_malloc(sizeof(*spapr));
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304 | 9fdf0c29 | David Gibson | cpu_ppc_hypercall = emulate_spapr_hypercall; |
305 | 9fdf0c29 | David Gibson | |
306 | 9fdf0c29 | David Gibson | /* We place the device tree just below either the top of RAM, or
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307 | 9fdf0c29 | David Gibson | * 2GB, so that it can be processed with 32-bit code if
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308 | 9fdf0c29 | David Gibson | * necessary */
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309 | a3467baa | David Gibson | spapr->fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE;
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310 | a3467baa | David Gibson | spapr->rtas_addr = spapr->fdt_addr - RTAS_MAX_SIZE; |
311 | 9fdf0c29 | David Gibson | |
312 | 9fdf0c29 | David Gibson | /* init CPUs */
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313 | 9fdf0c29 | David Gibson | if (cpu_model == NULL) { |
314 | 9fdf0c29 | David Gibson | cpu_model = "POWER7";
|
315 | 9fdf0c29 | David Gibson | } |
316 | 9fdf0c29 | David Gibson | for (i = 0; i < smp_cpus; i++) { |
317 | c7a5c0c9 | David Gibson | env = cpu_init(cpu_model); |
318 | 9fdf0c29 | David Gibson | |
319 | 9fdf0c29 | David Gibson | if (!env) {
|
320 | 9fdf0c29 | David Gibson | fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
321 | 9fdf0c29 | David Gibson | exit(1);
|
322 | 9fdf0c29 | David Gibson | } |
323 | 9fdf0c29 | David Gibson | /* Set time-base frequency to 512 MHz */
|
324 | 9fdf0c29 | David Gibson | cpu_ppc_tb_init(env, TIMEBASE_FREQ); |
325 | 9fdf0c29 | David Gibson | qemu_register_reset((QEMUResetHandler *)&cpu_reset, env); |
326 | 9fdf0c29 | David Gibson | |
327 | 9fdf0c29 | David Gibson | env->hreset_vector = 0x60;
|
328 | 9fdf0c29 | David Gibson | env->hreset_excp_prefix = 0;
|
329 | c7a5c0c9 | David Gibson | env->gpr[3] = env->cpu_index;
|
330 | 9fdf0c29 | David Gibson | } |
331 | 9fdf0c29 | David Gibson | |
332 | 9fdf0c29 | David Gibson | /* allocate RAM */
|
333 | 9fdf0c29 | David Gibson | ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size); |
334 | 9fdf0c29 | David Gibson | cpu_register_physical_memory(0, ram_size, ram_offset);
|
335 | 9fdf0c29 | David Gibson | |
336 | f43e3525 | David Gibson | /* allocate hash page table. For now we always make this 16mb,
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337 | f43e3525 | David Gibson | * later we should probably make it scale to the size of guest
|
338 | f43e3525 | David Gibson | * RAM */
|
339 | a3467baa | David Gibson | spapr->htab_size = 1ULL << (pteg_shift + 7); |
340 | a3467baa | David Gibson | spapr->htab = qemu_malloc(spapr->htab_size); |
341 | f43e3525 | David Gibson | |
342 | c7a5c0c9 | David Gibson | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
343 | a3467baa | David Gibson | env->external_htab = spapr->htab; |
344 | c7a5c0c9 | David Gibson | env->htab_base = -1;
|
345 | a3467baa | David Gibson | env->htab_mask = spapr->htab_size - 1;
|
346 | f43e3525 | David Gibson | } |
347 | f43e3525 | David Gibson | |
348 | 39ac8455 | David Gibson | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
|
349 | a3467baa | David Gibson | spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, |
350 | a3467baa | David Gibson | ram_size - spapr->rtas_addr); |
351 | a3467baa | David Gibson | if (spapr->rtas_size < 0) { |
352 | 39ac8455 | David Gibson | hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
|
353 | 39ac8455 | David Gibson | exit(1);
|
354 | 39ac8455 | David Gibson | } |
355 | 39ac8455 | David Gibson | qemu_free(filename); |
356 | 39ac8455 | David Gibson | |
357 | b5cec4c5 | David Gibson | /* Set up Interrupt Controller */
|
358 | c7a5c0c9 | David Gibson | spapr->icp = xics_system_init(XICS_IRQS); |
359 | b5cec4c5 | David Gibson | |
360 | b5cec4c5 | David Gibson | /* Set up VIO bus */
|
361 | 4040ab72 | David Gibson | spapr->vio_bus = spapr_vio_bus_init(); |
362 | 4040ab72 | David Gibson | |
363 | 0201e2da | David Gibson | for (i = 0; i < MAX_SERIAL_PORTS; i++, irq++) { |
364 | 4040ab72 | David Gibson | if (serial_hds[i]) {
|
365 | 0201e2da | David Gibson | spapr_vty_create(spapr->vio_bus, i, serial_hds[i], |
366 | 0201e2da | David Gibson | xics_find_qirq(spapr->icp, irq), irq); |
367 | 4040ab72 | David Gibson | } |
368 | 4040ab72 | David Gibson | } |
369 | 9fdf0c29 | David Gibson | |
370 | 8d90ad90 | David Gibson | for (i = 0; i < nb_nics; i++, irq++) { |
371 | 8d90ad90 | David Gibson | NICInfo *nd = &nd_table[i]; |
372 | 8d90ad90 | David Gibson | |
373 | 8d90ad90 | David Gibson | if (!nd->model) {
|
374 | 8d90ad90 | David Gibson | nd->model = qemu_strdup("ibmveth");
|
375 | 8d90ad90 | David Gibson | } |
376 | 8d90ad90 | David Gibson | |
377 | 8d90ad90 | David Gibson | if (strcmp(nd->model, "ibmveth") == 0) { |
378 | 8d90ad90 | David Gibson | spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd,
|
379 | 8d90ad90 | David Gibson | xics_find_qirq(spapr->icp, irq), irq); |
380 | 8d90ad90 | David Gibson | } else {
|
381 | 8d90ad90 | David Gibson | fprintf(stderr, "pSeries (sPAPR) platform does not support "
|
382 | 8d90ad90 | David Gibson | "NIC model '%s' (only ibmveth is supported)\n",
|
383 | 8d90ad90 | David Gibson | nd->model); |
384 | 8d90ad90 | David Gibson | exit(1);
|
385 | 8d90ad90 | David Gibson | } |
386 | 8d90ad90 | David Gibson | } |
387 | 8d90ad90 | David Gibson | |
388 | 6e270446 | Ben Herrenschmidt | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
389 | 6e270446 | Ben Herrenschmidt | spapr_vscsi_create(spapr->vio_bus, 0x2000 + i,
|
390 | 6e270446 | Ben Herrenschmidt | xics_find_qirq(spapr->icp, irq), irq); |
391 | 6e270446 | Ben Herrenschmidt | irq++; |
392 | 6e270446 | Ben Herrenschmidt | } |
393 | 6e270446 | Ben Herrenschmidt | |
394 | 9fdf0c29 | David Gibson | if (kernel_filename) {
|
395 | 9fdf0c29 | David Gibson | uint64_t lowaddr = 0;
|
396 | 9fdf0c29 | David Gibson | |
397 | 9fdf0c29 | David Gibson | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
|
398 | 9fdf0c29 | David Gibson | NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); |
399 | 9fdf0c29 | David Gibson | if (kernel_size < 0) { |
400 | a3467baa | David Gibson | kernel_size = load_image_targphys(kernel_filename, |
401 | a3467baa | David Gibson | KERNEL_LOAD_ADDR, |
402 | a3467baa | David Gibson | ram_size - KERNEL_LOAD_ADDR); |
403 | 9fdf0c29 | David Gibson | } |
404 | 9fdf0c29 | David Gibson | if (kernel_size < 0) { |
405 | 9fdf0c29 | David Gibson | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
406 | 9fdf0c29 | David Gibson | kernel_filename); |
407 | 9fdf0c29 | David Gibson | exit(1);
|
408 | 9fdf0c29 | David Gibson | } |
409 | 9fdf0c29 | David Gibson | |
410 | 9fdf0c29 | David Gibson | /* load initrd */
|
411 | 9fdf0c29 | David Gibson | if (initrd_filename) {
|
412 | 9fdf0c29 | David Gibson | initrd_base = INITRD_LOAD_ADDR; |
413 | 9fdf0c29 | David Gibson | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
414 | 9fdf0c29 | David Gibson | ram_size - initrd_base); |
415 | 9fdf0c29 | David Gibson | if (initrd_size < 0) { |
416 | 9fdf0c29 | David Gibson | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
417 | 9fdf0c29 | David Gibson | initrd_filename); |
418 | 9fdf0c29 | David Gibson | exit(1);
|
419 | 9fdf0c29 | David Gibson | } |
420 | 9fdf0c29 | David Gibson | } else {
|
421 | 9fdf0c29 | David Gibson | initrd_base = 0;
|
422 | 9fdf0c29 | David Gibson | initrd_size = 0;
|
423 | 9fdf0c29 | David Gibson | } |
424 | a3467baa | David Gibson | |
425 | a3467baa | David Gibson | spapr->entry_point = KERNEL_LOAD_ADDR; |
426 | 9fdf0c29 | David Gibson | } else {
|
427 | a9f8ad8f | David Gibson | if (ram_size < (MIN_RAM_SLOF << 20)) { |
428 | a9f8ad8f | David Gibson | fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
|
429 | a9f8ad8f | David Gibson | "%ldM guest RAM\n", MIN_RAM_SLOF);
|
430 | a9f8ad8f | David Gibson | exit(1);
|
431 | a9f8ad8f | David Gibson | } |
432 | a9f8ad8f | David Gibson | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "slof.bin");
|
433 | a9f8ad8f | David Gibson | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
|
434 | a9f8ad8f | David Gibson | if (fw_size < 0) { |
435 | a9f8ad8f | David Gibson | hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
|
436 | a9f8ad8f | David Gibson | exit(1);
|
437 | a9f8ad8f | David Gibson | } |
438 | a9f8ad8f | David Gibson | qemu_free(filename); |
439 | a3467baa | David Gibson | spapr->entry_point = 0x100;
|
440 | a9f8ad8f | David Gibson | initrd_base = 0;
|
441 | a9f8ad8f | David Gibson | initrd_size = 0;
|
442 | a9f8ad8f | David Gibson | |
443 | a9f8ad8f | David Gibson | /* SLOF will startup the secondary CPUs using RTAS,
|
444 | a9f8ad8f | David Gibson | rather than expecting a kexec() style entry */
|
445 | c7a5c0c9 | David Gibson | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
446 | c7a5c0c9 | David Gibson | env->halted = 1;
|
447 | a9f8ad8f | David Gibson | } |
448 | 9fdf0c29 | David Gibson | } |
449 | 9fdf0c29 | David Gibson | |
450 | 9fdf0c29 | David Gibson | /* Prepare the device tree */
|
451 | a3467baa | David Gibson | spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, |
452 | a3467baa | David Gibson | initrd_base, initrd_size, |
453 | a3467baa | David Gibson | boot_device, kernel_cmdline, |
454 | a3467baa | David Gibson | pteg_shift + 7);
|
455 | a3467baa | David Gibson | assert(spapr->fdt_skel != NULL);
|
456 | 9fdf0c29 | David Gibson | |
457 | a3467baa | David Gibson | qemu_register_reset(spapr_reset, spapr); |
458 | 9fdf0c29 | David Gibson | } |
459 | 9fdf0c29 | David Gibson | |
460 | 9fdf0c29 | David Gibson | static QEMUMachine spapr_machine = {
|
461 | 9fdf0c29 | David Gibson | .name = "pseries",
|
462 | 9fdf0c29 | David Gibson | .desc = "pSeries Logical Partition (PAPR compliant)",
|
463 | 9fdf0c29 | David Gibson | .init = ppc_spapr_init, |
464 | 9fdf0c29 | David Gibson | .max_cpus = MAX_CPUS, |
465 | 9fdf0c29 | David Gibson | .no_vga = 1,
|
466 | 9fdf0c29 | David Gibson | .no_parallel = 1,
|
467 | 6e270446 | Ben Herrenschmidt | .use_scsi = 1,
|
468 | 9fdf0c29 | David Gibson | }; |
469 | 9fdf0c29 | David Gibson | |
470 | 9fdf0c29 | David Gibson | static void spapr_machine_init(void) |
471 | 9fdf0c29 | David Gibson | { |
472 | 9fdf0c29 | David Gibson | qemu_register_machine(&spapr_machine); |
473 | 9fdf0c29 | David Gibson | } |
474 | 9fdf0c29 | David Gibson | |
475 | 9fdf0c29 | David Gibson | machine_init(spapr_machine_init); |