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Name Size
cpu.h 14.5 kB
exec.h 1.6 kB
helper.c 73.3 kB
helpers.h 15.9 kB
iwmmxt_helper.c 24.7 kB
machine.c 6.6 kB
neon_helper.c 34.4 kB
op_addsub.h 1.8 kB
op_helper.c 10.5 kB
translate.c 314.1 kB

Latest revisions

# Date Author Comment
2c9adbda 12/07/2010 05:37 pm Peter Maydell

ARM: fix ldrexd/strexd

Correct ldrexd and strexd code to always read and write the
high word of the 64-bit value from addr+4.
Also make ldrexd and strexd agree that for a 64 bit value the
address in env->exclusive_addr is that of the low word.

This fixes the issues reported in...
04595bf6 12/07/2010 05:37 pm Peter Maydell

ARM: Fix decoding of VFP forms of VCVT between float and int/fixed

Correct the decoding of source and destination registers
for the VFP forms of the VCVT instructions which convert
between floating point and integer or fixed-point.

Signed-off-by: Peter Maydell <>...
f73534a5 12/07/2010 05:37 pm Peter Maydell

ARM: Fix decoding of Neon forms of VCVT between float and fixed point

Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted...
d3587ef8 12/07/2010 05:37 pm Peter Maydell

ARM: Fix sense of to_integer bit in Neon VCVT float/int conversion

Signed-off-by: Peter Maydell <>
Reviewed-by: Nathan Froyd <>
09d9487f 12/07/2010 05:37 pm Peter Maydell

ARM: Return correct result for float-to-integer conversion of NaN

The ARM architecture mandates that converting a NaN value to
integer gives zero (if Invalid Operation FP exceptions are
not being trapped). This isn't the behaviour of the SoftFloat
library, so NaNs must be special-cased....
2d627737 12/07/2010 05:37 pm Peter Maydell

ARM: Return correct result for single<->double conversion of NaN

The ARM ARM defines that if the input to a single<->double conversion
is a NaN then the output is always forced to be a quiet NaN by setting
the most significant bit of the fraction part.

Signed-off-by: Peter Maydell <>...
26a5e69a 12/07/2010 05:37 pm Peter Maydell

ARM: Ignore top 16 bits when doing VCVT from 16 bit fixed point

VCVT of 16 bit fixed point to float should ignore the top 16 bits
of the source register. Cast to int16_t and friends rather than
int16 -- the former is guaranteed exactly 16 bits wide where the...
2af9ab77 12/07/2010 02:01 pm Johan Bengtsson

target-arm: Add support for PKHxx in thumb2

The PKHxx instructions were not recognized by the thumb2 decoder. The
solution provided in this changeset is identical to the arm-mode
implementation.

Signed-off-by: Johan Bengtsson <>
Signed-off-by: Peter Maydell <>...
4809c612 12/07/2010 02:01 pm Johan Bengtsson

target-arm: Fix mixup in decoding of saturating add and sub

The thumb2 decoder contained a mixup between the bit controlling
doubling and the bit controlling if the operation was an add or a sub.

Signed-off-by: Johan Bengtsson <>
Signed-off-by: Peter Maydell <>...
49e14940 12/07/2010 02:01 pm Adam Lackorzynski

target-arm: Handle 'smc' as an undefined instruction

Refine check on bkpt so that smc and undefined instruction encodings are
handled as an undefined instruction and trap.

Signed-off-by: Adam Lackorzynski <>
Signed-off-by: Peter Maydell <>...

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