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1 | 87ecb68b | pbrook | #ifndef QEMU_PCI_H
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2 | 87ecb68b | pbrook | #define QEMU_PCI_H
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3 | 87ecb68b | pbrook | |
4 | 376253ec | aliguori | #include "qemu-common.h" |
5 | 376253ec | aliguori | |
6 | 6b1b92d3 | Paul Brook | #include "qdev.h" |
7 | 6b1b92d3 | Paul Brook | |
8 | 87ecb68b | pbrook | /* PCI includes legacy ISA access. */
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9 | 87ecb68b | pbrook | #include "isa.h" |
10 | 87ecb68b | pbrook | |
11 | 87ecb68b | pbrook | /* PCI bus */
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12 | 87ecb68b | pbrook | |
13 | c227f099 | Anthony Liguori | extern target_phys_addr_t pci_mem_base;
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14 | 87ecb68b | pbrook | |
15 | 3ae80618 | aliguori | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
16 | 3ae80618 | aliguori | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
17 | 3ae80618 | aliguori | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
18 | 3ae80618 | aliguori | |
19 | a770dc7e | aliguori | /* Class, Vendor and Device IDs from Linux's pci_ids.h */
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20 | a770dc7e | aliguori | #include "pci_ids.h" |
21 | 173a543b | blueswir1 | |
22 | a770dc7e | aliguori | /* QEMU-specific Vendor and Device ID definitions */
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23 | 6f338c34 | aliguori | |
24 | a770dc7e | aliguori | /* IBM (0x1014) */
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25 | a770dc7e | aliguori | #define PCI_DEVICE_ID_IBM_440GX 0x027f |
26 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
27 | deb54399 | aliguori | |
28 | a770dc7e | aliguori | /* Hitachi (0x1054) */
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29 | deb54399 | aliguori | #define PCI_VENDOR_ID_HITACHI 0x1054 |
30 | a770dc7e | aliguori | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
31 | deb54399 | aliguori | |
32 | a770dc7e | aliguori | /* Apple (0x106b) */
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33 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
34 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e |
35 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f |
36 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
37 | a770dc7e | aliguori | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
38 | deb54399 | aliguori | |
39 | a770dc7e | aliguori | /* Realtek (0x10ec) */
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40 | a770dc7e | aliguori | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 |
41 | deb54399 | aliguori | |
42 | a770dc7e | aliguori | /* Xilinx (0x10ee) */
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43 | a770dc7e | aliguori | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 |
44 | deb54399 | aliguori | |
45 | a770dc7e | aliguori | /* Marvell (0x11ab) */
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46 | a770dc7e | aliguori | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 |
47 | deb54399 | aliguori | |
48 | a770dc7e | aliguori | /* QEMU/Bochs VGA (0x1234) */
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49 | 4ebcf884 | blueswir1 | #define PCI_VENDOR_ID_QEMU 0x1234 |
50 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 |
51 | 4ebcf884 | blueswir1 | |
52 | a770dc7e | aliguori | /* VMWare (0x15ad) */
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53 | deb54399 | aliguori | #define PCI_VENDOR_ID_VMWARE 0x15ad |
54 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
55 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
56 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
57 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
58 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
59 | deb54399 | aliguori | |
60 | cef3017c | aliguori | /* Intel (0x8086) */
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61 | a770dc7e | aliguori | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
62 | d6fd1e66 | Stefan Weil | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
63 | 74c62ba8 | aurel32 | |
64 | deb54399 | aliguori | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
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65 | d350d97d | aliguori | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
66 | d350d97d | aliguori | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 |
67 | d350d97d | aliguori | #define PCI_SUBDEVICE_ID_QEMU 0x1100 |
68 | d350d97d | aliguori | |
69 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 |
70 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 |
71 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 |
72 | 14d50bef | aliguori | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
73 | d350d97d | aliguori | |
74 | 87ecb68b | pbrook | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
75 | 87ecb68b | pbrook | uint32_t address, uint32_t data, int len);
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76 | 87ecb68b | pbrook | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
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77 | 87ecb68b | pbrook | uint32_t address, int len);
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78 | 87ecb68b | pbrook | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
79 | 87ecb68b | pbrook | uint32_t addr, uint32_t size, int type);
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80 | 5851e08c | aliguori | typedef int PCIUnregisterFunc(PCIDevice *pci_dev); |
81 | 87ecb68b | pbrook | |
82 | 87ecb68b | pbrook | #define PCI_ADDRESS_SPACE_MEM 0x00 |
83 | 87ecb68b | pbrook | #define PCI_ADDRESS_SPACE_IO 0x01 |
84 | 87ecb68b | pbrook | #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 |
85 | 87ecb68b | pbrook | |
86 | 87ecb68b | pbrook | typedef struct PCIIORegion { |
87 | 87ecb68b | pbrook | uint32_t addr; /* current PCI mapping address. -1 means not mapped */
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88 | 87ecb68b | pbrook | uint32_t size; |
89 | 87ecb68b | pbrook | uint8_t type; |
90 | 87ecb68b | pbrook | PCIMapIORegionFunc *map_func; |
91 | 87ecb68b | pbrook | } PCIIORegion; |
92 | 87ecb68b | pbrook | |
93 | 87ecb68b | pbrook | #define PCI_ROM_SLOT 6 |
94 | 87ecb68b | pbrook | #define PCI_NUM_REGIONS 7 |
95 | 87ecb68b | pbrook | |
96 | cef3017c | aliguori | /* Declarations from linux/pci_regs.h */
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97 | 87ecb68b | pbrook | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
98 | 87ecb68b | pbrook | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
99 | 87ecb68b | pbrook | #define PCI_COMMAND 0x04 /* 16 bits */ |
100 | 87ecb68b | pbrook | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
101 | 87ecb68b | pbrook | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
102 | b7ee1603 | Michael S. Tsirkin | #define PCI_COMMAND_MASTER 0x4 /* Enable bus master */ |
103 | cef3017c | aliguori | #define PCI_STATUS 0x06 /* 16 bits */ |
104 | cef3017c | aliguori | #define PCI_REVISION_ID 0x08 /* 8 bits */ |
105 | bd4b65ee | Michael S. Tsirkin | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
106 | 87ecb68b | pbrook | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
107 | b7ee1603 | Michael S. Tsirkin | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
108 | b7ee1603 | Michael S. Tsirkin | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
109 | cef3017c | aliguori | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
110 | 6407f373 | Isaku Yamahata | #define PCI_HEADER_TYPE_NORMAL 0 |
111 | 6407f373 | Isaku Yamahata | #define PCI_HEADER_TYPE_BRIDGE 1 |
112 | 6407f373 | Isaku Yamahata | #define PCI_HEADER_TYPE_CARDBUS 2 |
113 | 6407f373 | Isaku Yamahata | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
114 | b7ee1603 | Michael S. Tsirkin | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
115 | b7ee1603 | Michael S. Tsirkin | #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ |
116 | b7ee1603 | Michael S. Tsirkin | #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ |
117 | b7ee1603 | Michael S. Tsirkin | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ |
118 | cef3017c | aliguori | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */ |
119 | cef3017c | aliguori | #define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */ |
120 | 5330de09 | Michael S. Tsirkin | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
121 | 5330de09 | Michael S. Tsirkin | #define PCI_ROM_ADDRESS_ENABLE 0x01 |
122 | b7ee1603 | Michael S. Tsirkin | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
123 | 87ecb68b | pbrook | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
124 | 87ecb68b | pbrook | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
125 | 87ecb68b | pbrook | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
126 | 87ecb68b | pbrook | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
127 | 87ecb68b | pbrook | |
128 | 6f4cbd39 | Michael S. Tsirkin | /* Capability lists */
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129 | 6f4cbd39 | Michael S. Tsirkin | #define PCI_CAP_LIST_ID 0 /* Capability ID */ |
130 | 6f4cbd39 | Michael S. Tsirkin | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
131 | 6f4cbd39 | Michael S. Tsirkin | |
132 | cef3017c | aliguori | #define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */ |
133 | cef3017c | aliguori | #define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */ |
134 | cef3017c | aliguori | #define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */ |
135 | cef3017c | aliguori | |
136 | 8098ed41 | aurel32 | /* Bits in the PCI Status Register (PCI 2.3 spec) */
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137 | 8098ed41 | aurel32 | #define PCI_STATUS_RESERVED1 0x007 |
138 | 8098ed41 | aurel32 | #define PCI_STATUS_INT_STATUS 0x008 |
139 | 6f4cbd39 | Michael S. Tsirkin | #define PCI_STATUS_CAP_LIST 0x010 |
140 | 8098ed41 | aurel32 | #define PCI_STATUS_66MHZ 0x020 |
141 | 8098ed41 | aurel32 | #define PCI_STATUS_RESERVED2 0x040 |
142 | 8098ed41 | aurel32 | #define PCI_STATUS_FAST_BACK 0x080 |
143 | 8098ed41 | aurel32 | #define PCI_STATUS_DEVSEL 0x600 |
144 | 8098ed41 | aurel32 | |
145 | 8098ed41 | aurel32 | #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
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146 | 8098ed41 | aurel32 | PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \ |
147 | 8098ed41 | aurel32 | PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK) |
148 | 8098ed41 | aurel32 | |
149 | 8098ed41 | aurel32 | #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8) |
150 | 8098ed41 | aurel32 | |
151 | 475dc65f | aurel32 | /* Bits in the PCI Command Register (PCI 2.3 spec) */
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152 | 475dc65f | aurel32 | #define PCI_COMMAND_RESERVED 0xf800 |
153 | 475dc65f | aurel32 | |
154 | 475dc65f | aurel32 | #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8) |
155 | 475dc65f | aurel32 | |
156 | b7ee1603 | Michael S. Tsirkin | /* Size of the standard PCI config header */
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157 | b7ee1603 | Michael S. Tsirkin | #define PCI_CONFIG_HEADER_SIZE 0x40 |
158 | b7ee1603 | Michael S. Tsirkin | /* Size of the standard PCI config space */
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159 | b7ee1603 | Michael S. Tsirkin | #define PCI_CONFIG_SPACE_SIZE 0x100 |
160 | b7ee1603 | Michael S. Tsirkin | |
161 | 02eb84d0 | Michael S. Tsirkin | /* Bits in cap_present field. */
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162 | 02eb84d0 | Michael S. Tsirkin | enum {
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163 | 02eb84d0 | Michael S. Tsirkin | QEMU_PCI_CAP_MSIX = 0x1,
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164 | 02eb84d0 | Michael S. Tsirkin | }; |
165 | 02eb84d0 | Michael S. Tsirkin | |
166 | 87ecb68b | pbrook | struct PCIDevice {
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167 | 6b1b92d3 | Paul Brook | DeviceState qdev; |
168 | 87ecb68b | pbrook | /* PCI config space */
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169 | b7ee1603 | Michael S. Tsirkin | uint8_t config[PCI_CONFIG_SPACE_SIZE]; |
170 | b7ee1603 | Michael S. Tsirkin | |
171 | bd4b65ee | Michael S. Tsirkin | /* Used to enable config checks on load. Note that writeable bits are
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172 | bd4b65ee | Michael S. Tsirkin | * never checked even if set in cmask. */
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173 | bd4b65ee | Michael S. Tsirkin | uint8_t cmask[PCI_CONFIG_SPACE_SIZE]; |
174 | bd4b65ee | Michael S. Tsirkin | |
175 | b7ee1603 | Michael S. Tsirkin | /* Used to implement R/W bytes */
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176 | b7ee1603 | Michael S. Tsirkin | uint8_t wmask[PCI_CONFIG_SPACE_SIZE]; |
177 | 87ecb68b | pbrook | |
178 | 6f4cbd39 | Michael S. Tsirkin | /* Used to allocate config space for capabilities. */
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179 | 6f4cbd39 | Michael S. Tsirkin | uint8_t used[PCI_CONFIG_SPACE_SIZE]; |
180 | 6f4cbd39 | Michael S. Tsirkin | |
181 | 87ecb68b | pbrook | /* the following fields are read only */
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182 | 87ecb68b | pbrook | PCIBus *bus; |
183 | 54586bd1 | Gerd Hoffmann | uint32_t devfn; |
184 | 87ecb68b | pbrook | char name[64]; |
185 | 87ecb68b | pbrook | PCIIORegion io_regions[PCI_NUM_REGIONS]; |
186 | 87ecb68b | pbrook | |
187 | 87ecb68b | pbrook | /* do not access the following fields */
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188 | 87ecb68b | pbrook | PCIConfigReadFunc *config_read; |
189 | 87ecb68b | pbrook | PCIConfigWriteFunc *config_write; |
190 | 87ecb68b | pbrook | |
191 | 87ecb68b | pbrook | /* IRQ objects for the INTA-INTD pins. */
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192 | 87ecb68b | pbrook | qemu_irq *irq; |
193 | 87ecb68b | pbrook | |
194 | 87ecb68b | pbrook | /* Current IRQ levels. Used internally by the generic PCI code. */
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195 | 87ecb68b | pbrook | int irq_state[4]; |
196 | 02eb84d0 | Michael S. Tsirkin | |
197 | 02eb84d0 | Michael S. Tsirkin | /* Capability bits */
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198 | 02eb84d0 | Michael S. Tsirkin | uint32_t cap_present; |
199 | 02eb84d0 | Michael S. Tsirkin | |
200 | 02eb84d0 | Michael S. Tsirkin | /* Offset of MSI-X capability in config space */
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201 | 02eb84d0 | Michael S. Tsirkin | uint8_t msix_cap; |
202 | 02eb84d0 | Michael S. Tsirkin | |
203 | 02eb84d0 | Michael S. Tsirkin | /* MSI-X entries */
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204 | 02eb84d0 | Michael S. Tsirkin | int msix_entries_nr;
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205 | 02eb84d0 | Michael S. Tsirkin | |
206 | 02eb84d0 | Michael S. Tsirkin | /* Space to store MSIX table */
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207 | 02eb84d0 | Michael S. Tsirkin | uint8_t *msix_table_page; |
208 | 02eb84d0 | Michael S. Tsirkin | /* MMIO index used to map MSIX table and pending bit entries. */
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209 | 02eb84d0 | Michael S. Tsirkin | int msix_mmio_index;
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210 | 02eb84d0 | Michael S. Tsirkin | /* Reference-count for entries actually in use by driver. */
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211 | 02eb84d0 | Michael S. Tsirkin | unsigned *msix_entry_used;
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212 | 02eb84d0 | Michael S. Tsirkin | /* Region including the MSI-X table */
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213 | 02eb84d0 | Michael S. Tsirkin | uint32_t msix_bar_size; |
214 | f16c4abf | Juan Quintela | /* Version id needed for VMState */
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215 | f16c4abf | Juan Quintela | int32_t version_id; |
216 | 87ecb68b | pbrook | }; |
217 | 87ecb68b | pbrook | |
218 | 87ecb68b | pbrook | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
219 | 87ecb68b | pbrook | int instance_size, int devfn, |
220 | 87ecb68b | pbrook | PCIConfigReadFunc *config_read, |
221 | 87ecb68b | pbrook | PCIConfigWriteFunc *config_write); |
222 | 87ecb68b | pbrook | |
223 | 28c2c264 | Avi Kivity | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
224 | 87ecb68b | pbrook | uint32_t size, int type,
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225 | 87ecb68b | pbrook | PCIMapIORegionFunc *map_func); |
226 | 87ecb68b | pbrook | |
227 | 6f4cbd39 | Michael S. Tsirkin | int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
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228 | 6f4cbd39 | Michael S. Tsirkin | |
229 | 6f4cbd39 | Michael S. Tsirkin | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
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230 | 6f4cbd39 | Michael S. Tsirkin | |
231 | 6f4cbd39 | Michael S. Tsirkin | void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
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232 | 6f4cbd39 | Michael S. Tsirkin | |
233 | 6f4cbd39 | Michael S. Tsirkin | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
234 | 6f4cbd39 | Michael S. Tsirkin | |
235 | 6f4cbd39 | Michael S. Tsirkin | |
236 | 87ecb68b | pbrook | uint32_t pci_default_read_config(PCIDevice *d, |
237 | 87ecb68b | pbrook | uint32_t address, int len);
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238 | 87ecb68b | pbrook | void pci_default_write_config(PCIDevice *d,
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239 | 87ecb68b | pbrook | uint32_t address, uint32_t val, int len);
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240 | 87ecb68b | pbrook | void pci_device_save(PCIDevice *s, QEMUFile *f);
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241 | 87ecb68b | pbrook | int pci_device_load(PCIDevice *s, QEMUFile *f);
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242 | 87ecb68b | pbrook | |
243 | 5d4e84c8 | Juan Quintela | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
244 | 87ecb68b | pbrook | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
245 | ee995ffb | Gerd Hoffmann | typedef int (*pci_hotplug_fn)(PCIDevice *pci_dev, int state); |
246 | 21eea4b3 | Gerd Hoffmann | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
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247 | 21eea4b3 | Gerd Hoffmann | const char *name, int devfn_min); |
248 | 21eea4b3 | Gerd Hoffmann | PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min); |
249 | 21eea4b3 | Gerd Hoffmann | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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250 | 21eea4b3 | Gerd Hoffmann | void *irq_opaque, int nirq); |
251 | ee995ffb | Gerd Hoffmann | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug);
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252 | 02e2da45 | Paul Brook | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
253 | 02e2da45 | Paul Brook | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
254 | 5d4e84c8 | Juan Quintela | void *irq_opaque, int devfn_min, int nirq); |
255 | 87ecb68b | pbrook | |
256 | 5607c388 | Markus Armbruster | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
257 | 5607c388 | Markus Armbruster | const char *default_devaddr); |
258 | 07caea31 | Markus Armbruster | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
259 | 07caea31 | Markus Armbruster | const char *default_devaddr); |
260 | 87ecb68b | pbrook | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len); |
261 | 87ecb68b | pbrook | uint32_t pci_data_read(void *opaque, uint32_t addr, int len); |
262 | 87ecb68b | pbrook | int pci_bus_num(PCIBus *s);
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263 | 87ecb68b | pbrook | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)); |
264 | 3ae80618 | aliguori | PCIBus *pci_find_bus(int bus_num);
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265 | 3ae80618 | aliguori | PCIDevice *pci_find_device(int bus_num, int slot, int function); |
266 | 49bd1458 | Markus Armbruster | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); |
267 | 87ecb68b | pbrook | |
268 | e9283f8b | Jan Kiszka | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
269 | e9283f8b | Jan Kiszka | unsigned *slotp);
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270 | 880345c4 | aliguori | |
271 | 376253ec | aliguori | void pci_info(Monitor *mon);
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272 | 480b9f24 | blueswir1 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
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273 | 87ecb68b | pbrook | pci_map_irq_fn map_irq, const char *name); |
274 | 87ecb68b | pbrook | |
275 | deb54399 | aliguori | static inline void |
276 | 64d50b8b | Michael S. Tsirkin | pci_set_byte(uint8_t *config, uint8_t val) |
277 | 64d50b8b | Michael S. Tsirkin | { |
278 | 64d50b8b | Michael S. Tsirkin | *config = val; |
279 | 64d50b8b | Michael S. Tsirkin | } |
280 | 64d50b8b | Michael S. Tsirkin | |
281 | 64d50b8b | Michael S. Tsirkin | static inline uint8_t |
282 | 64d50b8b | Michael S. Tsirkin | pci_get_byte(uint8_t *config) |
283 | 64d50b8b | Michael S. Tsirkin | { |
284 | 64d50b8b | Michael S. Tsirkin | return *config;
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285 | 64d50b8b | Michael S. Tsirkin | } |
286 | 64d50b8b | Michael S. Tsirkin | |
287 | 64d50b8b | Michael S. Tsirkin | static inline void |
288 | 14e12559 | Michael S. Tsirkin | pci_set_word(uint8_t *config, uint16_t val) |
289 | 14e12559 | Michael S. Tsirkin | { |
290 | 14e12559 | Michael S. Tsirkin | cpu_to_le16wu((uint16_t *)config, val); |
291 | 14e12559 | Michael S. Tsirkin | } |
292 | 14e12559 | Michael S. Tsirkin | |
293 | 14e12559 | Michael S. Tsirkin | static inline uint16_t |
294 | 14e12559 | Michael S. Tsirkin | pci_get_word(uint8_t *config) |
295 | 14e12559 | Michael S. Tsirkin | { |
296 | 14e12559 | Michael S. Tsirkin | return le16_to_cpupu((uint16_t *)config);
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297 | 14e12559 | Michael S. Tsirkin | } |
298 | 14e12559 | Michael S. Tsirkin | |
299 | 14e12559 | Michael S. Tsirkin | static inline void |
300 | 14e12559 | Michael S. Tsirkin | pci_set_long(uint8_t *config, uint32_t val) |
301 | 14e12559 | Michael S. Tsirkin | { |
302 | 14e12559 | Michael S. Tsirkin | cpu_to_le32wu((uint32_t *)config, val); |
303 | 14e12559 | Michael S. Tsirkin | } |
304 | 14e12559 | Michael S. Tsirkin | |
305 | 14e12559 | Michael S. Tsirkin | static inline uint32_t |
306 | 14e12559 | Michael S. Tsirkin | pci_get_long(uint8_t *config) |
307 | 14e12559 | Michael S. Tsirkin | { |
308 | 14e12559 | Michael S. Tsirkin | return le32_to_cpupu((uint32_t *)config);
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309 | 14e12559 | Michael S. Tsirkin | } |
310 | 14e12559 | Michael S. Tsirkin | |
311 | 14e12559 | Michael S. Tsirkin | static inline void |
312 | deb54399 | aliguori | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) |
313 | deb54399 | aliguori | { |
314 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
315 | deb54399 | aliguori | } |
316 | deb54399 | aliguori | |
317 | deb54399 | aliguori | static inline void |
318 | deb54399 | aliguori | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) |
319 | deb54399 | aliguori | { |
320 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
321 | deb54399 | aliguori | } |
322 | deb54399 | aliguori | |
323 | 173a543b | blueswir1 | static inline void |
324 | 173a543b | blueswir1 | pci_config_set_class(uint8_t *pci_config, uint16_t val) |
325 | 173a543b | blueswir1 | { |
326 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
327 | 173a543b | blueswir1 | } |
328 | 173a543b | blueswir1 | |
329 | 81a322d4 | Gerd Hoffmann | typedef int (*pci_qdev_initfn)(PCIDevice *dev); |
330 | 0aab0d3a | Gerd Hoffmann | typedef struct { |
331 | 0aab0d3a | Gerd Hoffmann | DeviceInfo qdev; |
332 | 0aab0d3a | Gerd Hoffmann | pci_qdev_initfn init; |
333 | e3936fa5 | Gerd Hoffmann | PCIUnregisterFunc *exit; |
334 | 0aab0d3a | Gerd Hoffmann | PCIConfigReadFunc *config_read; |
335 | 0aab0d3a | Gerd Hoffmann | PCIConfigWriteFunc *config_write; |
336 | 0aab0d3a | Gerd Hoffmann | } PCIDeviceInfo; |
337 | 0aab0d3a | Gerd Hoffmann | |
338 | 0aab0d3a | Gerd Hoffmann | void pci_qdev_register(PCIDeviceInfo *info);
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339 | 0aab0d3a | Gerd Hoffmann | void pci_qdev_register_many(PCIDeviceInfo *info);
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340 | 6b1b92d3 | Paul Brook | |
341 | 499cf102 | Markus Armbruster | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
342 | 6b1b92d3 | Paul Brook | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
343 | 6b1b92d3 | Paul Brook | |
344 | 87ecb68b | pbrook | /* lsi53c895a.c */
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345 | e4bcb14c | ths | #define LSI_MAX_DEVS 7 |
346 | 87ecb68b | pbrook | |
347 | 87ecb68b | pbrook | /* vmware_vga.c */
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348 | fbe1b595 | Paul Brook | void pci_vmsvga_init(PCIBus *bus);
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349 | 87ecb68b | pbrook | |
350 | 87ecb68b | pbrook | /* usb-uhci.c */
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351 | 87ecb68b | pbrook | void usb_uhci_piix3_init(PCIBus *bus, int devfn); |
352 | 87ecb68b | pbrook | void usb_uhci_piix4_init(PCIBus *bus, int devfn); |
353 | 87ecb68b | pbrook | |
354 | 87ecb68b | pbrook | /* usb-ohci.c */
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355 | 5b19d9a2 | Gerd Hoffmann | void usb_ohci_init_pci(struct PCIBus *bus, int devfn); |
356 | 87ecb68b | pbrook | |
357 | 87ecb68b | pbrook | /* prep_pci.c */
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358 | 87ecb68b | pbrook | PCIBus *pci_prep_init(qemu_irq *pic); |
359 | 87ecb68b | pbrook | |
360 | 87ecb68b | pbrook | /* apb_pci.c */
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361 | c227f099 | Anthony Liguori | PCIBus *pci_apb_init(target_phys_addr_t special_base, |
362 | c227f099 | Anthony Liguori | target_phys_addr_t mem_base, |
363 | c190ea07 | blueswir1 | qemu_irq *pic, PCIBus **bus2, PCIBus **bus3); |
364 | 87ecb68b | pbrook | |
365 | b79e1752 | aurel32 | /* sh_pci.c */
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366 | b79e1752 | aurel32 | PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
367 | 5d4e84c8 | Juan Quintela | void *pic, int devfn_min, int nirq); |
368 | b79e1752 | aurel32 | |
369 | 87ecb68b | pbrook | #endif |