cpu: Change qemu_init_vcpu() argument to CPUState
This allows to move the call into CPUState's realizefn.Therefore move the stub into libqemustub.a.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_unassigned_access() into a CPUState hook
Use it for all targets, but be careful not to pass invalid CPUState.cpu_single_env can be NULL, e.g. on Xen.
Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
target-mips: clean-up in BIT_INSV
This is a small follow-up change to "fix incorrect behaviour for INSV".
It includes two minor modifications:
- sizefilter is constant so it can be moved inside of the block,- several lines of the code are replaced with a call to deposit64....
linux-user: Save the correct resume address for MIPS signal handling
The current ISA mode needs to be saved in bit 0 of the resume address.If the current instruction happens to be in a branch delay slot, thenthe address of the preceding jump instruction should be stored instead....
target-mips: set carry bit correctly in DSPControl register
First we need to clear the bit and then we set the given value.Instruction ADDSC sets the bit and instruction ADDWC uses this bit.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: fix EXTPDP and setting up pos field in the DSPControl reg
This change makes sure that modifications of pos field in the DSPControlregister do not trash other bits in the register. This bug can be triggeredwith the additional test case in mips32-dsp/extpdp.c in this commit....
target-mips: fix incorrect behaviour for EXTP
The mask for EXTP instruction when size=31 has not been correctlycalculated.
The test (mips32-dsp/extp.c) has been extended to include the case thattriggers the issue.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>...
target-mips: fix incorrect behaviour for INSV
Corner case for INSV instruction when size=32 has not been correctlyimplemented. The mask for size should be one bit wider, and preparing thefilter variable should be aware of this case too.
The test for INSV has been extended to include the case that triggers the...
target-mips: add missing check_dspr2 for multiply instructions
The emulator needs to check in hflags if DSP unit has been turned off beforeit generates code for MUL_PH, MUL_S_PH, MULQ_S_W, and MULQ_RS_W.
target-mips: fix calculation of overflow for SHLL.PH and SHLL.QB
This change corrects and simplifies how discard is calculated for shiftleft logical vector instructions. It is used to detect overflow and set bit22 in the DSPControl register.
The existing tests (shll_ph.c, shll_qb.c) are extended with the corner cases...
target-mips: fix mipsdsp_mul_q15_q15 and tests for MAQ_SA_W_PHL/PHR
The operands for MAQ_SA_W.PHL/MAQ_SA_W.PHR must in specified format.Otherwise, the results are unpredictable. Once the operands were correctedin the tests (part of this change), a bug in mipsdsp_mul_q15_q15 became...
target-mips: fix rndrashift_short_acc and code for EXTR_ instructions
Fix for rndrashift_short_acc to set correct value to higher 64 bits.This change also corrects conditions when bit 23 of the DSPControl registeris set.
The existing test files have been extended with several examples that...
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
exec: Pass CPUState to cpu_reset_interrupt()
Move it to qom/cpu.c to avoid build failures depending on include orderof cpu-qom.h and exec/cpu-all.h.
Change opaques of various ..._irq_handler() functions to theappropriate CPU type to facilitate using cpu_reset_interrupt()....
cpu: Pass CPUState to cpu_interrupt()
Move it to qom/cpu.h to avoid issues with include order.
Change pc_acpi_smi_interrupt() opaque to X86CPU.
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
mips-linux-user: Save and restore fpu and dsp from sigcontext
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
mips64-linux-user: Enable 64-bit address mode and fpu
target-mips: Fix accumulator selection for MIPS16 and microMIPS
Add accumulator arguments to gen_HILO and gen_muldiv, rather thanextracting the accumulator directly from ctx->opcode. The extractionwas only right for the standard encoding: MIPS16 doesn't have access...
target-mips: fix DSP overflow macro and affected routines
The previous implementation incorrectly used same macro to detect overflowfor addition and subtraction. This patch makes distinction between thesetwo, and creates separate macros. The affected routines are changed...
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
cpu: Introduce ENV_OFFSET macros
Introduce ENV_OFFSET macros which can be used in non-target-specificcode that needs to generate TCG instructions which reference CPUStatefields given the cpu_env register that TCG targets set up with apointer to the CPUArchState struct....
target-mips: fix for sign-issue in MULQ_W helper
Correct sign-propagation before multiplication in MULQ_W helper.The change also fixes previously incorrect expected values in thetests for MULQ_RS.W and MULQ_S.W.
Signed-off-by: Petar Jovanovic <petarj@mips.com>...
target-mips: fix for incorrect multiplication with MULQ_S.PH
The change corrects sign-related issue with MULQ_S.PH. It also includesextension to the already existing test which will trigger the issue.
Signed-off-by: Petar Jovanovic <petarj@mips.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Use mul[us]2 in [D]MULT[U] insns
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu: Add CPUArchState pointer to CPUState
The target-specific ENV_GET_CPU() macros have allowed us to navigatefrom CPUArchState to CPUState. The reverse direction was not supported.Avoid introducing CPU_GET_ENV() macros by initializing an untypedpointer that is initialized in derived instance_init functions....
target-mips: Move TCG initialization to MIPSCPU initfn
Make mips_tcg_init() non-static and add tcg_enabled() check to suppressit for qtest.
target-mips: Introduce QOM realizefn for MIPSCPU
Introduce a realizefn and set realized = true from cpu_mips_init().
target-mips: enable access to DSP ASE if implemented
compute_hflags() will reset DSP h-flags, so MX bit should be initially setfor usermode in cpu_state_reset() if DSP ASE is implemented.This change will bring back user-mode support for DSP ASE, since one of the...
target-mips: Unfuse {,N}M{ADD,SUB}.fmt
Turn MADD.fmt, MSUB.fmt, NMADD.fmt and NMSUB.fmt from fused to unfusedoperations, so that they behave in the same way as a separate multiplicationand addition. The instructions were only fused in early MIPS IV processors....
target-mips: Sign-extend the result of LWR
Sign-extend the result of LWR, as is already done for LWL. This is necessaryin the case where LWR loads the full word (i.e. the address is actuallyaligned). In the other cases, it is implementation defined whether the...
target-mips: Fix signedness of loads in MIPS16 RESTOREs
Make RESTORE use sign-extending rather than zero-extending loads.
Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: implement DSP (d)append sub-class with TCG
DSP instruction from the (d)append sub-class can be implemented withTCG. Use a different function for these instructions are they are quitedifferent from compare-pick sub-class.
Fix BALIGN instruction for negative value, where the value should be...
target-mips: use DSP unions for reduction add instructions
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: use DSP unions for unary DSP operators
This allow to reduce the number of macros.
target-mips: use DSP unions for binary DSP operators
target-mips: add unions to access DSP elements
Instead of playing with bit shifting, add two unions (one for 32-bitvalues, one for 64-bit ones) to access all the DSP elements with thecorrect type.
This make the code easier to read and less error prone, and allow GCC...
target-mips: generate a reserved instruction exception on CPU without DSP
On CPU without DSP ASE support, a reserved instruction exception (instead ofa DSP ASE sate disabled) should be generated.
target-mips: copy insn_flags in DisasContext
Copy insn_flags in DisasContext to avoid passing a CPUMIPSState pointerto subroutines, as suggested by Richard Henderson. Change subroutines touse this new field and remove the first argument.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-mips: fix DSP loads with rd = 0
When rd is 0, which still need to do the actually load to possiblygenerate a TLB exception.
Reviewed-by: Eric Johnson <ericj@mips.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
exec: Return CPUState from qemu_get_cpu()
Move the declaration to qemu/cpu.h and add documentation.The implementation still depends on CPUArchState for CPU iteration.
cpu: Move nr_{cores,threads} fields to CPUState
To facilitate the field movements, pass MIPSCPU to malta_mips_config();avoid that for mips_cpu_map_tc() since callers only access MIPS ThreadContexts, inside TCG helpers.
target-mips: Clean up mips_cpu_map_tc() documentation
This function will be touched again soon, so a good understanding of envvs. other helps. Adopt gtk-doc style.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Eric Johnson <ericj@mips.com>
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using anegative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset()....
target-mips: Fix helper and tests for dot/cross-dot product instructions
Helper function for dpa_w_ph, dpax_w_ph, dps_w_ph and dpsx_w_ph incorrectlydefines halfword vector elements as unsigned values. This results in wrongoutput which is not triggered in the tests as they also follow this logic....
target-mips: Replace macros by inline functions
The macros RESTORE_ROUNDING_MODE and RESTORE_FLUSH_MODE silently usedvariable env from their callers. Using inline functions with env passedas a function argument is more transparent.
This modification was proposed by Peter Maydell....
target-mips: Allow DSP access to be disabled once enabled.
Clear the DSP hflags at the start of compute_hflags. Otherwise accessis not properly disabled once enabled.
Signed-off-by: Eric Johnson <ericj@mips.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Use EXCP_SC rather than a magic number
From the discussion on the ML [1], the exception limit defined bymagic number 0x100 is actually EXCP_SC defined in cpu.h. Replace themagic number with EXCP_SC. Remove "#if 1 .. #endif" as well.
[1] http://lists.gnu.org/archive/html/qemu-devel/2012-11/msg03080.html...
target-mips: Make repl_ph to sign extend to target-long
The immediate value is 9bits, should sign-extend to 16bits. The return value toregister should sign-extend to target_long, as Richard says, removing anunnecessary cast works fun.
Signed-off-by: Dongxue Zhang <elta.era@gmail.com>...
Fix my email address
Fix my email address, last time it's wrong.
Signed-off-by: Dongxue Zhang <elta.era@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Remove semicolon from macro definition
Macro RESTORE_FLUSH_MODE is similar to RESTORE_ROUNDING_MODEbut included a semicolon.
The code which uses that macro also includes a semicolon,so the result was an empty statement.
Remove the superfluous semicolon from the macro definition....
target-mips: Fix for helpers for EXTR_* instructions
The change removes some unnecessary and incorrect code for EXTR_S.H.Further, it corrects the mask for shift value in the EXTR_ instructions. It alsoextends the existing tests so they trigger the issues corrected with the change....
target-mips: Fix incorrect reads and writes to DSPControl register
Upper 4 bits of ccond (bits 31..28 ) of DSPControl register are not used inthe MIPS32 architecture. They are used in the MIPS64 architecture. For MIPS32these bits must be written as zero, and return zero on read....
fpu: move public header file to include/fpu
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
misc: move include files to include/qemu/
qom: move include files to include/qom/
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Merge branch 'master' of git.qemu-project.org:/pub/git/qemu
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
target-mips: Fix incorrect shift for SHILO and SHILOV
helper_shilo has not been shifting an accumulator value correctly for negativevalues in 'shift' field. Minor optimization for shift=0 case.This change also adds tests that will trigger issue and check for regressions....
target-mips: Fix incorrect code and test for INSV
Content of register rs should be shifted for pos before applying a mask.This change contains both fix for the instruction and to the existing test.
Signed-off-by: Petar Jovanovic <petarj@mips.com>Reviewed-by: Eric Johnson <ericj@mips.com>...
target-mips: remove POOL48A from the microMIPS decoding
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Add comments on POOL32Axf encoding
Current QEMU MIPS POOL32AXF encoding comes from microMIPS32and microMIPS32 DSP. Add comment here to help reading.
Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw>Reviewed-by: Eric Johnson <ericj@mips.com>...
target-mips: Clean up microMIPS32 major opcode
I check MIPS microMIPS manual [1], and found the major opcode mightbe wrong. I add a comment to explicitly indicate what manual I am referingto, and according that manual I remove microMIPS32 major opcodes 0x1f....
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
target-mips: fix wrong microMIPS opcode encoding
While reading microMIPS decoding, I found a possible wrong opcodeencoding. According to [1] page 166, the bits 13..12 for MULTU is0x01 rather than 0x00. Please review, thanks.
[1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP...
target-mips: Fix seg fault for LUI when MIPS_DEBUG_DISAS==1.
The call to gen_logic_imm for OPC_LUI passes -1 for rs. Thiscauses the MIPS_DEBUG statement to seg fault due to the deferenceof regnames[rs]. This patch fixes that.
Signed-off-by: Eric Johnson <ericj@mips.com>...
disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
target-mips: use ULL for 64 bit constants
Fix build on a 32 bit host: CC mips-softmmu/target-mips/dsp_helper.o/src/qemu/target-mips/dsp_helper.c: In function 'helper_dextr_rs_w':/src/qemu/target-mips/dsp_helper.c:3556: error: integer constant is too large for 'long' type...
Merge remote-tracking branch 'afaerber/qom-cpu' into staging
target-mips: fix TLBR wrt SEGMask
Like r4k_map_address(), r4k_helper_tlbp() should use SEGMask to mask theaddress.
target-mips: don't flush extra TLB on permissions upgrade
If the guest uses a TLBWI instruction for upgrading permissions, wedon't need to flush the extra TLBs. This improve boot time performanceby about 10%.
target-mips: don't use local temps for store conditional
Store conditional operations only need local temps in user mode. Fixthe code to use temp local only in user mode, this spares two memorystores in system mode.
At the same time remove a wrong a wrong copied & pasted comment,...
target-mips: implement movn/movz using movcond
Avoid the branches in movn/movz implementation and replace them withmovcond. Also update a wrong command.
target-mips: optimize ddiv/ddivu/div/divu with movcond
The result of a division by 0, or a division of INT_MIN by -1 in thesigned case, is unpredictable. Just replace 0 by 1 in that case so thatit doesn't trigger a floating point exception on the host....
target-mips: use deposit instead of hardcoded version
Use the deposit op instead of and hardcoded bit field insertion. Itallows the host to emit the corresponding instruction if available.
At the same time remove the (lsb > msb) test. The MIPS64R2 instruction...
target-mips: cleanup load/store operations
Load/store operations use macros for historical reasons. Now that thereis no point in keeping them, replace them by direct calls to qemu_ld/st.
target-mips: optimize load operations
Only allocate t1 when needed.
target-mips: simplify load/store microMIPS helpers
load/store microMIPS helpers are reinventing the wheel. Call do_lw,do_ll, do_sw and do_sl instead of using a macro calling the cpu_*load/store functions.
target-mips: implement unaligned loads using TCG
Load/store from helpers should be avoided as they are quiteinefficient. Rewrite unaligned loads instructions using TCG andaligned loads. The number of actual loads operations to implementan unaligned load instruction is reduced from up to 8 to 1....
target-mips: keep softfloat exception set to 0 between instructions
Instead of clearing the softfloat exception flags before each floatingpoint instruction, reset them to 0 in update_fcr31() when an exceptionis detected.
target-mips: fix FPU exceptions
For each FPU instruction that can trigger an FPU exception, to callcall update_fcr31() after.
Remove the manual NaN assignment in case of float to float operation, assoftfloat is already taking care of that. However for float to int...
target-mips: cleanup float to int conversion helpers
Instead of accessing the flags from the floating point controlregister after updating it, read the softfloat flags.
This is just code cleanup and should not change the behaviour.
target-mips: use softfloat constants when possible
softfloat already has a few constants defined, use them instead ofredefining them in target-mips.
Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW andFP_TO_INT64_OVERFLOW as even if they have the same value, they are...
target-mips: restore CPU state after an FPU exception
Rework raise_exception() functions so that they can be called fromother helpers, passing the return address as an argument.
Use do_raise_exception() function in update_fcr31() to correctly restore...
target-mips: correctly restore btarget upon exception
When the CPU state is restored through retranslation after an exception,btarget should also be restored.
target-mips: do not save CPU state when using retranslation
When the CPU state after a possible retranslation is going to be handledthrough code retranslation, we don't need to save the CPU state before.
target-mips: use the softfloat floatXX_muladd functions
Use the new softfloat floatXX_muladd() functions to implement the madd,msub, nmadd and nmsub instructions. At the same time replace the name ofthe helpers by the name of the instruction, as the only reason for the...
target-mips: remove #if defined(TARGET_MIPS64) in opcode enums
All switch() decoding instruction have a default entry, so it is possibleto have unused enum entries. Remove conditional definitions of MIPS64opcode enums, as it only makes the code less readable....
target-mips: Change TODO file
Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file.
Signed-off-by: Jia Liu <proljc@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Add ASE DSP accumulator instructions
Add MIPS ASE DSP Accumulator and DSPControl Access instructions.
target-mips: Add ASE DSP processors
Add 74kf and mips64dspr2-generic-cpu model for test.
target-mips: Add ASE DSP compare-pick instructions
Add MIPS ASE DSP Compare-Pick instructions.
target-mips: Add ASE DSP bit/manipulation instructions
Add MIPS ASE DSP Bit/Manipulation instructions.