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  ppc
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  s390
  sparc
  tci
LICENSE 146 Bytes
README 15 kB
TODO 394 Bytes
optimize.c 25.2 kB
tcg-op.h 84.2 kB
tcg-opc.h 9.6 kB
tcg-runtime.h 706 Bytes
tcg.c 75.7 kB
tcg.h 18.7 kB

Latest revisions

# Date Author Comment
2174d1e1 10/17/2012 02:26 am Aurelien Jarno

tcg/ia64: remove suboptimal register shifting in qemu_ld/st ops

Remove suboptimal register shifting in qemu_ld/st ops, introduced at the
CONFIG_TCG_PASS_AREG0 time.

As mem_idx is now loaded in register R58/R59 for the slow path, we have
to make sure to do it last, to not add additional register constraints....
63975ea7 10/17/2012 02:26 am Aurelien Jarno

tcg/ia64: slightly optimize TLB access code

It is possible to slightly optimize the TLB access code, by replacing
the movi + and instructions by a deposit instruction.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
c7d4475a 10/17/2012 02:26 am Richard Henderson

tcg-ia64: Implement deposit

Note that in the general reg=reg,reg case we're restricted
to 16-bit insertions. This makes it easy to allow "any"
constant as input, as post-truncation it will fit into the
constant load insn for which we have room in the bundle....
da897bf5 10/17/2012 02:26 am Blue Swirl

tcg/ia64: use stack for TCG temps

Use stack instead of temp_buf array in CPUState for TCG temps.

Signed-off-by: Blue Swirl <>
Signed-off-by: Aurelien Jarno <>
b90cf716 10/17/2012 02:26 am Aurelien Jarno

tcg/ia64: implement movcond_i32/64

Implement movcond_i32/64 on ia64 hosts. It is not possible to have
immediate compare arguments without adding a new bundle, but it is
possible to have 22-bit immediate value arguments.

Reviewed-by: Richard Henderson <>...
4a1d241e 10/17/2012 02:22 am Peter Maydell

tcg/arm: Implement movcond_i32

Implement movcond_i32 for ARM, as the sequence
mov dst, v2 (implicitly done by the tcg common code)
cmp c1, c2
movCC dst, v1

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
7fc645bf 10/17/2012 02:22 am Peter Maydell

tcg/arm: Factor out code to emit immediate or reg-reg op

The code to emit either an immediate cmp or a register cmp insn is
duplicated in several places; factor it out into its own function.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
a115f3ea 10/13/2012 01:39 pm Richard Henderson

tcg-sparc: Drop use of Bicc in favor of BPcc

Now that we're always sparcv9, we can not bother using Bicc for
32-bit branches and BPcc for 64-bit branches and instead always
use BPcc.

New interfaces allow less direct use of tcg_out32 and raw numbers
inside the qemu_ld/st routines....
ab1339b9 10/13/2012 01:39 pm Richard Henderson

tcg-sparc: Emit BPr insns for brcond_i64

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
203342d8 10/13/2012 01:39 pm Richard Henderson

tcg-sparc: Emit MOVR insns for setcond_i64 and movcond_64

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

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