root / hw / pci-host / ppce500.c @ 2c9b15ca
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1 | 74c62ba8 | aurel32 | /*
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2 | 74c62ba8 | aurel32 | * QEMU PowerPC E500 embedded processors pci controller emulation
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3 | 74c62ba8 | aurel32 | *
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4 | 74c62ba8 | aurel32 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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5 | 74c62ba8 | aurel32 | *
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6 | 74c62ba8 | aurel32 | * Author: Yu Liu, <yu.liu@freescale.com>
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7 | 74c62ba8 | aurel32 | *
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8 | 74c62ba8 | aurel32 | * This file is derived from hw/ppc4xx_pci.c,
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9 | 74c62ba8 | aurel32 | * the copyright for that material belongs to the original owners.
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10 | 74c62ba8 | aurel32 | *
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11 | 74c62ba8 | aurel32 | * This is free software; you can redistribute it and/or modify
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12 | 74c62ba8 | aurel32 | * it under the terms of the GNU General Public License as published by
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13 | 74c62ba8 | aurel32 | * the Free Software Foundation; either version 2 of the License, or
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14 | 74c62ba8 | aurel32 | * (at your option) any later version.
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15 | 74c62ba8 | aurel32 | */
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16 | 74c62ba8 | aurel32 | |
17 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
18 | 3eddc1be | Bharat Bhushan | #include "hw/ppc/e500-ccsr.h" |
19 | 83c9f4ca | Paolo Bonzini | #include "hw/pci/pci.h" |
20 | 83c9f4ca | Paolo Bonzini | #include "hw/pci/pci_host.h" |
21 | 1de7afc9 | Paolo Bonzini | #include "qemu/bswap.h" |
22 | 0d09e41a | Paolo Bonzini | #include "hw/pci-host/ppce500.h" |
23 | 74c62ba8 | aurel32 | |
24 | 74c62ba8 | aurel32 | #ifdef DEBUG_PCI
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25 | 001faf32 | Blue Swirl | #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) |
26 | 74c62ba8 | aurel32 | #else
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27 | 001faf32 | Blue Swirl | #define pci_debug(fmt, ...)
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28 | 74c62ba8 | aurel32 | #endif
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29 | 74c62ba8 | aurel32 | |
30 | 74c62ba8 | aurel32 | #define PCIE500_CFGADDR 0x0 |
31 | 74c62ba8 | aurel32 | #define PCIE500_CFGDATA 0x4 |
32 | 74c62ba8 | aurel32 | #define PCIE500_REG_BASE 0xC00 |
33 | be13cc7a | Alexander Graf | #define PCIE500_ALL_SIZE 0x1000 |
34 | be13cc7a | Alexander Graf | #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
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35 | 74c62ba8 | aurel32 | |
36 | a1bc20df | Alexander Graf | #define PCIE500_PCI_IOLEN 0x10000ULL |
37 | a1bc20df | Alexander Graf | |
38 | 74c62ba8 | aurel32 | #define PPCE500_PCI_CONFIG_ADDR 0x0 |
39 | 74c62ba8 | aurel32 | #define PPCE500_PCI_CONFIG_DATA 0x4 |
40 | 74c62ba8 | aurel32 | #define PPCE500_PCI_INTACK 0x8 |
41 | 74c62ba8 | aurel32 | |
42 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) |
43 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) |
44 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) |
45 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) |
46 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) |
47 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) |
48 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) |
49 | 74c62ba8 | aurel32 | |
50 | 74c62ba8 | aurel32 | #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) |
51 | 74c62ba8 | aurel32 | |
52 | 74c62ba8 | aurel32 | #define PCI_POTAR 0x0 |
53 | 74c62ba8 | aurel32 | #define PCI_POTEAR 0x4 |
54 | 74c62ba8 | aurel32 | #define PCI_POWBAR 0x8 |
55 | 74c62ba8 | aurel32 | #define PCI_POWAR 0x10 |
56 | 74c62ba8 | aurel32 | |
57 | 74c62ba8 | aurel32 | #define PCI_PITAR 0x0 |
58 | 74c62ba8 | aurel32 | #define PCI_PIWBAR 0x8 |
59 | 74c62ba8 | aurel32 | #define PCI_PIWBEAR 0xC |
60 | 74c62ba8 | aurel32 | #define PCI_PIWAR 0x10 |
61 | 74c62ba8 | aurel32 | |
62 | 74c62ba8 | aurel32 | #define PPCE500_PCI_NR_POBS 5 |
63 | 74c62ba8 | aurel32 | #define PPCE500_PCI_NR_PIBS 3 |
64 | 74c62ba8 | aurel32 | |
65 | 74c62ba8 | aurel32 | struct pci_outbound {
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66 | 74c62ba8 | aurel32 | uint32_t potar; |
67 | 74c62ba8 | aurel32 | uint32_t potear; |
68 | 74c62ba8 | aurel32 | uint32_t powbar; |
69 | 74c62ba8 | aurel32 | uint32_t powar; |
70 | 74c62ba8 | aurel32 | }; |
71 | 74c62ba8 | aurel32 | |
72 | 74c62ba8 | aurel32 | struct pci_inbound {
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73 | 74c62ba8 | aurel32 | uint32_t pitar; |
74 | 74c62ba8 | aurel32 | uint32_t piwbar; |
75 | 74c62ba8 | aurel32 | uint32_t piwbear; |
76 | 74c62ba8 | aurel32 | uint32_t piwar; |
77 | 74c62ba8 | aurel32 | }; |
78 | 74c62ba8 | aurel32 | |
79 | 9c1a61f0 | Andreas Färber | #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost" |
80 | 9c1a61f0 | Andreas Färber | |
81 | 9c1a61f0 | Andreas Färber | #define PPC_E500_PCI_HOST_BRIDGE(obj) \
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82 | 9c1a61f0 | Andreas Färber | OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE) |
83 | 9c1a61f0 | Andreas Färber | |
84 | 74c62ba8 | aurel32 | struct PPCE500PCIState {
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85 | 67c332fd | Andreas Färber | PCIHostState parent_obj; |
86 | 9c1a61f0 | Andreas Färber | |
87 | 74c62ba8 | aurel32 | struct pci_outbound pob[PPCE500_PCI_NR_POBS];
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88 | 74c62ba8 | aurel32 | struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
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89 | 74c62ba8 | aurel32 | uint32_t gasket_time; |
90 | be13cc7a | Alexander Graf | qemu_irq irq[4];
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91 | eafb325f | Alexander Graf | uint32_t first_slot; |
92 | be13cc7a | Alexander Graf | /* mmio maps */
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93 | cb4e15c7 | Benoît Canet | MemoryRegion container; |
94 | cd5cba79 | Avi Kivity | MemoryRegion iomem; |
95 | a1bc20df | Alexander Graf | MemoryRegion pio; |
96 | 74c62ba8 | aurel32 | }; |
97 | 74c62ba8 | aurel32 | |
98 | 3eddc1be | Bharat Bhushan | #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge" |
99 | 3eddc1be | Bharat Bhushan | #define PPC_E500_PCI_BRIDGE(obj) \
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100 | 3eddc1be | Bharat Bhushan | OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE) |
101 | 3eddc1be | Bharat Bhushan | |
102 | 3eddc1be | Bharat Bhushan | struct PPCE500PCIBridgeState {
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103 | 3eddc1be | Bharat Bhushan | /*< private >*/
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104 | 3eddc1be | Bharat Bhushan | PCIDevice parent; |
105 | 3eddc1be | Bharat Bhushan | /*< public >*/
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106 | 3eddc1be | Bharat Bhushan | |
107 | 3eddc1be | Bharat Bhushan | MemoryRegion bar0; |
108 | 3eddc1be | Bharat Bhushan | }; |
109 | 3eddc1be | Bharat Bhushan | |
110 | 3eddc1be | Bharat Bhushan | typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState; |
111 | 74c62ba8 | aurel32 | typedef struct PPCE500PCIState PPCE500PCIState; |
112 | 74c62ba8 | aurel32 | |
113 | a8170e5e | Avi Kivity | static uint64_t pci_reg_read4(void *opaque, hwaddr addr, |
114 | cd5cba79 | Avi Kivity | unsigned size)
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115 | 74c62ba8 | aurel32 | { |
116 | 74c62ba8 | aurel32 | PPCE500PCIState *pci = opaque; |
117 | 74c62ba8 | aurel32 | unsigned long win; |
118 | 74c62ba8 | aurel32 | uint32_t value = 0;
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119 | eeae2e7b | Liu Yu-B13201 | int idx;
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120 | 74c62ba8 | aurel32 | |
121 | 74c62ba8 | aurel32 | win = addr & 0xfe0;
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122 | 74c62ba8 | aurel32 | |
123 | 74c62ba8 | aurel32 | switch (win) {
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124 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW1:
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125 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW2:
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126 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW3:
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127 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW4:
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128 | eeae2e7b | Liu Yu-B13201 | idx = (addr >> 5) & 0x7; |
129 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
130 | 6875dc8e | Liu Yu-B13201 | case PCI_POTAR:
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131 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].potar; |
132 | 6875dc8e | Liu Yu-B13201 | break;
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133 | 6875dc8e | Liu Yu-B13201 | case PCI_POTEAR:
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134 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].potear; |
135 | 6875dc8e | Liu Yu-B13201 | break;
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136 | 6875dc8e | Liu Yu-B13201 | case PCI_POWBAR:
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137 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].powbar; |
138 | 6875dc8e | Liu Yu-B13201 | break;
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139 | 6875dc8e | Liu Yu-B13201 | case PCI_POWAR:
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140 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].powar; |
141 | 6875dc8e | Liu Yu-B13201 | break;
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142 | 6875dc8e | Liu Yu-B13201 | default:
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143 | 6875dc8e | Liu Yu-B13201 | break;
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144 | 74c62ba8 | aurel32 | } |
145 | 74c62ba8 | aurel32 | break;
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146 | 74c62ba8 | aurel32 | |
147 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW3:
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148 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW2:
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149 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW1:
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150 | eeae2e7b | Liu Yu-B13201 | idx = ((addr >> 5) & 0x3) - 1; |
151 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
152 | 6875dc8e | Liu Yu-B13201 | case PCI_PITAR:
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153 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].pitar; |
154 | 6875dc8e | Liu Yu-B13201 | break;
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155 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBAR:
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156 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].piwbar; |
157 | 6875dc8e | Liu Yu-B13201 | break;
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158 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBEAR:
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159 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].piwbear; |
160 | 6875dc8e | Liu Yu-B13201 | break;
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161 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWAR:
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162 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].piwar; |
163 | 6875dc8e | Liu Yu-B13201 | break;
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164 | 6875dc8e | Liu Yu-B13201 | default:
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165 | 6875dc8e | Liu Yu-B13201 | break;
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166 | 74c62ba8 | aurel32 | }; |
167 | 74c62ba8 | aurel32 | break;
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168 | 74c62ba8 | aurel32 | |
169 | 74c62ba8 | aurel32 | case PPCE500_PCI_GASKET_TIMR:
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170 | 74c62ba8 | aurel32 | value = pci->gasket_time; |
171 | 74c62ba8 | aurel32 | break;
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172 | 74c62ba8 | aurel32 | |
173 | 74c62ba8 | aurel32 | default:
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174 | 74c62ba8 | aurel32 | break;
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175 | 74c62ba8 | aurel32 | } |
176 | 74c62ba8 | aurel32 | |
177 | c0a2a096 | Blue Swirl | pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, |
178 | c0a2a096 | Blue Swirl | win, addr, value); |
179 | 74c62ba8 | aurel32 | return value;
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180 | 74c62ba8 | aurel32 | } |
181 | 74c62ba8 | aurel32 | |
182 | a8170e5e | Avi Kivity | static void pci_reg_write4(void *opaque, hwaddr addr, |
183 | cd5cba79 | Avi Kivity | uint64_t value, unsigned size)
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184 | 74c62ba8 | aurel32 | { |
185 | 74c62ba8 | aurel32 | PPCE500PCIState *pci = opaque; |
186 | 74c62ba8 | aurel32 | unsigned long win; |
187 | eeae2e7b | Liu Yu-B13201 | int idx;
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188 | 74c62ba8 | aurel32 | |
189 | 74c62ba8 | aurel32 | win = addr & 0xfe0;
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190 | 74c62ba8 | aurel32 | |
191 | c0a2a096 | Blue Swirl | pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", |
192 | cd5cba79 | Avi Kivity | __func__, (unsigned)value, win, addr);
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193 | 74c62ba8 | aurel32 | |
194 | 74c62ba8 | aurel32 | switch (win) {
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195 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW1:
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196 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW2:
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197 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW3:
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198 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW4:
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199 | eeae2e7b | Liu Yu-B13201 | idx = (addr >> 5) & 0x7; |
200 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
201 | 6875dc8e | Liu Yu-B13201 | case PCI_POTAR:
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202 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].potar = value; |
203 | 6875dc8e | Liu Yu-B13201 | break;
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204 | 6875dc8e | Liu Yu-B13201 | case PCI_POTEAR:
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205 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].potear = value; |
206 | 6875dc8e | Liu Yu-B13201 | break;
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207 | 6875dc8e | Liu Yu-B13201 | case PCI_POWBAR:
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208 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].powbar = value; |
209 | 6875dc8e | Liu Yu-B13201 | break;
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210 | 6875dc8e | Liu Yu-B13201 | case PCI_POWAR:
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211 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].powar = value; |
212 | 6875dc8e | Liu Yu-B13201 | break;
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213 | 6875dc8e | Liu Yu-B13201 | default:
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214 | 6875dc8e | Liu Yu-B13201 | break;
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215 | 74c62ba8 | aurel32 | }; |
216 | 74c62ba8 | aurel32 | break;
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217 | 74c62ba8 | aurel32 | |
218 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW3:
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219 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW2:
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220 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW1:
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221 | eeae2e7b | Liu Yu-B13201 | idx = ((addr >> 5) & 0x3) - 1; |
222 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
223 | 6875dc8e | Liu Yu-B13201 | case PCI_PITAR:
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224 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].pitar = value; |
225 | 6875dc8e | Liu Yu-B13201 | break;
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226 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBAR:
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227 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].piwbar = value; |
228 | 6875dc8e | Liu Yu-B13201 | break;
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229 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBEAR:
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230 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].piwbear = value; |
231 | 6875dc8e | Liu Yu-B13201 | break;
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232 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWAR:
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233 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].piwar = value; |
234 | 6875dc8e | Liu Yu-B13201 | break;
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235 | 6875dc8e | Liu Yu-B13201 | default:
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236 | 6875dc8e | Liu Yu-B13201 | break;
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237 | 74c62ba8 | aurel32 | }; |
238 | 74c62ba8 | aurel32 | break;
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239 | 74c62ba8 | aurel32 | |
240 | 74c62ba8 | aurel32 | case PPCE500_PCI_GASKET_TIMR:
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241 | 74c62ba8 | aurel32 | pci->gasket_time = value; |
242 | 74c62ba8 | aurel32 | break;
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243 | 74c62ba8 | aurel32 | |
244 | 74c62ba8 | aurel32 | default:
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245 | 74c62ba8 | aurel32 | break;
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246 | 74c62ba8 | aurel32 | }; |
247 | 74c62ba8 | aurel32 | } |
248 | 74c62ba8 | aurel32 | |
249 | cd5cba79 | Avi Kivity | static const MemoryRegionOps e500_pci_reg_ops = { |
250 | cd5cba79 | Avi Kivity | .read = pci_reg_read4, |
251 | cd5cba79 | Avi Kivity | .write = pci_reg_write4, |
252 | cd5cba79 | Avi Kivity | .endianness = DEVICE_BIG_ENDIAN, |
253 | 74c62ba8 | aurel32 | }; |
254 | 74c62ba8 | aurel32 | |
255 | 74c62ba8 | aurel32 | static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
256 | 74c62ba8 | aurel32 | { |
257 | 05f57d9d | Alexander Graf | int devno = pci_dev->devfn >> 3; |
258 | 05f57d9d | Alexander Graf | int ret;
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259 | 74c62ba8 | aurel32 | |
260 | 9e2c1298 | Alexander Graf | ret = ppce500_pci_map_irq_slot(devno, irq_num); |
261 | 74c62ba8 | aurel32 | |
262 | 74c62ba8 | aurel32 | pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
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263 | 74c62ba8 | aurel32 | pci_dev->devfn, irq_num, ret, devno); |
264 | 74c62ba8 | aurel32 | |
265 | 74c62ba8 | aurel32 | return ret;
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266 | 74c62ba8 | aurel32 | } |
267 | 74c62ba8 | aurel32 | |
268 | 5d4e84c8 | Juan Quintela | static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level) |
269 | 74c62ba8 | aurel32 | { |
270 | 5d4e84c8 | Juan Quintela | qemu_irq *pic = opaque; |
271 | 5d4e84c8 | Juan Quintela | |
272 | 74c62ba8 | aurel32 | pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
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273 | 74c62ba8 | aurel32 | |
274 | 74c62ba8 | aurel32 | qemu_set_irq(pic[irq_num], level); |
275 | 74c62ba8 | aurel32 | } |
276 | 74c62ba8 | aurel32 | |
277 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_pci_outbound = { |
278 | e0433ecc | Juan Quintela | .name = "pci_outbound",
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279 | e0433ecc | Juan Quintela | .version_id = 0,
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280 | e0433ecc | Juan Quintela | .minimum_version_id = 0,
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281 | e0433ecc | Juan Quintela | .minimum_version_id_old = 0,
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282 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
283 | e0433ecc | Juan Quintela | VMSTATE_UINT32(potar, struct pci_outbound),
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284 | e0433ecc | Juan Quintela | VMSTATE_UINT32(potear, struct pci_outbound),
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285 | e0433ecc | Juan Quintela | VMSTATE_UINT32(powbar, struct pci_outbound),
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286 | e0433ecc | Juan Quintela | VMSTATE_UINT32(powar, struct pci_outbound),
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287 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
288 | 74c62ba8 | aurel32 | } |
289 | e0433ecc | Juan Quintela | }; |
290 | 74c62ba8 | aurel32 | |
291 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_pci_inbound = { |
292 | e0433ecc | Juan Quintela | .name = "pci_inbound",
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293 | e0433ecc | Juan Quintela | .version_id = 0,
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294 | e0433ecc | Juan Quintela | .minimum_version_id = 0,
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295 | e0433ecc | Juan Quintela | .minimum_version_id_old = 0,
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296 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
297 | e0433ecc | Juan Quintela | VMSTATE_UINT32(pitar, struct pci_inbound),
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298 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwbar, struct pci_inbound),
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299 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwbear, struct pci_inbound),
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300 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwar, struct pci_inbound),
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301 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
302 | 74c62ba8 | aurel32 | } |
303 | e0433ecc | Juan Quintela | }; |
304 | 74c62ba8 | aurel32 | |
305 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_ppce500_pci = { |
306 | e0433ecc | Juan Quintela | .name = "ppce500_pci",
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307 | e0433ecc | Juan Quintela | .version_id = 1,
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308 | e0433ecc | Juan Quintela | .minimum_version_id = 1,
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309 | e0433ecc | Juan Quintela | .minimum_version_id_old = 1,
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310 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
311 | e0433ecc | Juan Quintela | VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
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312 | e0433ecc | Juan Quintela | vmstate_pci_outbound, struct pci_outbound),
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313 | e0433ecc | Juan Quintela | VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
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314 | e0433ecc | Juan Quintela | vmstate_pci_outbound, struct pci_inbound),
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315 | e0433ecc | Juan Quintela | VMSTATE_UINT32(gasket_time, PPCE500PCIState), |
316 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
317 | 74c62ba8 | aurel32 | } |
318 | e0433ecc | Juan Quintela | }; |
319 | 74c62ba8 | aurel32 | |
320 | 022c62cb | Paolo Bonzini | #include "exec/address-spaces.h" |
321 | 1e39101c | Avi Kivity | |
322 | 3eddc1be | Bharat Bhushan | static int e500_pcihost_bridge_initfn(PCIDevice *d) |
323 | 3eddc1be | Bharat Bhushan | { |
324 | 3eddc1be | Bharat Bhushan | PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d); |
325 | 3eddc1be | Bharat Bhushan | PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(), |
326 | 3eddc1be | Bharat Bhushan | "/e500-ccsr"));
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327 | 3eddc1be | Bharat Bhushan | |
328 | 99750506 | Alexander Graf | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); |
329 | 99750506 | Alexander Graf | d->config[PCI_HEADER_TYPE] = |
330 | 99750506 | Alexander Graf | (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | |
331 | 99750506 | Alexander Graf | PCI_HEADER_TYPE_BRIDGE; |
332 | 99750506 | Alexander Graf | |
333 | 2c9b15ca | Paolo Bonzini | memory_region_init_alias(&b->bar0, NULL, "e500-pci-bar0", &ccsr->ccsr_space, |
334 | 3eddc1be | Bharat Bhushan | 0, int128_get64(ccsr->ccsr_space.size));
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335 | 3eddc1be | Bharat Bhushan | pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
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336 | 99750506 | Alexander Graf | |
337 | 3eddc1be | Bharat Bhushan | return 0; |
338 | 3eddc1be | Bharat Bhushan | } |
339 | 3eddc1be | Bharat Bhushan | |
340 | be13cc7a | Alexander Graf | static int e500_pcihost_initfn(SysBusDevice *dev) |
341 | be13cc7a | Alexander Graf | { |
342 | be13cc7a | Alexander Graf | PCIHostState *h; |
343 | be13cc7a | Alexander Graf | PPCE500PCIState *s; |
344 | be13cc7a | Alexander Graf | PCIBus *b; |
345 | be13cc7a | Alexander Graf | int i;
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346 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem = get_system_memory(); |
347 | be13cc7a | Alexander Graf | |
348 | 8558d942 | Andreas Färber | h = PCI_HOST_BRIDGE(dev); |
349 | 9c1a61f0 | Andreas Färber | s = PPC_E500_PCI_HOST_BRIDGE(dev); |
350 | be13cc7a | Alexander Graf | |
351 | be13cc7a | Alexander Graf | for (i = 0; i < ARRAY_SIZE(s->irq); i++) { |
352 | be13cc7a | Alexander Graf | sysbus_init_irq(dev, &s->irq[i]); |
353 | be13cc7a | Alexander Graf | } |
354 | be13cc7a | Alexander Graf | |
355 | 2c9b15ca | Paolo Bonzini | memory_region_init(&s->pio, NULL, "pci-pio", PCIE500_PCI_IOLEN); |
356 | a1bc20df | Alexander Graf | |
357 | 9c1a61f0 | Andreas Färber | b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
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358 | aee97b84 | Avi Kivity | mpc85xx_pci_map_irq, s->irq, address_space_mem, |
359 | 60a0e443 | Alex Williamson | &s->pio, PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS); |
360 | 9c1a61f0 | Andreas Färber | h->bus = b; |
361 | be13cc7a | Alexander Graf | |
362 | be13cc7a | Alexander Graf | pci_create_simple(b, 0, "e500-host-bridge"); |
363 | be13cc7a | Alexander Graf | |
364 | 2c9b15ca | Paolo Bonzini | memory_region_init(&s->container, NULL, "pci-container", PCIE500_ALL_SIZE); |
365 | 2c9b15ca | Paolo Bonzini | memory_region_init_io(&h->conf_mem, NULL, &pci_host_conf_be_ops, h,
|
366 | d0ed8076 | Avi Kivity | "pci-conf-idx", 4); |
367 | 2c9b15ca | Paolo Bonzini | memory_region_init_io(&h->data_mem, NULL, &pci_host_data_le_ops, h,
|
368 | d0ed8076 | Avi Kivity | "pci-conf-data", 4); |
369 | 2c9b15ca | Paolo Bonzini | memory_region_init_io(&s->iomem, NULL, &e500_pci_reg_ops, s,
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370 | cd5cba79 | Avi Kivity | "pci.reg", PCIE500_REG_SIZE);
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371 | cb4e15c7 | Benoît Canet | memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem); |
372 | cb4e15c7 | Benoît Canet | memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); |
373 | cb4e15c7 | Benoît Canet | memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); |
374 | cb4e15c7 | Benoît Canet | sysbus_init_mmio(dev, &s->container); |
375 | a1bc20df | Alexander Graf | sysbus_init_mmio(dev, &s->pio); |
376 | be13cc7a | Alexander Graf | |
377 | be13cc7a | Alexander Graf | return 0; |
378 | be13cc7a | Alexander Graf | } |
379 | be13cc7a | Alexander Graf | |
380 | 40021f08 | Anthony Liguori | static void e500_host_bridge_class_init(ObjectClass *klass, void *data) |
381 | 40021f08 | Anthony Liguori | { |
382 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
383 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
384 | 40021f08 | Anthony Liguori | |
385 | 3eddc1be | Bharat Bhushan | k->init = e500_pcihost_bridge_initfn; |
386 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_FREESCALE; |
387 | 40021f08 | Anthony Liguori | k->device_id = PCI_DEVICE_ID_MPC8533E; |
388 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_PROCESSOR_POWERPC; |
389 | 39bffca2 | Anthony Liguori | dc->desc = "Host bridge";
|
390 | 40021f08 | Anthony Liguori | } |
391 | 40021f08 | Anthony Liguori | |
392 | 4240abff | Andreas Färber | static const TypeInfo e500_host_bridge_info = { |
393 | 39bffca2 | Anthony Liguori | .name = "e500-host-bridge",
|
394 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
395 | 3eddc1be | Bharat Bhushan | .instance_size = sizeof(PPCE500PCIBridgeState),
|
396 | 39bffca2 | Anthony Liguori | .class_init = e500_host_bridge_class_init, |
397 | be13cc7a | Alexander Graf | }; |
398 | be13cc7a | Alexander Graf | |
399 | eafb325f | Alexander Graf | static Property pcihost_properties[] = {
|
400 | eafb325f | Alexander Graf | DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11), |
401 | eafb325f | Alexander Graf | DEFINE_PROP_END_OF_LIST(), |
402 | eafb325f | Alexander Graf | }; |
403 | eafb325f | Alexander Graf | |
404 | 999e12bb | Anthony Liguori | static void e500_pcihost_class_init(ObjectClass *klass, void *data) |
405 | 999e12bb | Anthony Liguori | { |
406 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
407 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
408 | 999e12bb | Anthony Liguori | |
409 | 999e12bb | Anthony Liguori | k->init = e500_pcihost_initfn; |
410 | eafb325f | Alexander Graf | dc->props = pcihost_properties; |
411 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_ppce500_pci; |
412 | 999e12bb | Anthony Liguori | } |
413 | 999e12bb | Anthony Liguori | |
414 | 4240abff | Andreas Färber | static const TypeInfo e500_pcihost_info = { |
415 | 9c1a61f0 | Andreas Färber | .name = TYPE_PPC_E500_PCI_HOST_BRIDGE, |
416 | 8558d942 | Andreas Färber | .parent = TYPE_PCI_HOST_BRIDGE, |
417 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PPCE500PCIState),
|
418 | 39bffca2 | Anthony Liguori | .class_init = e500_pcihost_class_init, |
419 | be13cc7a | Alexander Graf | }; |
420 | be13cc7a | Alexander Graf | |
421 | 83f7d43a | Andreas Färber | static void e500_pci_register_types(void) |
422 | 74c62ba8 | aurel32 | { |
423 | 39bffca2 | Anthony Liguori | type_register_static(&e500_pcihost_info); |
424 | 39bffca2 | Anthony Liguori | type_register_static(&e500_host_bridge_info); |
425 | 74c62ba8 | aurel32 | } |
426 | 83f7d43a | Andreas Färber | |
427 | 83f7d43a | Andreas Färber | type_init(e500_pci_register_types) |