ARM: fix ldrexd/strexd
Correct ldrexd and strexd code to always read and write thehigh word of the 64-bit value from addr+4.Also make ldrexd and strexd agree that for a 64 bit value theaddress in env->exclusive_addr is that of the low word.
This fixes the issues reported in...
ARM: Fix decoding of VFP forms of VCVT between float and int/fixed
Correct the decoding of source and destination registersfor the VFP forms of the VCVT instructions which convertbetween floating point and integer or fixed-point.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
ARM: Fix decoding of Neon forms of VCVT between float and fixed point
Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted...
ARM: Fix sense of to_integer bit in Neon VCVT float/int conversion
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
softfloat: Add float*_is_any_nan() functions
Add float*_is_any_nan() functions which return true if the argumentis a NaN of any kind (quiet or signalling).
ARM: Return correct result for float-to-integer conversion of NaN
The ARM architecture mandates that converting a NaN value tointeger gives zero (if Invalid Operation FP exceptions arenot being trapped). This isn't the behaviour of the SoftFloatlibrary, so NaNs must be special-cased....
softfloat: Add float*_maybe_silence_nan() functions
Add functions float*_maybe_silence_nan() which ensure that avalue is not a signaling NaN by turning it into a quiet NaN.
ARM: Return correct result for single<->double conversion of NaN
The ARM ARM defines that if the input to a single<->double conversionis a NaN then the output is always forced to be a quiet NaN by settingthe most significant bit of the fraction part.
target-arm: Fix mixup in decoding of saturating add and sub
The thumb2 decoder contained a mixup between the bit controllingdoubling and the bit controlling if the operation was an add or a sub.
Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Handle 'smc' as an undefined instruction
Refine check on bkpt so that smc and undefined instruction encodings arehandled as an undefined instruction and trap.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
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