root / hw / rc4030.c @ 2d9401aa
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1 | 4ce7ff6e | aurel32 | /*
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2 | 4ce7ff6e | aurel32 | * QEMU JAZZ RC4030 chipset
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3 | 4ce7ff6e | aurel32 | *
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4 | 9ea0b7a1 | aurel32 | * Copyright (c) 2007-2009 Herve Poussineau
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5 | 4ce7ff6e | aurel32 | *
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6 | 4ce7ff6e | aurel32 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 4ce7ff6e | aurel32 | * of this software and associated documentation files (the "Software"), to deal
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8 | 4ce7ff6e | aurel32 | * in the Software without restriction, including without limitation the rights
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9 | 4ce7ff6e | aurel32 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 4ce7ff6e | aurel32 | * copies of the Software, and to permit persons to whom the Software is
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11 | 4ce7ff6e | aurel32 | * furnished to do so, subject to the following conditions:
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12 | 4ce7ff6e | aurel32 | *
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13 | 4ce7ff6e | aurel32 | * The above copyright notice and this permission notice shall be included in
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14 | 4ce7ff6e | aurel32 | * all copies or substantial portions of the Software.
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15 | 4ce7ff6e | aurel32 | *
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16 | 4ce7ff6e | aurel32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 4ce7ff6e | aurel32 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 4ce7ff6e | aurel32 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 4ce7ff6e | aurel32 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 4ce7ff6e | aurel32 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 4ce7ff6e | aurel32 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 4ce7ff6e | aurel32 | * THE SOFTWARE.
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23 | 4ce7ff6e | aurel32 | */
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24 | 4ce7ff6e | aurel32 | |
25 | 4ce7ff6e | aurel32 | #include "hw.h" |
26 | cd5158ea | aurel32 | #include "mips.h" |
27 | 4ce7ff6e | aurel32 | #include "qemu-timer.h" |
28 | 4ce7ff6e | aurel32 | |
29 | c6945b15 | aurel32 | /********************************************************/
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30 | c6945b15 | aurel32 | /* debug rc4030 */
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31 | c6945b15 | aurel32 | |
32 | 4ce7ff6e | aurel32 | //#define DEBUG_RC4030
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33 | c6945b15 | aurel32 | //#define DEBUG_RC4030_DMA
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34 | 4ce7ff6e | aurel32 | |
35 | 4ce7ff6e | aurel32 | #ifdef DEBUG_RC4030
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36 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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37 | 001faf32 | Blue Swirl | do { printf("rc4030: " fmt , ## __VA_ARGS__); } while (0) |
38 | 4ce7ff6e | aurel32 | static const char* irq_names[] = { "parallel", "floppy", "sound", "video", |
39 | 4ce7ff6e | aurel32 | "network", "scsi", "keyboard", "mouse", "serial0", "serial1" }; |
40 | c6945b15 | aurel32 | #else
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41 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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42 | 4ce7ff6e | aurel32 | #endif
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43 | 4ce7ff6e | aurel32 | |
44 | 001faf32 | Blue Swirl | #define RC4030_ERROR(fmt, ...) \
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45 | 001faf32 | Blue Swirl | do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) |
46 | c6945b15 | aurel32 | |
47 | c6945b15 | aurel32 | /********************************************************/
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48 | c6945b15 | aurel32 | /* rc4030 emulation */
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49 | c6945b15 | aurel32 | |
50 | c6945b15 | aurel32 | typedef struct dma_pagetable_entry { |
51 | c6945b15 | aurel32 | int32_t frame; |
52 | c6945b15 | aurel32 | int32_t owner; |
53 | c6945b15 | aurel32 | } __attribute__((packed)) dma_pagetable_entry; |
54 | c6945b15 | aurel32 | |
55 | c6945b15 | aurel32 | #define DMA_PAGESIZE 4096 |
56 | c6945b15 | aurel32 | #define DMA_REG_ENABLE 1 |
57 | c6945b15 | aurel32 | #define DMA_REG_COUNT 2 |
58 | c6945b15 | aurel32 | #define DMA_REG_ADDRESS 3 |
59 | c6945b15 | aurel32 | |
60 | c6945b15 | aurel32 | #define DMA_FLAG_ENABLE 0x0001 |
61 | c6945b15 | aurel32 | #define DMA_FLAG_MEM_TO_DEV 0x0002 |
62 | c6945b15 | aurel32 | #define DMA_FLAG_TC_INTR 0x0100 |
63 | c6945b15 | aurel32 | #define DMA_FLAG_MEM_INTR 0x0200 |
64 | c6945b15 | aurel32 | #define DMA_FLAG_ADDR_INTR 0x0400 |
65 | c6945b15 | aurel32 | |
66 | 4ce7ff6e | aurel32 | typedef struct rc4030State |
67 | 4ce7ff6e | aurel32 | { |
68 | 4ce7ff6e | aurel32 | uint32_t config; /* 0x0000: RC4030 config register */
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69 | 9ea0b7a1 | aurel32 | uint32_t revision; /* 0x0008: RC4030 Revision register */
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70 | 4ce7ff6e | aurel32 | uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
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71 | 4ce7ff6e | aurel32 | |
72 | 4ce7ff6e | aurel32 | /* DMA */
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73 | 4ce7ff6e | aurel32 | uint32_t dma_regs[8][4]; |
74 | 4ce7ff6e | aurel32 | uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
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75 | 4ce7ff6e | aurel32 | uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
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76 | 4ce7ff6e | aurel32 | |
77 | 4ce7ff6e | aurel32 | /* cache */
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78 | 9ea0b7a1 | aurel32 | uint32_t cache_maint; /* 0x0030: Cache Maintenance */
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79 | 4ce7ff6e | aurel32 | uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
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80 | 4ce7ff6e | aurel32 | uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
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81 | 4ce7ff6e | aurel32 | uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
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82 | 4ce7ff6e | aurel32 | uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
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83 | 4ce7ff6e | aurel32 | uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
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84 | 4ce7ff6e | aurel32 | |
85 | 9ea0b7a1 | aurel32 | uint32_t nmi_interrupt; /* 0x0200: interrupt source */
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86 | 4ce7ff6e | aurel32 | uint32_t offset210; |
87 | 4ce7ff6e | aurel32 | uint32_t nvram_protect; /* 0x0220: NV ram protect register */
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88 | 9ea0b7a1 | aurel32 | uint32_t rem_speed[16];
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89 | 4ce7ff6e | aurel32 | uint32_t imr_jazz; /* Local bus int enable mask */
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90 | 4ce7ff6e | aurel32 | uint32_t isr_jazz; /* Local bus int source */
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91 | 4ce7ff6e | aurel32 | |
92 | 4ce7ff6e | aurel32 | /* timer */
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93 | 4ce7ff6e | aurel32 | QEMUTimer *periodic_timer; |
94 | 4ce7ff6e | aurel32 | uint32_t itr; /* Interval timer reload */
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95 | 4ce7ff6e | aurel32 | |
96 | 4ce7ff6e | aurel32 | qemu_irq timer_irq; |
97 | 4ce7ff6e | aurel32 | qemu_irq jazz_bus_irq; |
98 | 4ce7ff6e | aurel32 | } rc4030State; |
99 | 4ce7ff6e | aurel32 | |
100 | 4ce7ff6e | aurel32 | static void set_next_tick(rc4030State *s) |
101 | 4ce7ff6e | aurel32 | { |
102 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->timer_irq); |
103 | b0f74c87 | balrog | uint32_t tm_hz; |
104 | 4ce7ff6e | aurel32 | |
105 | b0f74c87 | balrog | tm_hz = 1000 / (s->itr + 1); |
106 | 4ce7ff6e | aurel32 | |
107 | b0f74c87 | balrog | qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) + ticks_per_sec / tm_hz); |
108 | 4ce7ff6e | aurel32 | } |
109 | 4ce7ff6e | aurel32 | |
110 | 4ce7ff6e | aurel32 | /* called for accesses to rc4030 */
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111 | 4ce7ff6e | aurel32 | static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr) |
112 | 4ce7ff6e | aurel32 | { |
113 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
114 | 4ce7ff6e | aurel32 | uint32_t val; |
115 | 4ce7ff6e | aurel32 | |
116 | 4ce7ff6e | aurel32 | addr &= 0x3fff;
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117 | 4ce7ff6e | aurel32 | switch (addr & ~0x3) { |
118 | 4ce7ff6e | aurel32 | /* Global config register */
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119 | 4ce7ff6e | aurel32 | case 0x0000: |
120 | 4ce7ff6e | aurel32 | val = s->config; |
121 | 4ce7ff6e | aurel32 | break;
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122 | 9ea0b7a1 | aurel32 | /* Revision register */
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123 | 9ea0b7a1 | aurel32 | case 0x0008: |
124 | 9ea0b7a1 | aurel32 | val = s->revision; |
125 | 9ea0b7a1 | aurel32 | break;
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126 | 4ce7ff6e | aurel32 | /* Invalid Address register */
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127 | 4ce7ff6e | aurel32 | case 0x0010: |
128 | 4ce7ff6e | aurel32 | val = s->invalid_address_register; |
129 | 4ce7ff6e | aurel32 | break;
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130 | 4ce7ff6e | aurel32 | /* DMA transl. table base */
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131 | 4ce7ff6e | aurel32 | case 0x0018: |
132 | 4ce7ff6e | aurel32 | val = s->dma_tl_base; |
133 | 4ce7ff6e | aurel32 | break;
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134 | 4ce7ff6e | aurel32 | /* DMA transl. table limit */
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135 | 4ce7ff6e | aurel32 | case 0x0020: |
136 | 4ce7ff6e | aurel32 | val = s->dma_tl_limit; |
137 | 4ce7ff6e | aurel32 | break;
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138 | 4ce7ff6e | aurel32 | /* Remote Failed Address */
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139 | 4ce7ff6e | aurel32 | case 0x0038: |
140 | 4ce7ff6e | aurel32 | val = s->remote_failed_address; |
141 | 4ce7ff6e | aurel32 | break;
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142 | 4ce7ff6e | aurel32 | /* Memory Failed Address */
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143 | 4ce7ff6e | aurel32 | case 0x0040: |
144 | 4ce7ff6e | aurel32 | val = s->memory_failed_address; |
145 | 4ce7ff6e | aurel32 | break;
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146 | 4ce7ff6e | aurel32 | /* I/O Cache Byte Mask */
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147 | 4ce7ff6e | aurel32 | case 0x0058: |
148 | 4ce7ff6e | aurel32 | val = s->cache_bmask; |
149 | 4ce7ff6e | aurel32 | /* HACK */
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150 | 4ce7ff6e | aurel32 | if (s->cache_bmask == (uint32_t)-1) |
151 | 4ce7ff6e | aurel32 | s->cache_bmask = 0;
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152 | 4ce7ff6e | aurel32 | break;
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153 | 4ce7ff6e | aurel32 | /* Remote Speed Registers */
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154 | 4ce7ff6e | aurel32 | case 0x0070: |
155 | 4ce7ff6e | aurel32 | case 0x0078: |
156 | 4ce7ff6e | aurel32 | case 0x0080: |
157 | 4ce7ff6e | aurel32 | case 0x0088: |
158 | 4ce7ff6e | aurel32 | case 0x0090: |
159 | 4ce7ff6e | aurel32 | case 0x0098: |
160 | 4ce7ff6e | aurel32 | case 0x00a0: |
161 | 4ce7ff6e | aurel32 | case 0x00a8: |
162 | 4ce7ff6e | aurel32 | case 0x00b0: |
163 | 4ce7ff6e | aurel32 | case 0x00b8: |
164 | 4ce7ff6e | aurel32 | case 0x00c0: |
165 | 4ce7ff6e | aurel32 | case 0x00c8: |
166 | 4ce7ff6e | aurel32 | case 0x00d0: |
167 | 4ce7ff6e | aurel32 | case 0x00d8: |
168 | 4ce7ff6e | aurel32 | case 0x00e0: |
169 | 9ea0b7a1 | aurel32 | case 0x00e8: |
170 | 4ce7ff6e | aurel32 | val = s->rem_speed[(addr - 0x0070) >> 3]; |
171 | 4ce7ff6e | aurel32 | break;
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172 | 4ce7ff6e | aurel32 | /* DMA channel base address */
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173 | 4ce7ff6e | aurel32 | case 0x0100: |
174 | 4ce7ff6e | aurel32 | case 0x0108: |
175 | 4ce7ff6e | aurel32 | case 0x0110: |
176 | 4ce7ff6e | aurel32 | case 0x0118: |
177 | 4ce7ff6e | aurel32 | case 0x0120: |
178 | 4ce7ff6e | aurel32 | case 0x0128: |
179 | 4ce7ff6e | aurel32 | case 0x0130: |
180 | 4ce7ff6e | aurel32 | case 0x0138: |
181 | 4ce7ff6e | aurel32 | case 0x0140: |
182 | 4ce7ff6e | aurel32 | case 0x0148: |
183 | 4ce7ff6e | aurel32 | case 0x0150: |
184 | 4ce7ff6e | aurel32 | case 0x0158: |
185 | 4ce7ff6e | aurel32 | case 0x0160: |
186 | 4ce7ff6e | aurel32 | case 0x0168: |
187 | 4ce7ff6e | aurel32 | case 0x0170: |
188 | 4ce7ff6e | aurel32 | case 0x0178: |
189 | 4ce7ff6e | aurel32 | case 0x0180: |
190 | 4ce7ff6e | aurel32 | case 0x0188: |
191 | 4ce7ff6e | aurel32 | case 0x0190: |
192 | 4ce7ff6e | aurel32 | case 0x0198: |
193 | 4ce7ff6e | aurel32 | case 0x01a0: |
194 | 4ce7ff6e | aurel32 | case 0x01a8: |
195 | 4ce7ff6e | aurel32 | case 0x01b0: |
196 | 4ce7ff6e | aurel32 | case 0x01b8: |
197 | 4ce7ff6e | aurel32 | case 0x01c0: |
198 | 4ce7ff6e | aurel32 | case 0x01c8: |
199 | 4ce7ff6e | aurel32 | case 0x01d0: |
200 | 4ce7ff6e | aurel32 | case 0x01d8: |
201 | 4ce7ff6e | aurel32 | case 0x01e0: |
202 | c6945b15 | aurel32 | case 0x01e8: |
203 | 4ce7ff6e | aurel32 | case 0x01f0: |
204 | 4ce7ff6e | aurel32 | case 0x01f8: |
205 | 4ce7ff6e | aurel32 | { |
206 | 4ce7ff6e | aurel32 | int entry = (addr - 0x0100) >> 5; |
207 | 4ce7ff6e | aurel32 | int idx = (addr & 0x1f) >> 3; |
208 | 4ce7ff6e | aurel32 | val = s->dma_regs[entry][idx]; |
209 | 4ce7ff6e | aurel32 | } |
210 | 4ce7ff6e | aurel32 | break;
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211 | 9ea0b7a1 | aurel32 | /* Interrupt source */
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212 | 9ea0b7a1 | aurel32 | case 0x0200: |
213 | 9ea0b7a1 | aurel32 | val = s->nmi_interrupt; |
214 | 9ea0b7a1 | aurel32 | break;
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215 | 9ea0b7a1 | aurel32 | /* Error type */
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216 | 4ce7ff6e | aurel32 | case 0x0208: |
217 | c6945b15 | aurel32 | val = 0;
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218 | 4ce7ff6e | aurel32 | break;
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219 | 4ce7ff6e | aurel32 | /* Offset 0x0210 */
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220 | 4ce7ff6e | aurel32 | case 0x0210: |
221 | 4ce7ff6e | aurel32 | val = s->offset210; |
222 | 4ce7ff6e | aurel32 | break;
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223 | 4ce7ff6e | aurel32 | /* NV ram protect register */
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224 | 4ce7ff6e | aurel32 | case 0x0220: |
225 | 4ce7ff6e | aurel32 | val = s->nvram_protect; |
226 | 4ce7ff6e | aurel32 | break;
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227 | 4ce7ff6e | aurel32 | /* Interval timer count */
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228 | 4ce7ff6e | aurel32 | case 0x0230: |
229 | c6945b15 | aurel32 | val = 0;
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230 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->timer_irq); |
231 | 4ce7ff6e | aurel32 | break;
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232 | 9ea0b7a1 | aurel32 | /* EISA interrupt */
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233 | 4ce7ff6e | aurel32 | case 0x0238: |
234 | 9ea0b7a1 | aurel32 | val = 7; /* FIXME: should be read from EISA controller */ |
235 | 4ce7ff6e | aurel32 | break;
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236 | 4ce7ff6e | aurel32 | default:
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237 | c6945b15 | aurel32 | RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr); |
238 | 4ce7ff6e | aurel32 | val = 0;
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239 | 4ce7ff6e | aurel32 | break;
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240 | 4ce7ff6e | aurel32 | } |
241 | 4ce7ff6e | aurel32 | |
242 | 4ce7ff6e | aurel32 | if ((addr & ~3) != 0x230) |
243 | c6945b15 | aurel32 | DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr); |
244 | 4ce7ff6e | aurel32 | |
245 | 4ce7ff6e | aurel32 | return val;
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246 | 4ce7ff6e | aurel32 | } |
247 | 4ce7ff6e | aurel32 | |
248 | 4ce7ff6e | aurel32 | static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr) |
249 | 4ce7ff6e | aurel32 | { |
250 | 4ce7ff6e | aurel32 | uint32_t v = rc4030_readl(opaque, addr & ~0x3);
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251 | 4ce7ff6e | aurel32 | if (addr & 0x2) |
252 | 4ce7ff6e | aurel32 | return v >> 16; |
253 | 4ce7ff6e | aurel32 | else
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254 | 4ce7ff6e | aurel32 | return v & 0xffff; |
255 | 4ce7ff6e | aurel32 | } |
256 | 4ce7ff6e | aurel32 | |
257 | 4ce7ff6e | aurel32 | static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr) |
258 | 4ce7ff6e | aurel32 | { |
259 | 4ce7ff6e | aurel32 | uint32_t v = rc4030_readl(opaque, addr & ~0x3);
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260 | 4ce7ff6e | aurel32 | return (v >> (8 * (addr & 0x3))) & 0xff; |
261 | 4ce7ff6e | aurel32 | } |
262 | 4ce7ff6e | aurel32 | |
263 | 4ce7ff6e | aurel32 | static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
264 | 4ce7ff6e | aurel32 | { |
265 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
266 | 4ce7ff6e | aurel32 | addr &= 0x3fff;
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267 | 4ce7ff6e | aurel32 | |
268 | c6945b15 | aurel32 | DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr); |
269 | 4ce7ff6e | aurel32 | |
270 | 4ce7ff6e | aurel32 | switch (addr & ~0x3) { |
271 | 4ce7ff6e | aurel32 | /* Global config register */
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272 | 4ce7ff6e | aurel32 | case 0x0000: |
273 | 4ce7ff6e | aurel32 | s->config = val; |
274 | 4ce7ff6e | aurel32 | break;
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275 | 4ce7ff6e | aurel32 | /* DMA transl. table base */
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276 | 4ce7ff6e | aurel32 | case 0x0018: |
277 | 4ce7ff6e | aurel32 | s->dma_tl_base = val; |
278 | 4ce7ff6e | aurel32 | break;
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279 | 4ce7ff6e | aurel32 | /* DMA transl. table limit */
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280 | 4ce7ff6e | aurel32 | case 0x0020: |
281 | 4ce7ff6e | aurel32 | s->dma_tl_limit = val; |
282 | 4ce7ff6e | aurel32 | break;
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283 | c6945b15 | aurel32 | /* DMA transl. table invalidated */
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284 | c6945b15 | aurel32 | case 0x0028: |
285 | c6945b15 | aurel32 | break;
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286 | c6945b15 | aurel32 | /* Cache Maintenance */
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287 | c6945b15 | aurel32 | case 0x0030: |
288 | 9ea0b7a1 | aurel32 | s->cache_maint = val; |
289 | c6945b15 | aurel32 | break;
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290 | 4ce7ff6e | aurel32 | /* I/O Cache Physical Tag */
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291 | 4ce7ff6e | aurel32 | case 0x0048: |
292 | 4ce7ff6e | aurel32 | s->cache_ptag = val; |
293 | 4ce7ff6e | aurel32 | break;
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294 | 4ce7ff6e | aurel32 | /* I/O Cache Logical Tag */
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295 | 4ce7ff6e | aurel32 | case 0x0050: |
296 | 4ce7ff6e | aurel32 | s->cache_ltag = val; |
297 | 4ce7ff6e | aurel32 | break;
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298 | 4ce7ff6e | aurel32 | /* I/O Cache Byte Mask */
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299 | 4ce7ff6e | aurel32 | case 0x0058: |
300 | 4ce7ff6e | aurel32 | s->cache_bmask |= val; /* HACK */
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301 | 4ce7ff6e | aurel32 | break;
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302 | 4ce7ff6e | aurel32 | /* I/O Cache Buffer Window */
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303 | 4ce7ff6e | aurel32 | case 0x0060: |
304 | 4ce7ff6e | aurel32 | /* HACK */
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305 | 4ce7ff6e | aurel32 | if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) { |
306 | 9ea0b7a1 | aurel32 | target_phys_addr_t dest = s->cache_ptag & ~0x1;
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307 | 9ea0b7a1 | aurel32 | dest += (s->cache_maint & 0x3) << 3; |
308 | 9ea0b7a1 | aurel32 | cpu_physical_memory_rw(dest, (uint8_t*)&val, 4, 1); |
309 | 4ce7ff6e | aurel32 | } |
310 | 4ce7ff6e | aurel32 | break;
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311 | 4ce7ff6e | aurel32 | /* Remote Speed Registers */
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312 | 4ce7ff6e | aurel32 | case 0x0070: |
313 | 4ce7ff6e | aurel32 | case 0x0078: |
314 | 4ce7ff6e | aurel32 | case 0x0080: |
315 | 4ce7ff6e | aurel32 | case 0x0088: |
316 | 4ce7ff6e | aurel32 | case 0x0090: |
317 | 4ce7ff6e | aurel32 | case 0x0098: |
318 | 4ce7ff6e | aurel32 | case 0x00a0: |
319 | 4ce7ff6e | aurel32 | case 0x00a8: |
320 | 4ce7ff6e | aurel32 | case 0x00b0: |
321 | 4ce7ff6e | aurel32 | case 0x00b8: |
322 | 4ce7ff6e | aurel32 | case 0x00c0: |
323 | 4ce7ff6e | aurel32 | case 0x00c8: |
324 | 4ce7ff6e | aurel32 | case 0x00d0: |
325 | 4ce7ff6e | aurel32 | case 0x00d8: |
326 | 4ce7ff6e | aurel32 | case 0x00e0: |
327 | 9ea0b7a1 | aurel32 | case 0x00e8: |
328 | 4ce7ff6e | aurel32 | s->rem_speed[(addr - 0x0070) >> 3] = val; |
329 | 4ce7ff6e | aurel32 | break;
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330 | 4ce7ff6e | aurel32 | /* DMA channel base address */
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331 | 4ce7ff6e | aurel32 | case 0x0100: |
332 | 4ce7ff6e | aurel32 | case 0x0108: |
333 | 4ce7ff6e | aurel32 | case 0x0110: |
334 | 4ce7ff6e | aurel32 | case 0x0118: |
335 | 4ce7ff6e | aurel32 | case 0x0120: |
336 | 4ce7ff6e | aurel32 | case 0x0128: |
337 | 4ce7ff6e | aurel32 | case 0x0130: |
338 | 4ce7ff6e | aurel32 | case 0x0138: |
339 | 4ce7ff6e | aurel32 | case 0x0140: |
340 | 4ce7ff6e | aurel32 | case 0x0148: |
341 | 4ce7ff6e | aurel32 | case 0x0150: |
342 | 4ce7ff6e | aurel32 | case 0x0158: |
343 | 4ce7ff6e | aurel32 | case 0x0160: |
344 | 4ce7ff6e | aurel32 | case 0x0168: |
345 | 4ce7ff6e | aurel32 | case 0x0170: |
346 | 4ce7ff6e | aurel32 | case 0x0178: |
347 | 4ce7ff6e | aurel32 | case 0x0180: |
348 | 4ce7ff6e | aurel32 | case 0x0188: |
349 | 4ce7ff6e | aurel32 | case 0x0190: |
350 | 4ce7ff6e | aurel32 | case 0x0198: |
351 | 4ce7ff6e | aurel32 | case 0x01a0: |
352 | 4ce7ff6e | aurel32 | case 0x01a8: |
353 | 4ce7ff6e | aurel32 | case 0x01b0: |
354 | 4ce7ff6e | aurel32 | case 0x01b8: |
355 | 4ce7ff6e | aurel32 | case 0x01c0: |
356 | 4ce7ff6e | aurel32 | case 0x01c8: |
357 | 4ce7ff6e | aurel32 | case 0x01d0: |
358 | 4ce7ff6e | aurel32 | case 0x01d8: |
359 | 4ce7ff6e | aurel32 | case 0x01e0: |
360 | c6945b15 | aurel32 | case 0x01e8: |
361 | 4ce7ff6e | aurel32 | case 0x01f0: |
362 | 4ce7ff6e | aurel32 | case 0x01f8: |
363 | 4ce7ff6e | aurel32 | { |
364 | 4ce7ff6e | aurel32 | int entry = (addr - 0x0100) >> 5; |
365 | 4ce7ff6e | aurel32 | int idx = (addr & 0x1f) >> 3; |
366 | 4ce7ff6e | aurel32 | s->dma_regs[entry][idx] = val; |
367 | 4ce7ff6e | aurel32 | } |
368 | 4ce7ff6e | aurel32 | break;
|
369 | 4ce7ff6e | aurel32 | /* Offset 0x0210 */
|
370 | 4ce7ff6e | aurel32 | case 0x0210: |
371 | 4ce7ff6e | aurel32 | s->offset210 = val; |
372 | 4ce7ff6e | aurel32 | break;
|
373 | 4ce7ff6e | aurel32 | /* Interval timer reload */
|
374 | 4ce7ff6e | aurel32 | case 0x0228: |
375 | 4ce7ff6e | aurel32 | s->itr = val; |
376 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->timer_irq); |
377 | 4ce7ff6e | aurel32 | set_next_tick(s); |
378 | 4ce7ff6e | aurel32 | break;
|
379 | 9ea0b7a1 | aurel32 | /* EISA interrupt */
|
380 | 9ea0b7a1 | aurel32 | case 0x0238: |
381 | 9ea0b7a1 | aurel32 | break;
|
382 | 4ce7ff6e | aurel32 | default:
|
383 | c6945b15 | aurel32 | RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr); |
384 | 4ce7ff6e | aurel32 | break;
|
385 | 4ce7ff6e | aurel32 | } |
386 | 4ce7ff6e | aurel32 | } |
387 | 4ce7ff6e | aurel32 | |
388 | 4ce7ff6e | aurel32 | static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
389 | 4ce7ff6e | aurel32 | { |
390 | 4ce7ff6e | aurel32 | uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
|
391 | 4ce7ff6e | aurel32 | |
392 | 4ce7ff6e | aurel32 | if (addr & 0x2) |
393 | 4ce7ff6e | aurel32 | val = (val << 16) | (old_val & 0x0000ffff); |
394 | 4ce7ff6e | aurel32 | else
|
395 | 4ce7ff6e | aurel32 | val = val | (old_val & 0xffff0000);
|
396 | 4ce7ff6e | aurel32 | rc4030_writel(opaque, addr & ~0x3, val);
|
397 | 4ce7ff6e | aurel32 | } |
398 | 4ce7ff6e | aurel32 | |
399 | 4ce7ff6e | aurel32 | static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
400 | 4ce7ff6e | aurel32 | { |
401 | 4ce7ff6e | aurel32 | uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
|
402 | 4ce7ff6e | aurel32 | |
403 | 4ce7ff6e | aurel32 | switch (addr & 3) { |
404 | 4ce7ff6e | aurel32 | case 0: |
405 | 4ce7ff6e | aurel32 | val = val | (old_val & 0xffffff00);
|
406 | 4ce7ff6e | aurel32 | break;
|
407 | 4ce7ff6e | aurel32 | case 1: |
408 | 4ce7ff6e | aurel32 | val = (val << 8) | (old_val & 0xffff00ff); |
409 | 4ce7ff6e | aurel32 | break;
|
410 | 4ce7ff6e | aurel32 | case 2: |
411 | 4ce7ff6e | aurel32 | val = (val << 16) | (old_val & 0xff00ffff); |
412 | 4ce7ff6e | aurel32 | break;
|
413 | 4ce7ff6e | aurel32 | case 3: |
414 | 4ce7ff6e | aurel32 | val = (val << 24) | (old_val & 0x00ffffff); |
415 | 4ce7ff6e | aurel32 | break;
|
416 | 4ce7ff6e | aurel32 | } |
417 | 4ce7ff6e | aurel32 | rc4030_writel(opaque, addr & ~0x3, val);
|
418 | 4ce7ff6e | aurel32 | } |
419 | 4ce7ff6e | aurel32 | |
420 | 4ce7ff6e | aurel32 | static CPUReadMemoryFunc *rc4030_read[3] = { |
421 | 4ce7ff6e | aurel32 | rc4030_readb, |
422 | 4ce7ff6e | aurel32 | rc4030_readw, |
423 | 4ce7ff6e | aurel32 | rc4030_readl, |
424 | 4ce7ff6e | aurel32 | }; |
425 | 4ce7ff6e | aurel32 | |
426 | 4ce7ff6e | aurel32 | static CPUWriteMemoryFunc *rc4030_write[3] = { |
427 | 4ce7ff6e | aurel32 | rc4030_writeb, |
428 | 4ce7ff6e | aurel32 | rc4030_writew, |
429 | 4ce7ff6e | aurel32 | rc4030_writel, |
430 | 4ce7ff6e | aurel32 | }; |
431 | 4ce7ff6e | aurel32 | |
432 | 4ce7ff6e | aurel32 | static void update_jazz_irq(rc4030State *s) |
433 | 4ce7ff6e | aurel32 | { |
434 | 4ce7ff6e | aurel32 | uint16_t pending; |
435 | 4ce7ff6e | aurel32 | |
436 | 4ce7ff6e | aurel32 | pending = s->isr_jazz & s->imr_jazz; |
437 | 4ce7ff6e | aurel32 | |
438 | 4ce7ff6e | aurel32 | #ifdef DEBUG_RC4030
|
439 | 4ce7ff6e | aurel32 | if (s->isr_jazz != 0) { |
440 | 4ce7ff6e | aurel32 | uint32_t irq = 0;
|
441 | c6945b15 | aurel32 | DPRINTF("pending irqs:");
|
442 | b1503cda | malc | for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) { |
443 | 4ce7ff6e | aurel32 | if (s->isr_jazz & (1 << irq)) { |
444 | 4ce7ff6e | aurel32 | printf(" %s", irq_names[irq]);
|
445 | 4ce7ff6e | aurel32 | if (!(s->imr_jazz & (1 << irq))) { |
446 | 4ce7ff6e | aurel32 | printf("(ignored)");
|
447 | 4ce7ff6e | aurel32 | } |
448 | 4ce7ff6e | aurel32 | } |
449 | 4ce7ff6e | aurel32 | } |
450 | 4ce7ff6e | aurel32 | printf("\n");
|
451 | 4ce7ff6e | aurel32 | } |
452 | 4ce7ff6e | aurel32 | #endif
|
453 | 4ce7ff6e | aurel32 | |
454 | 4ce7ff6e | aurel32 | if (pending != 0) |
455 | 4ce7ff6e | aurel32 | qemu_irq_raise(s->jazz_bus_irq); |
456 | 4ce7ff6e | aurel32 | else
|
457 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->jazz_bus_irq); |
458 | 4ce7ff6e | aurel32 | } |
459 | 4ce7ff6e | aurel32 | |
460 | 4ce7ff6e | aurel32 | static void rc4030_irq_jazz_request(void *opaque, int irq, int level) |
461 | 4ce7ff6e | aurel32 | { |
462 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
463 | 4ce7ff6e | aurel32 | |
464 | 4ce7ff6e | aurel32 | if (level) {
|
465 | 4ce7ff6e | aurel32 | s->isr_jazz |= 1 << irq;
|
466 | 4ce7ff6e | aurel32 | } else {
|
467 | 4ce7ff6e | aurel32 | s->isr_jazz &= ~(1 << irq);
|
468 | 4ce7ff6e | aurel32 | } |
469 | 4ce7ff6e | aurel32 | |
470 | 4ce7ff6e | aurel32 | update_jazz_irq(s); |
471 | 4ce7ff6e | aurel32 | } |
472 | 4ce7ff6e | aurel32 | |
473 | 4ce7ff6e | aurel32 | static void rc4030_periodic_timer(void *opaque) |
474 | 4ce7ff6e | aurel32 | { |
475 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
476 | 4ce7ff6e | aurel32 | |
477 | 4ce7ff6e | aurel32 | set_next_tick(s); |
478 | 4ce7ff6e | aurel32 | qemu_irq_raise(s->timer_irq); |
479 | 4ce7ff6e | aurel32 | } |
480 | 4ce7ff6e | aurel32 | |
481 | c6945b15 | aurel32 | static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr) |
482 | 4ce7ff6e | aurel32 | { |
483 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
484 | 4ce7ff6e | aurel32 | uint32_t val; |
485 | 4ce7ff6e | aurel32 | uint32_t irq; |
486 | 4ce7ff6e | aurel32 | addr &= 0xfff;
|
487 | 4ce7ff6e | aurel32 | |
488 | 4ce7ff6e | aurel32 | switch (addr) {
|
489 | c6945b15 | aurel32 | /* Local bus int source */
|
490 | 4ce7ff6e | aurel32 | case 0x00: { |
491 | 4ce7ff6e | aurel32 | uint32_t pending = s->isr_jazz & s->imr_jazz; |
492 | 4ce7ff6e | aurel32 | val = 0;
|
493 | 4ce7ff6e | aurel32 | irq = 0;
|
494 | 4ce7ff6e | aurel32 | while (pending) {
|
495 | 4ce7ff6e | aurel32 | if (pending & 1) { |
496 | c6945b15 | aurel32 | DPRINTF("returning irq %s\n", irq_names[irq]);
|
497 | 4ce7ff6e | aurel32 | val = (irq + 1) << 2; |
498 | 4ce7ff6e | aurel32 | break;
|
499 | 4ce7ff6e | aurel32 | } |
500 | 4ce7ff6e | aurel32 | irq++; |
501 | 4ce7ff6e | aurel32 | pending >>= 1;
|
502 | 4ce7ff6e | aurel32 | } |
503 | 4ce7ff6e | aurel32 | break;
|
504 | 4ce7ff6e | aurel32 | } |
505 | c6945b15 | aurel32 | /* Local bus int enable mask */
|
506 | c6945b15 | aurel32 | case 0x02: |
507 | c6945b15 | aurel32 | val = s->imr_jazz; |
508 | c6945b15 | aurel32 | break;
|
509 | 4ce7ff6e | aurel32 | default:
|
510 | c6945b15 | aurel32 | RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr); |
511 | c6945b15 | aurel32 | val = 0;
|
512 | 4ce7ff6e | aurel32 | } |
513 | 4ce7ff6e | aurel32 | |
514 | c6945b15 | aurel32 | DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr); |
515 | 4ce7ff6e | aurel32 | |
516 | 4ce7ff6e | aurel32 | return val;
|
517 | 4ce7ff6e | aurel32 | } |
518 | 4ce7ff6e | aurel32 | |
519 | c6945b15 | aurel32 | static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr) |
520 | 4ce7ff6e | aurel32 | { |
521 | 4ce7ff6e | aurel32 | uint32_t v; |
522 | c6945b15 | aurel32 | v = jazzio_readw(opaque, addr & ~0x1);
|
523 | c6945b15 | aurel32 | return (v >> (8 * (addr & 0x1))) & 0xff; |
524 | 4ce7ff6e | aurel32 | } |
525 | 4ce7ff6e | aurel32 | |
526 | c6945b15 | aurel32 | static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr) |
527 | 4ce7ff6e | aurel32 | { |
528 | 4ce7ff6e | aurel32 | uint32_t v; |
529 | c6945b15 | aurel32 | v = jazzio_readw(opaque, addr); |
530 | c6945b15 | aurel32 | v |= jazzio_readw(opaque, addr + 2) << 16; |
531 | 4ce7ff6e | aurel32 | return v;
|
532 | 4ce7ff6e | aurel32 | } |
533 | 4ce7ff6e | aurel32 | |
534 | c6945b15 | aurel32 | static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
535 | 4ce7ff6e | aurel32 | { |
536 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
537 | 4ce7ff6e | aurel32 | addr &= 0xfff;
|
538 | 4ce7ff6e | aurel32 | |
539 | c6945b15 | aurel32 | DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr); |
540 | 4ce7ff6e | aurel32 | |
541 | 4ce7ff6e | aurel32 | switch (addr) {
|
542 | 4ce7ff6e | aurel32 | /* Local bus int enable mask */
|
543 | 4ce7ff6e | aurel32 | case 0x02: |
544 | c6945b15 | aurel32 | s->imr_jazz = val; |
545 | c6945b15 | aurel32 | update_jazz_irq(s); |
546 | 4ce7ff6e | aurel32 | break;
|
547 | 4ce7ff6e | aurel32 | default:
|
548 | c6945b15 | aurel32 | RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr); |
549 | 4ce7ff6e | aurel32 | break;
|
550 | 4ce7ff6e | aurel32 | } |
551 | 4ce7ff6e | aurel32 | } |
552 | 4ce7ff6e | aurel32 | |
553 | c6945b15 | aurel32 | static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
554 | 4ce7ff6e | aurel32 | { |
555 | c6945b15 | aurel32 | uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
|
556 | c6945b15 | aurel32 | |
557 | c6945b15 | aurel32 | switch (addr & 1) { |
558 | c6945b15 | aurel32 | case 0: |
559 | c6945b15 | aurel32 | val = val | (old_val & 0xff00);
|
560 | c6945b15 | aurel32 | break;
|
561 | c6945b15 | aurel32 | case 1: |
562 | c6945b15 | aurel32 | val = (val << 8) | (old_val & 0x00ff); |
563 | c6945b15 | aurel32 | break;
|
564 | c6945b15 | aurel32 | } |
565 | c6945b15 | aurel32 | jazzio_writew(opaque, addr & ~0x1, val);
|
566 | 4ce7ff6e | aurel32 | } |
567 | 4ce7ff6e | aurel32 | |
568 | c6945b15 | aurel32 | static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
569 | 4ce7ff6e | aurel32 | { |
570 | c6945b15 | aurel32 | jazzio_writew(opaque, addr, val & 0xffff);
|
571 | c6945b15 | aurel32 | jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff); |
572 | 4ce7ff6e | aurel32 | } |
573 | 4ce7ff6e | aurel32 | |
574 | c6945b15 | aurel32 | static CPUReadMemoryFunc *jazzio_read[3] = { |
575 | c6945b15 | aurel32 | jazzio_readb, |
576 | c6945b15 | aurel32 | jazzio_readw, |
577 | c6945b15 | aurel32 | jazzio_readl, |
578 | 4ce7ff6e | aurel32 | }; |
579 | 4ce7ff6e | aurel32 | |
580 | c6945b15 | aurel32 | static CPUWriteMemoryFunc *jazzio_write[3] = { |
581 | c6945b15 | aurel32 | jazzio_writeb, |
582 | c6945b15 | aurel32 | jazzio_writew, |
583 | c6945b15 | aurel32 | jazzio_writel, |
584 | 4ce7ff6e | aurel32 | }; |
585 | 4ce7ff6e | aurel32 | |
586 | 4ce7ff6e | aurel32 | static void rc4030_reset(void *opaque) |
587 | 4ce7ff6e | aurel32 | { |
588 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
589 | 4ce7ff6e | aurel32 | int i;
|
590 | 4ce7ff6e | aurel32 | |
591 | c6945b15 | aurel32 | s->config = 0x410; /* some boards seem to accept 0x104 too */ |
592 | 9ea0b7a1 | aurel32 | s->revision = 1;
|
593 | 4ce7ff6e | aurel32 | s->invalid_address_register = 0;
|
594 | 4ce7ff6e | aurel32 | |
595 | 4ce7ff6e | aurel32 | memset(s->dma_regs, 0, sizeof(s->dma_regs)); |
596 | 4ce7ff6e | aurel32 | s->dma_tl_base = s->dma_tl_limit = 0;
|
597 | 4ce7ff6e | aurel32 | |
598 | 4ce7ff6e | aurel32 | s->remote_failed_address = s->memory_failed_address = 0;
|
599 | 9ea0b7a1 | aurel32 | s->cache_maint = 0;
|
600 | 4ce7ff6e | aurel32 | s->cache_ptag = s->cache_ltag = 0;
|
601 | 9ea0b7a1 | aurel32 | s->cache_bmask = 0;
|
602 | 4ce7ff6e | aurel32 | |
603 | 4ce7ff6e | aurel32 | s->offset210 = 0x18186;
|
604 | 4ce7ff6e | aurel32 | s->nvram_protect = 7;
|
605 | 4ce7ff6e | aurel32 | for (i = 0; i < 15; i++) |
606 | 4ce7ff6e | aurel32 | s->rem_speed[i] = 7;
|
607 | 9ea0b7a1 | aurel32 | s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */ |
608 | 9ea0b7a1 | aurel32 | s->isr_jazz = 0;
|
609 | 4ce7ff6e | aurel32 | |
610 | 4ce7ff6e | aurel32 | s->itr = 0;
|
611 | 4ce7ff6e | aurel32 | |
612 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->timer_irq); |
613 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->jazz_bus_irq); |
614 | 4ce7ff6e | aurel32 | } |
615 | 4ce7ff6e | aurel32 | |
616 | d5853c20 | aurel32 | static int rc4030_load(QEMUFile *f, void *opaque, int version_id) |
617 | d5853c20 | aurel32 | { |
618 | d5853c20 | aurel32 | rc4030State* s = opaque; |
619 | d5853c20 | aurel32 | int i, j;
|
620 | d5853c20 | aurel32 | |
621 | 9ea0b7a1 | aurel32 | if (version_id != 2) |
622 | d5853c20 | aurel32 | return -EINVAL;
|
623 | d5853c20 | aurel32 | |
624 | d5853c20 | aurel32 | s->config = qemu_get_be32(f); |
625 | d5853c20 | aurel32 | s->invalid_address_register = qemu_get_be32(f); |
626 | d5853c20 | aurel32 | for (i = 0; i < 8; i++) |
627 | d5853c20 | aurel32 | for (j = 0; j < 4; j++) |
628 | d5853c20 | aurel32 | s->dma_regs[i][j] = qemu_get_be32(f); |
629 | d5853c20 | aurel32 | s->dma_tl_base = qemu_get_be32(f); |
630 | d5853c20 | aurel32 | s->dma_tl_limit = qemu_get_be32(f); |
631 | 9ea0b7a1 | aurel32 | s->cache_maint = qemu_get_be32(f); |
632 | d5853c20 | aurel32 | s->remote_failed_address = qemu_get_be32(f); |
633 | d5853c20 | aurel32 | s->memory_failed_address = qemu_get_be32(f); |
634 | d5853c20 | aurel32 | s->cache_ptag = qemu_get_be32(f); |
635 | d5853c20 | aurel32 | s->cache_ltag = qemu_get_be32(f); |
636 | d5853c20 | aurel32 | s->cache_bmask = qemu_get_be32(f); |
637 | d5853c20 | aurel32 | s->offset210 = qemu_get_be32(f); |
638 | d5853c20 | aurel32 | s->nvram_protect = qemu_get_be32(f); |
639 | d5853c20 | aurel32 | for (i = 0; i < 15; i++) |
640 | d5853c20 | aurel32 | s->rem_speed[i] = qemu_get_be32(f); |
641 | d5853c20 | aurel32 | s->imr_jazz = qemu_get_be32(f); |
642 | d5853c20 | aurel32 | s->isr_jazz = qemu_get_be32(f); |
643 | d5853c20 | aurel32 | s->itr = qemu_get_be32(f); |
644 | d5853c20 | aurel32 | |
645 | d5853c20 | aurel32 | set_next_tick(s); |
646 | d5853c20 | aurel32 | update_jazz_irq(s); |
647 | d5853c20 | aurel32 | |
648 | d5853c20 | aurel32 | return 0; |
649 | d5853c20 | aurel32 | } |
650 | d5853c20 | aurel32 | |
651 | d5853c20 | aurel32 | static void rc4030_save(QEMUFile *f, void *opaque) |
652 | d5853c20 | aurel32 | { |
653 | d5853c20 | aurel32 | rc4030State* s = opaque; |
654 | d5853c20 | aurel32 | int i, j;
|
655 | d5853c20 | aurel32 | |
656 | d5853c20 | aurel32 | qemu_put_be32(f, s->config); |
657 | d5853c20 | aurel32 | qemu_put_be32(f, s->invalid_address_register); |
658 | d5853c20 | aurel32 | for (i = 0; i < 8; i++) |
659 | d5853c20 | aurel32 | for (j = 0; j < 4; j++) |
660 | d5853c20 | aurel32 | qemu_put_be32(f, s->dma_regs[i][j]); |
661 | d5853c20 | aurel32 | qemu_put_be32(f, s->dma_tl_base); |
662 | d5853c20 | aurel32 | qemu_put_be32(f, s->dma_tl_limit); |
663 | 9ea0b7a1 | aurel32 | qemu_put_be32(f, s->cache_maint); |
664 | d5853c20 | aurel32 | qemu_put_be32(f, s->remote_failed_address); |
665 | d5853c20 | aurel32 | qemu_put_be32(f, s->memory_failed_address); |
666 | d5853c20 | aurel32 | qemu_put_be32(f, s->cache_ptag); |
667 | d5853c20 | aurel32 | qemu_put_be32(f, s->cache_ltag); |
668 | d5853c20 | aurel32 | qemu_put_be32(f, s->cache_bmask); |
669 | d5853c20 | aurel32 | qemu_put_be32(f, s->offset210); |
670 | d5853c20 | aurel32 | qemu_put_be32(f, s->nvram_protect); |
671 | d5853c20 | aurel32 | for (i = 0; i < 15; i++) |
672 | d5853c20 | aurel32 | qemu_put_be32(f, s->rem_speed[i]); |
673 | d5853c20 | aurel32 | qemu_put_be32(f, s->imr_jazz); |
674 | d5853c20 | aurel32 | qemu_put_be32(f, s->isr_jazz); |
675 | d5853c20 | aurel32 | qemu_put_be32(f, s->itr); |
676 | d5853c20 | aurel32 | } |
677 | d5853c20 | aurel32 | |
678 | 68238a9e | aurel32 | void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write) |
679 | c6945b15 | aurel32 | { |
680 | c6945b15 | aurel32 | rc4030State *s = opaque; |
681 | c6945b15 | aurel32 | target_phys_addr_t entry_addr; |
682 | 9ea0b7a1 | aurel32 | target_phys_addr_t phys_addr; |
683 | c6945b15 | aurel32 | dma_pagetable_entry entry; |
684 | 9ea0b7a1 | aurel32 | int index;
|
685 | c6945b15 | aurel32 | int ncpy, i;
|
686 | c6945b15 | aurel32 | |
687 | c6945b15 | aurel32 | i = 0;
|
688 | c6945b15 | aurel32 | for (;;) {
|
689 | c6945b15 | aurel32 | if (i == len) {
|
690 | c6945b15 | aurel32 | break;
|
691 | c6945b15 | aurel32 | } |
692 | c6945b15 | aurel32 | |
693 | 9ea0b7a1 | aurel32 | ncpy = DMA_PAGESIZE - (addr & (DMA_PAGESIZE - 1));
|
694 | c6945b15 | aurel32 | if (ncpy > len - i)
|
695 | c6945b15 | aurel32 | ncpy = len - i; |
696 | c6945b15 | aurel32 | |
697 | c6945b15 | aurel32 | /* Get DMA translation table entry */
|
698 | 9ea0b7a1 | aurel32 | index = addr / DMA_PAGESIZE; |
699 | c6945b15 | aurel32 | if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) { |
700 | c6945b15 | aurel32 | break;
|
701 | c6945b15 | aurel32 | } |
702 | c6945b15 | aurel32 | entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
|
703 | c6945b15 | aurel32 | /* XXX: not sure. should we really use only lowest bits? */
|
704 | c6945b15 | aurel32 | entry_addr &= 0x7fffffff;
|
705 | c6945b15 | aurel32 | cpu_physical_memory_rw(entry_addr, (uint8_t *)&entry, sizeof(entry), 0); |
706 | c6945b15 | aurel32 | |
707 | c6945b15 | aurel32 | /* Read/write data at right place */
|
708 | 9ea0b7a1 | aurel32 | phys_addr = entry.frame + (addr & (DMA_PAGESIZE - 1));
|
709 | c6945b15 | aurel32 | cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write); |
710 | c6945b15 | aurel32 | |
711 | c6945b15 | aurel32 | i += ncpy; |
712 | 9ea0b7a1 | aurel32 | addr += ncpy; |
713 | 9ea0b7a1 | aurel32 | } |
714 | 9ea0b7a1 | aurel32 | } |
715 | 9ea0b7a1 | aurel32 | |
716 | 9ea0b7a1 | aurel32 | static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write) |
717 | 9ea0b7a1 | aurel32 | { |
718 | 9ea0b7a1 | aurel32 | rc4030State *s = opaque; |
719 | 9ea0b7a1 | aurel32 | target_phys_addr_t dma_addr; |
720 | 9ea0b7a1 | aurel32 | int dev_to_mem;
|
721 | 9ea0b7a1 | aurel32 | |
722 | 9ea0b7a1 | aurel32 | s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR); |
723 | 9ea0b7a1 | aurel32 | |
724 | 9ea0b7a1 | aurel32 | /* Check DMA channel consistency */
|
725 | 9ea0b7a1 | aurel32 | dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1; |
726 | 9ea0b7a1 | aurel32 | if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
|
727 | 9ea0b7a1 | aurel32 | (is_write != dev_to_mem)) { |
728 | 9ea0b7a1 | aurel32 | s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR; |
729 | 9ea0b7a1 | aurel32 | s->nmi_interrupt |= 1 << n;
|
730 | 9ea0b7a1 | aurel32 | return;
|
731 | c6945b15 | aurel32 | } |
732 | c6945b15 | aurel32 | |
733 | 9ea0b7a1 | aurel32 | /* Get start address and len */
|
734 | 9ea0b7a1 | aurel32 | if (len > s->dma_regs[n][DMA_REG_COUNT])
|
735 | 9ea0b7a1 | aurel32 | len = s->dma_regs[n][DMA_REG_COUNT]; |
736 | 9ea0b7a1 | aurel32 | dma_addr = s->dma_regs[n][DMA_REG_ADDRESS]; |
737 | 9ea0b7a1 | aurel32 | |
738 | 9ea0b7a1 | aurel32 | /* Read/write data at right place */
|
739 | 9ea0b7a1 | aurel32 | rc4030_dma_memory_rw(opaque, dma_addr, buf, len, is_write); |
740 | 9ea0b7a1 | aurel32 | |
741 | 9ea0b7a1 | aurel32 | s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR; |
742 | 9ea0b7a1 | aurel32 | s->dma_regs[n][DMA_REG_COUNT] -= len; |
743 | 9ea0b7a1 | aurel32 | |
744 | c6945b15 | aurel32 | #ifdef DEBUG_RC4030_DMA
|
745 | c6945b15 | aurel32 | { |
746 | c6945b15 | aurel32 | int i, j;
|
747 | c6945b15 | aurel32 | printf("rc4030 dma: Copying %d bytes %s host %p\n",
|
748 | c6945b15 | aurel32 | len, is_write ? "from" : "to", buf); |
749 | c6945b15 | aurel32 | for (i = 0; i < len; i += 16) { |
750 | c6945b15 | aurel32 | int n = min(16, len - i); |
751 | c6945b15 | aurel32 | for (j = 0; j < n; j++) |
752 | c6945b15 | aurel32 | printf("%02x ", buf[i + j]);
|
753 | c6945b15 | aurel32 | while (j++ < 16) |
754 | c6945b15 | aurel32 | printf(" ");
|
755 | c6945b15 | aurel32 | printf("| ");
|
756 | c6945b15 | aurel32 | for (j = 0; j < n; j++) |
757 | c6945b15 | aurel32 | printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.'); |
758 | c6945b15 | aurel32 | printf("\n");
|
759 | c6945b15 | aurel32 | } |
760 | c6945b15 | aurel32 | } |
761 | c6945b15 | aurel32 | #endif
|
762 | c6945b15 | aurel32 | } |
763 | c6945b15 | aurel32 | |
764 | c6945b15 | aurel32 | struct rc4030DMAState {
|
765 | c6945b15 | aurel32 | void *opaque;
|
766 | c6945b15 | aurel32 | int n;
|
767 | c6945b15 | aurel32 | }; |
768 | c6945b15 | aurel32 | |
769 | 68238a9e | aurel32 | void rc4030_dma_read(void *dma, uint8_t *buf, int len) |
770 | c6945b15 | aurel32 | { |
771 | c6945b15 | aurel32 | rc4030_dma s = dma; |
772 | c6945b15 | aurel32 | rc4030_do_dma(s->opaque, s->n, buf, len, 0);
|
773 | c6945b15 | aurel32 | } |
774 | c6945b15 | aurel32 | |
775 | 68238a9e | aurel32 | void rc4030_dma_write(void *dma, uint8_t *buf, int len) |
776 | c6945b15 | aurel32 | { |
777 | c6945b15 | aurel32 | rc4030_dma s = dma; |
778 | c6945b15 | aurel32 | rc4030_do_dma(s->opaque, s->n, buf, len, 1);
|
779 | c6945b15 | aurel32 | } |
780 | c6945b15 | aurel32 | |
781 | c6945b15 | aurel32 | static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n) |
782 | c6945b15 | aurel32 | { |
783 | c6945b15 | aurel32 | rc4030_dma *s; |
784 | c6945b15 | aurel32 | struct rc4030DMAState *p;
|
785 | c6945b15 | aurel32 | int i;
|
786 | c6945b15 | aurel32 | |
787 | c6945b15 | aurel32 | s = (rc4030_dma *)qemu_mallocz(sizeof(rc4030_dma) * n);
|
788 | c6945b15 | aurel32 | p = (struct rc4030DMAState *)qemu_mallocz(sizeof(struct rc4030DMAState) * n); |
789 | c6945b15 | aurel32 | for (i = 0; i < n; i++) { |
790 | c6945b15 | aurel32 | p->opaque = opaque; |
791 | c6945b15 | aurel32 | p->n = i; |
792 | c6945b15 | aurel32 | s[i] = p; |
793 | c6945b15 | aurel32 | p++; |
794 | c6945b15 | aurel32 | } |
795 | c6945b15 | aurel32 | return s;
|
796 | c6945b15 | aurel32 | } |
797 | c6945b15 | aurel32 | |
798 | 68238a9e | aurel32 | void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
|
799 | 68238a9e | aurel32 | qemu_irq **irqs, rc4030_dma **dmas) |
800 | 4ce7ff6e | aurel32 | { |
801 | 4ce7ff6e | aurel32 | rc4030State *s; |
802 | c6945b15 | aurel32 | int s_chipset, s_jazzio;
|
803 | 4ce7ff6e | aurel32 | |
804 | 4ce7ff6e | aurel32 | s = qemu_mallocz(sizeof(rc4030State));
|
805 | 4ce7ff6e | aurel32 | |
806 | 68238a9e | aurel32 | *irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
|
807 | c6945b15 | aurel32 | *dmas = rc4030_allocate_dmas(s, 4);
|
808 | c6945b15 | aurel32 | |
809 | 4ce7ff6e | aurel32 | s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s); |
810 | 4ce7ff6e | aurel32 | s->timer_irq = timer; |
811 | 4ce7ff6e | aurel32 | s->jazz_bus_irq = jazz_bus; |
812 | 4ce7ff6e | aurel32 | |
813 | 4ce7ff6e | aurel32 | qemu_register_reset(rc4030_reset, s); |
814 | 9ea0b7a1 | aurel32 | register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s); |
815 | 4ce7ff6e | aurel32 | rc4030_reset(s); |
816 | 4ce7ff6e | aurel32 | |
817 | 4ce7ff6e | aurel32 | s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s);
|
818 | 4ce7ff6e | aurel32 | cpu_register_physical_memory(0x80000000, 0x300, s_chipset); |
819 | c6945b15 | aurel32 | s_jazzio = cpu_register_io_memory(0, jazzio_read, jazzio_write, s);
|
820 | c6945b15 | aurel32 | cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio); |
821 | 4ce7ff6e | aurel32 | |
822 | 68238a9e | aurel32 | return s;
|
823 | 4ce7ff6e | aurel32 | } |