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/*
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* QEMU JAZZ RC4030 chipset
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*
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* Copyright (c) 2007-2009 Herve Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "mips.h" |
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#include "qemu-timer.h" |
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/********************************************************/
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/* debug rc4030 */
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//#define DEBUG_RC4030
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//#define DEBUG_RC4030_DMA
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#ifdef DEBUG_RC4030
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#define DPRINTF(fmt, ...) \
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do { printf("rc4030: " fmt , ## __VA_ARGS__); } while (0) |
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static const char* irq_names[] = { "parallel", "floppy", "sound", "video", |
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"network", "scsi", "keyboard", "mouse", "serial0", "serial1" }; |
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define RC4030_ERROR(fmt, ...) \
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do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) |
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/********************************************************/
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/* rc4030 emulation */
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typedef struct dma_pagetable_entry { |
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int32_t frame; |
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int32_t owner; |
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} __attribute__((packed)) dma_pagetable_entry; |
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|
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#define DMA_PAGESIZE 4096 |
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#define DMA_REG_ENABLE 1 |
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#define DMA_REG_COUNT 2 |
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#define DMA_REG_ADDRESS 3 |
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#define DMA_FLAG_ENABLE 0x0001 |
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#define DMA_FLAG_MEM_TO_DEV 0x0002 |
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#define DMA_FLAG_TC_INTR 0x0100 |
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#define DMA_FLAG_MEM_INTR 0x0200 |
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#define DMA_FLAG_ADDR_INTR 0x0400 |
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typedef struct rc4030State |
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{ |
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uint32_t config; /* 0x0000: RC4030 config register */
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uint32_t revision; /* 0x0008: RC4030 Revision register */
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uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
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/* DMA */
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uint32_t dma_regs[8][4]; |
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uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
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uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
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/* cache */
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uint32_t cache_maint; /* 0x0030: Cache Maintenance */
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uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
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uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
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uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
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uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
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uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
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uint32_t nmi_interrupt; /* 0x0200: interrupt source */
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uint32_t offset210; |
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uint32_t nvram_protect; /* 0x0220: NV ram protect register */
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uint32_t rem_speed[16];
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uint32_t imr_jazz; /* Local bus int enable mask */
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uint32_t isr_jazz; /* Local bus int source */
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/* timer */
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QEMUTimer *periodic_timer; |
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uint32_t itr; /* Interval timer reload */
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qemu_irq timer_irq; |
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qemu_irq jazz_bus_irq; |
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} rc4030State; |
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static void set_next_tick(rc4030State *s) |
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{ |
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qemu_irq_lower(s->timer_irq); |
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uint32_t tm_hz; |
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tm_hz = 1000 / (s->itr + 1); |
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qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) + ticks_per_sec / tm_hz); |
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} |
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/* called for accesses to rc4030 */
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static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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rc4030State *s = opaque; |
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uint32_t val; |
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addr &= 0x3fff;
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switch (addr & ~0x3) { |
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/* Global config register */
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case 0x0000: |
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val = s->config; |
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break;
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/* Revision register */
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case 0x0008: |
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val = s->revision; |
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break;
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/* Invalid Address register */
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case 0x0010: |
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val = s->invalid_address_register; |
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break;
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/* DMA transl. table base */
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case 0x0018: |
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val = s->dma_tl_base; |
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break;
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/* DMA transl. table limit */
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case 0x0020: |
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val = s->dma_tl_limit; |
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break;
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/* Remote Failed Address */
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case 0x0038: |
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val = s->remote_failed_address; |
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break;
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/* Memory Failed Address */
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case 0x0040: |
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val = s->memory_failed_address; |
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break;
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/* I/O Cache Byte Mask */
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case 0x0058: |
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val = s->cache_bmask; |
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/* HACK */
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if (s->cache_bmask == (uint32_t)-1) |
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s->cache_bmask = 0;
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break;
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/* Remote Speed Registers */
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case 0x0070: |
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case 0x0078: |
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case 0x0080: |
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case 0x0088: |
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case 0x0090: |
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case 0x0098: |
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case 0x00a0: |
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case 0x00a8: |
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case 0x00b0: |
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case 0x00b8: |
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case 0x00c0: |
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case 0x00c8: |
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case 0x00d0: |
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case 0x00d8: |
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case 0x00e0: |
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case 0x00e8: |
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val = s->rem_speed[(addr - 0x0070) >> 3]; |
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break;
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/* DMA channel base address */
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case 0x0100: |
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case 0x0108: |
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case 0x0110: |
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case 0x0118: |
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case 0x0120: |
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case 0x0128: |
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case 0x0130: |
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case 0x0138: |
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case 0x0140: |
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case 0x0148: |
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case 0x0150: |
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case 0x0158: |
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case 0x0160: |
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case 0x0168: |
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case 0x0170: |
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case 0x0178: |
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case 0x0180: |
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case 0x0188: |
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case 0x0190: |
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case 0x0198: |
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case 0x01a0: |
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case 0x01a8: |
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case 0x01b0: |
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case 0x01b8: |
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case 0x01c0: |
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case 0x01c8: |
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case 0x01d0: |
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case 0x01d8: |
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case 0x01e0: |
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case 0x01e8: |
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case 0x01f0: |
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case 0x01f8: |
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{ |
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int entry = (addr - 0x0100) >> 5; |
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int idx = (addr & 0x1f) >> 3; |
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val = s->dma_regs[entry][idx]; |
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} |
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break;
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/* Interrupt source */
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case 0x0200: |
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val = s->nmi_interrupt; |
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break;
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/* Error type */
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case 0x0208: |
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val = 0;
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break;
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/* Offset 0x0210 */
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case 0x0210: |
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val = s->offset210; |
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break;
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/* NV ram protect register */
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case 0x0220: |
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val = s->nvram_protect; |
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break;
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/* Interval timer count */
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case 0x0230: |
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val = 0;
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qemu_irq_lower(s->timer_irq); |
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break;
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/* EISA interrupt */
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case 0x0238: |
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val = 7; /* FIXME: should be read from EISA controller */ |
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break;
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default:
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RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr); |
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val = 0;
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break;
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} |
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if ((addr & ~3) != 0x230) |
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DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr); |
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return val;
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} |
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static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t v = rc4030_readl(opaque, addr & ~0x3);
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if (addr & 0x2) |
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return v >> 16; |
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else
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return v & 0xffff; |
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} |
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static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t v = rc4030_readl(opaque, addr & ~0x3);
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return (v >> (8 * (addr & 0x3))) & 0xff; |
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} |
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static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{ |
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rc4030State *s = opaque; |
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addr &= 0x3fff;
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DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr); |
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switch (addr & ~0x3) { |
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/* Global config register */
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case 0x0000: |
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s->config = val; |
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break;
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/* DMA transl. table base */
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case 0x0018: |
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s->dma_tl_base = val; |
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break;
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/* DMA transl. table limit */
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case 0x0020: |
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s->dma_tl_limit = val; |
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break;
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/* DMA transl. table invalidated */
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case 0x0028: |
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break;
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/* Cache Maintenance */
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case 0x0030: |
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s->cache_maint = val; |
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break;
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/* I/O Cache Physical Tag */
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case 0x0048: |
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s->cache_ptag = val; |
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break;
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/* I/O Cache Logical Tag */
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case 0x0050: |
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s->cache_ltag = val; |
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break;
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/* I/O Cache Byte Mask */
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case 0x0058: |
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s->cache_bmask |= val; /* HACK */
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break;
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/* I/O Cache Buffer Window */
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case 0x0060: |
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/* HACK */
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if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) { |
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target_phys_addr_t dest = s->cache_ptag & ~0x1;
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dest += (s->cache_maint & 0x3) << 3; |
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cpu_physical_memory_rw(dest, (uint8_t*)&val, 4, 1); |
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} |
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break;
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/* Remote Speed Registers */
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case 0x0070: |
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case 0x0078: |
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case 0x0080: |
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case 0x0088: |
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case 0x0090: |
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case 0x0098: |
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case 0x00a0: |
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case 0x00a8: |
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case 0x00b0: |
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case 0x00b8: |
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case 0x00c0: |
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case 0x00c8: |
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case 0x00d0: |
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case 0x00d8: |
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case 0x00e0: |
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case 0x00e8: |
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s->rem_speed[(addr - 0x0070) >> 3] = val; |
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break;
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/* DMA channel base address */
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case 0x0100: |
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case 0x0108: |
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case 0x0110: |
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case 0x0118: |
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case 0x0120: |
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case 0x0128: |
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case 0x0130: |
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case 0x0138: |
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case 0x0140: |
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case 0x0148: |
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case 0x0150: |
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case 0x0158: |
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case 0x0160: |
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case 0x0168: |
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case 0x0170: |
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case 0x0178: |
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case 0x0180: |
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case 0x0188: |
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case 0x0190: |
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case 0x0198: |
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case 0x01a0: |
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case 0x01a8: |
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case 0x01b0: |
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case 0x01b8: |
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case 0x01c0: |
356 |
case 0x01c8: |
357 |
case 0x01d0: |
358 |
case 0x01d8: |
359 |
case 0x01e0: |
360 |
case 0x01e8: |
361 |
case 0x01f0: |
362 |
case 0x01f8: |
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{ |
364 |
int entry = (addr - 0x0100) >> 5; |
365 |
int idx = (addr & 0x1f) >> 3; |
366 |
s->dma_regs[entry][idx] = val; |
367 |
} |
368 |
break;
|
369 |
/* Offset 0x0210 */
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case 0x0210: |
371 |
s->offset210 = val; |
372 |
break;
|
373 |
/* Interval timer reload */
|
374 |
case 0x0228: |
375 |
s->itr = val; |
376 |
qemu_irq_lower(s->timer_irq); |
377 |
set_next_tick(s); |
378 |
break;
|
379 |
/* EISA interrupt */
|
380 |
case 0x0238: |
381 |
break;
|
382 |
default:
|
383 |
RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr); |
384 |
break;
|
385 |
} |
386 |
} |
387 |
|
388 |
static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
389 |
{ |
390 |
uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
|
391 |
|
392 |
if (addr & 0x2) |
393 |
val = (val << 16) | (old_val & 0x0000ffff); |
394 |
else
|
395 |
val = val | (old_val & 0xffff0000);
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rc4030_writel(opaque, addr & ~0x3, val);
|
397 |
} |
398 |
|
399 |
static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
400 |
{ |
401 |
uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
|
402 |
|
403 |
switch (addr & 3) { |
404 |
case 0: |
405 |
val = val | (old_val & 0xffffff00);
|
406 |
break;
|
407 |
case 1: |
408 |
val = (val << 8) | (old_val & 0xffff00ff); |
409 |
break;
|
410 |
case 2: |
411 |
val = (val << 16) | (old_val & 0xff00ffff); |
412 |
break;
|
413 |
case 3: |
414 |
val = (val << 24) | (old_val & 0x00ffffff); |
415 |
break;
|
416 |
} |
417 |
rc4030_writel(opaque, addr & ~0x3, val);
|
418 |
} |
419 |
|
420 |
static CPUReadMemoryFunc *rc4030_read[3] = { |
421 |
rc4030_readb, |
422 |
rc4030_readw, |
423 |
rc4030_readl, |
424 |
}; |
425 |
|
426 |
static CPUWriteMemoryFunc *rc4030_write[3] = { |
427 |
rc4030_writeb, |
428 |
rc4030_writew, |
429 |
rc4030_writel, |
430 |
}; |
431 |
|
432 |
static void update_jazz_irq(rc4030State *s) |
433 |
{ |
434 |
uint16_t pending; |
435 |
|
436 |
pending = s->isr_jazz & s->imr_jazz; |
437 |
|
438 |
#ifdef DEBUG_RC4030
|
439 |
if (s->isr_jazz != 0) { |
440 |
uint32_t irq = 0;
|
441 |
DPRINTF("pending irqs:");
|
442 |
for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) { |
443 |
if (s->isr_jazz & (1 << irq)) { |
444 |
printf(" %s", irq_names[irq]);
|
445 |
if (!(s->imr_jazz & (1 << irq))) { |
446 |
printf("(ignored)");
|
447 |
} |
448 |
} |
449 |
} |
450 |
printf("\n");
|
451 |
} |
452 |
#endif
|
453 |
|
454 |
if (pending != 0) |
455 |
qemu_irq_raise(s->jazz_bus_irq); |
456 |
else
|
457 |
qemu_irq_lower(s->jazz_bus_irq); |
458 |
} |
459 |
|
460 |
static void rc4030_irq_jazz_request(void *opaque, int irq, int level) |
461 |
{ |
462 |
rc4030State *s = opaque; |
463 |
|
464 |
if (level) {
|
465 |
s->isr_jazz |= 1 << irq;
|
466 |
} else {
|
467 |
s->isr_jazz &= ~(1 << irq);
|
468 |
} |
469 |
|
470 |
update_jazz_irq(s); |
471 |
} |
472 |
|
473 |
static void rc4030_periodic_timer(void *opaque) |
474 |
{ |
475 |
rc4030State *s = opaque; |
476 |
|
477 |
set_next_tick(s); |
478 |
qemu_irq_raise(s->timer_irq); |
479 |
} |
480 |
|
481 |
static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr) |
482 |
{ |
483 |
rc4030State *s = opaque; |
484 |
uint32_t val; |
485 |
uint32_t irq; |
486 |
addr &= 0xfff;
|
487 |
|
488 |
switch (addr) {
|
489 |
/* Local bus int source */
|
490 |
case 0x00: { |
491 |
uint32_t pending = s->isr_jazz & s->imr_jazz; |
492 |
val = 0;
|
493 |
irq = 0;
|
494 |
while (pending) {
|
495 |
if (pending & 1) { |
496 |
DPRINTF("returning irq %s\n", irq_names[irq]);
|
497 |
val = (irq + 1) << 2; |
498 |
break;
|
499 |
} |
500 |
irq++; |
501 |
pending >>= 1;
|
502 |
} |
503 |
break;
|
504 |
} |
505 |
/* Local bus int enable mask */
|
506 |
case 0x02: |
507 |
val = s->imr_jazz; |
508 |
break;
|
509 |
default:
|
510 |
RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr); |
511 |
val = 0;
|
512 |
} |
513 |
|
514 |
DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr); |
515 |
|
516 |
return val;
|
517 |
} |
518 |
|
519 |
static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr) |
520 |
{ |
521 |
uint32_t v; |
522 |
v = jazzio_readw(opaque, addr & ~0x1);
|
523 |
return (v >> (8 * (addr & 0x1))) & 0xff; |
524 |
} |
525 |
|
526 |
static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr) |
527 |
{ |
528 |
uint32_t v; |
529 |
v = jazzio_readw(opaque, addr); |
530 |
v |= jazzio_readw(opaque, addr + 2) << 16; |
531 |
return v;
|
532 |
} |
533 |
|
534 |
static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
535 |
{ |
536 |
rc4030State *s = opaque; |
537 |
addr &= 0xfff;
|
538 |
|
539 |
DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr); |
540 |
|
541 |
switch (addr) {
|
542 |
/* Local bus int enable mask */
|
543 |
case 0x02: |
544 |
s->imr_jazz = val; |
545 |
update_jazz_irq(s); |
546 |
break;
|
547 |
default:
|
548 |
RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr); |
549 |
break;
|
550 |
} |
551 |
} |
552 |
|
553 |
static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
554 |
{ |
555 |
uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
|
556 |
|
557 |
switch (addr & 1) { |
558 |
case 0: |
559 |
val = val | (old_val & 0xff00);
|
560 |
break;
|
561 |
case 1: |
562 |
val = (val << 8) | (old_val & 0x00ff); |
563 |
break;
|
564 |
} |
565 |
jazzio_writew(opaque, addr & ~0x1, val);
|
566 |
} |
567 |
|
568 |
static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
569 |
{ |
570 |
jazzio_writew(opaque, addr, val & 0xffff);
|
571 |
jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff); |
572 |
} |
573 |
|
574 |
static CPUReadMemoryFunc *jazzio_read[3] = { |
575 |
jazzio_readb, |
576 |
jazzio_readw, |
577 |
jazzio_readl, |
578 |
}; |
579 |
|
580 |
static CPUWriteMemoryFunc *jazzio_write[3] = { |
581 |
jazzio_writeb, |
582 |
jazzio_writew, |
583 |
jazzio_writel, |
584 |
}; |
585 |
|
586 |
static void rc4030_reset(void *opaque) |
587 |
{ |
588 |
rc4030State *s = opaque; |
589 |
int i;
|
590 |
|
591 |
s->config = 0x410; /* some boards seem to accept 0x104 too */ |
592 |
s->revision = 1;
|
593 |
s->invalid_address_register = 0;
|
594 |
|
595 |
memset(s->dma_regs, 0, sizeof(s->dma_regs)); |
596 |
s->dma_tl_base = s->dma_tl_limit = 0;
|
597 |
|
598 |
s->remote_failed_address = s->memory_failed_address = 0;
|
599 |
s->cache_maint = 0;
|
600 |
s->cache_ptag = s->cache_ltag = 0;
|
601 |
s->cache_bmask = 0;
|
602 |
|
603 |
s->offset210 = 0x18186;
|
604 |
s->nvram_protect = 7;
|
605 |
for (i = 0; i < 15; i++) |
606 |
s->rem_speed[i] = 7;
|
607 |
s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */ |
608 |
s->isr_jazz = 0;
|
609 |
|
610 |
s->itr = 0;
|
611 |
|
612 |
qemu_irq_lower(s->timer_irq); |
613 |
qemu_irq_lower(s->jazz_bus_irq); |
614 |
} |
615 |
|
616 |
static int rc4030_load(QEMUFile *f, void *opaque, int version_id) |
617 |
{ |
618 |
rc4030State* s = opaque; |
619 |
int i, j;
|
620 |
|
621 |
if (version_id != 2) |
622 |
return -EINVAL;
|
623 |
|
624 |
s->config = qemu_get_be32(f); |
625 |
s->invalid_address_register = qemu_get_be32(f); |
626 |
for (i = 0; i < 8; i++) |
627 |
for (j = 0; j < 4; j++) |
628 |
s->dma_regs[i][j] = qemu_get_be32(f); |
629 |
s->dma_tl_base = qemu_get_be32(f); |
630 |
s->dma_tl_limit = qemu_get_be32(f); |
631 |
s->cache_maint = qemu_get_be32(f); |
632 |
s->remote_failed_address = qemu_get_be32(f); |
633 |
s->memory_failed_address = qemu_get_be32(f); |
634 |
s->cache_ptag = qemu_get_be32(f); |
635 |
s->cache_ltag = qemu_get_be32(f); |
636 |
s->cache_bmask = qemu_get_be32(f); |
637 |
s->offset210 = qemu_get_be32(f); |
638 |
s->nvram_protect = qemu_get_be32(f); |
639 |
for (i = 0; i < 15; i++) |
640 |
s->rem_speed[i] = qemu_get_be32(f); |
641 |
s->imr_jazz = qemu_get_be32(f); |
642 |
s->isr_jazz = qemu_get_be32(f); |
643 |
s->itr = qemu_get_be32(f); |
644 |
|
645 |
set_next_tick(s); |
646 |
update_jazz_irq(s); |
647 |
|
648 |
return 0; |
649 |
} |
650 |
|
651 |
static void rc4030_save(QEMUFile *f, void *opaque) |
652 |
{ |
653 |
rc4030State* s = opaque; |
654 |
int i, j;
|
655 |
|
656 |
qemu_put_be32(f, s->config); |
657 |
qemu_put_be32(f, s->invalid_address_register); |
658 |
for (i = 0; i < 8; i++) |
659 |
for (j = 0; j < 4; j++) |
660 |
qemu_put_be32(f, s->dma_regs[i][j]); |
661 |
qemu_put_be32(f, s->dma_tl_base); |
662 |
qemu_put_be32(f, s->dma_tl_limit); |
663 |
qemu_put_be32(f, s->cache_maint); |
664 |
qemu_put_be32(f, s->remote_failed_address); |
665 |
qemu_put_be32(f, s->memory_failed_address); |
666 |
qemu_put_be32(f, s->cache_ptag); |
667 |
qemu_put_be32(f, s->cache_ltag); |
668 |
qemu_put_be32(f, s->cache_bmask); |
669 |
qemu_put_be32(f, s->offset210); |
670 |
qemu_put_be32(f, s->nvram_protect); |
671 |
for (i = 0; i < 15; i++) |
672 |
qemu_put_be32(f, s->rem_speed[i]); |
673 |
qemu_put_be32(f, s->imr_jazz); |
674 |
qemu_put_be32(f, s->isr_jazz); |
675 |
qemu_put_be32(f, s->itr); |
676 |
} |
677 |
|
678 |
void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write) |
679 |
{ |
680 |
rc4030State *s = opaque; |
681 |
target_phys_addr_t entry_addr; |
682 |
target_phys_addr_t phys_addr; |
683 |
dma_pagetable_entry entry; |
684 |
int index;
|
685 |
int ncpy, i;
|
686 |
|
687 |
i = 0;
|
688 |
for (;;) {
|
689 |
if (i == len) {
|
690 |
break;
|
691 |
} |
692 |
|
693 |
ncpy = DMA_PAGESIZE - (addr & (DMA_PAGESIZE - 1));
|
694 |
if (ncpy > len - i)
|
695 |
ncpy = len - i; |
696 |
|
697 |
/* Get DMA translation table entry */
|
698 |
index = addr / DMA_PAGESIZE; |
699 |
if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) { |
700 |
break;
|
701 |
} |
702 |
entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
|
703 |
/* XXX: not sure. should we really use only lowest bits? */
|
704 |
entry_addr &= 0x7fffffff;
|
705 |
cpu_physical_memory_rw(entry_addr, (uint8_t *)&entry, sizeof(entry), 0); |
706 |
|
707 |
/* Read/write data at right place */
|
708 |
phys_addr = entry.frame + (addr & (DMA_PAGESIZE - 1));
|
709 |
cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write); |
710 |
|
711 |
i += ncpy; |
712 |
addr += ncpy; |
713 |
} |
714 |
} |
715 |
|
716 |
static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write) |
717 |
{ |
718 |
rc4030State *s = opaque; |
719 |
target_phys_addr_t dma_addr; |
720 |
int dev_to_mem;
|
721 |
|
722 |
s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR); |
723 |
|
724 |
/* Check DMA channel consistency */
|
725 |
dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1; |
726 |
if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
|
727 |
(is_write != dev_to_mem)) { |
728 |
s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR; |
729 |
s->nmi_interrupt |= 1 << n;
|
730 |
return;
|
731 |
} |
732 |
|
733 |
/* Get start address and len */
|
734 |
if (len > s->dma_regs[n][DMA_REG_COUNT])
|
735 |
len = s->dma_regs[n][DMA_REG_COUNT]; |
736 |
dma_addr = s->dma_regs[n][DMA_REG_ADDRESS]; |
737 |
|
738 |
/* Read/write data at right place */
|
739 |
rc4030_dma_memory_rw(opaque, dma_addr, buf, len, is_write); |
740 |
|
741 |
s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR; |
742 |
s->dma_regs[n][DMA_REG_COUNT] -= len; |
743 |
|
744 |
#ifdef DEBUG_RC4030_DMA
|
745 |
{ |
746 |
int i, j;
|
747 |
printf("rc4030 dma: Copying %d bytes %s host %p\n",
|
748 |
len, is_write ? "from" : "to", buf); |
749 |
for (i = 0; i < len; i += 16) { |
750 |
int n = min(16, len - i); |
751 |
for (j = 0; j < n; j++) |
752 |
printf("%02x ", buf[i + j]);
|
753 |
while (j++ < 16) |
754 |
printf(" ");
|
755 |
printf("| ");
|
756 |
for (j = 0; j < n; j++) |
757 |
printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.'); |
758 |
printf("\n");
|
759 |
} |
760 |
} |
761 |
#endif
|
762 |
} |
763 |
|
764 |
struct rc4030DMAState {
|
765 |
void *opaque;
|
766 |
int n;
|
767 |
}; |
768 |
|
769 |
void rc4030_dma_read(void *dma, uint8_t *buf, int len) |
770 |
{ |
771 |
rc4030_dma s = dma; |
772 |
rc4030_do_dma(s->opaque, s->n, buf, len, 0);
|
773 |
} |
774 |
|
775 |
void rc4030_dma_write(void *dma, uint8_t *buf, int len) |
776 |
{ |
777 |
rc4030_dma s = dma; |
778 |
rc4030_do_dma(s->opaque, s->n, buf, len, 1);
|
779 |
} |
780 |
|
781 |
static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n) |
782 |
{ |
783 |
rc4030_dma *s; |
784 |
struct rc4030DMAState *p;
|
785 |
int i;
|
786 |
|
787 |
s = (rc4030_dma *)qemu_mallocz(sizeof(rc4030_dma) * n);
|
788 |
p = (struct rc4030DMAState *)qemu_mallocz(sizeof(struct rc4030DMAState) * n); |
789 |
for (i = 0; i < n; i++) { |
790 |
p->opaque = opaque; |
791 |
p->n = i; |
792 |
s[i] = p; |
793 |
p++; |
794 |
} |
795 |
return s;
|
796 |
} |
797 |
|
798 |
void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
|
799 |
qemu_irq **irqs, rc4030_dma **dmas) |
800 |
{ |
801 |
rc4030State *s; |
802 |
int s_chipset, s_jazzio;
|
803 |
|
804 |
s = qemu_mallocz(sizeof(rc4030State));
|
805 |
|
806 |
*irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
|
807 |
*dmas = rc4030_allocate_dmas(s, 4);
|
808 |
|
809 |
s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s); |
810 |
s->timer_irq = timer; |
811 |
s->jazz_bus_irq = jazz_bus; |
812 |
|
813 |
qemu_register_reset(rc4030_reset, s); |
814 |
register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s); |
815 |
rc4030_reset(s); |
816 |
|
817 |
s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s);
|
818 |
cpu_register_physical_memory(0x80000000, 0x300, s_chipset); |
819 |
s_jazzio = cpu_register_io_memory(0, jazzio_read, jazzio_write, s);
|
820 |
cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio); |
821 |
|
822 |
return s;
|
823 |
} |