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1 | 049f7adb | Michael S. Tsirkin | #include "rwhandler.h" |
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2 | 049f7adb | Michael S. Tsirkin | #include "ioport.h" |
3 | 049f7adb | Michael S. Tsirkin | #include "cpu-all.h" |
4 | 049f7adb | Michael S. Tsirkin | |
5 | 049f7adb | Michael S. Tsirkin | #define RWHANDLER_WRITE(name, len, type) \
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6 | 049f7adb | Michael S. Tsirkin | static void name(void *opaque, type addr, uint32_t value) \ |
7 | 049f7adb | Michael S. Tsirkin | {\ |
8 | 049f7adb | Michael S. Tsirkin | struct ReadWriteHandler *handler = opaque;\
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9 | 049f7adb | Michael S. Tsirkin | handler->write(handler, addr, value, len);\ |
10 | 049f7adb | Michael S. Tsirkin | } |
11 | 049f7adb | Michael S. Tsirkin | |
12 | 049f7adb | Michael S. Tsirkin | #define RWHANDLER_READ(name, len, type) \
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13 | 049f7adb | Michael S. Tsirkin | static uint32_t name(void *opaque, type addr) \ |
14 | 049f7adb | Michael S. Tsirkin | { \ |
15 | 049f7adb | Michael S. Tsirkin | struct ReadWriteHandler *handler = opaque; \
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16 | 049f7adb | Michael S. Tsirkin | return handler->read(handler, addr, len); \
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17 | 049f7adb | Michael S. Tsirkin | } |
18 | 049f7adb | Michael S. Tsirkin | |
19 | 049f7adb | Michael S. Tsirkin | RWHANDLER_WRITE(cpu_io_memory_simple_writeb, 1, target_phys_addr_t);
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20 | 049f7adb | Michael S. Tsirkin | RWHANDLER_READ(cpu_io_memory_simple_readb, 1, target_phys_addr_t);
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21 | 049f7adb | Michael S. Tsirkin | RWHANDLER_WRITE(cpu_io_memory_simple_writew, 2, target_phys_addr_t);
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22 | 049f7adb | Michael S. Tsirkin | RWHANDLER_READ(cpu_io_memory_simple_readw, 2, target_phys_addr_t);
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23 | 049f7adb | Michael S. Tsirkin | RWHANDLER_WRITE(cpu_io_memory_simple_writel, 4, target_phys_addr_t);
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24 | 049f7adb | Michael S. Tsirkin | RWHANDLER_READ(cpu_io_memory_simple_readl, 4, target_phys_addr_t);
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25 | 049f7adb | Michael S. Tsirkin | |
26 | 049f7adb | Michael S. Tsirkin | static CPUWriteMemoryFunc * const cpu_io_memory_simple_write[] = { |
27 | 049f7adb | Michael S. Tsirkin | &cpu_io_memory_simple_writeb, |
28 | 049f7adb | Michael S. Tsirkin | &cpu_io_memory_simple_writew, |
29 | 049f7adb | Michael S. Tsirkin | &cpu_io_memory_simple_writel, |
30 | 049f7adb | Michael S. Tsirkin | }; |
31 | 049f7adb | Michael S. Tsirkin | |
32 | 049f7adb | Michael S. Tsirkin | static CPUReadMemoryFunc * const cpu_io_memory_simple_read[] = { |
33 | 049f7adb | Michael S. Tsirkin | &cpu_io_memory_simple_readb, |
34 | 049f7adb | Michael S. Tsirkin | &cpu_io_memory_simple_readw, |
35 | 049f7adb | Michael S. Tsirkin | &cpu_io_memory_simple_readl, |
36 | 049f7adb | Michael S. Tsirkin | }; |
37 | 049f7adb | Michael S. Tsirkin | |
38 | 049f7adb | Michael S. Tsirkin | int cpu_register_io_memory_simple(struct ReadWriteHandler *handler) |
39 | 049f7adb | Michael S. Tsirkin | { |
40 | 049f7adb | Michael S. Tsirkin | if (!handler->read || !handler->write) {
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41 | 049f7adb | Michael S. Tsirkin | return -1; |
42 | 049f7adb | Michael S. Tsirkin | } |
43 | 049f7adb | Michael S. Tsirkin | return cpu_register_io_memory(cpu_io_memory_simple_read,
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44 | 049f7adb | Michael S. Tsirkin | cpu_io_memory_simple_write, |
45 | 049f7adb | Michael S. Tsirkin | handler); |
46 | 049f7adb | Michael S. Tsirkin | } |
47 | 049f7adb | Michael S. Tsirkin | |
48 | 049f7adb | Michael S. Tsirkin | RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t);
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49 | 049f7adb | Michael S. Tsirkin | RWHANDLER_READ(ioport_simple_readb, 1, uint32_t);
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50 | 049f7adb | Michael S. Tsirkin | RWHANDLER_WRITE(ioport_simple_writew, 2, uint32_t);
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51 | 049f7adb | Michael S. Tsirkin | RWHANDLER_READ(ioport_simple_readw, 2, uint32_t);
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52 | 049f7adb | Michael S. Tsirkin | RWHANDLER_WRITE(ioport_simple_writel, 4, uint32_t);
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53 | 049f7adb | Michael S. Tsirkin | RWHANDLER_READ(ioport_simple_readl, 4, uint32_t);
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54 | 049f7adb | Michael S. Tsirkin | |
55 | 049f7adb | Michael S. Tsirkin | int register_ioport_simple(ReadWriteHandler* handler,
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56 | 049f7adb | Michael S. Tsirkin | pio_addr_t start, int length, int size) |
57 | 049f7adb | Michael S. Tsirkin | { |
58 | 049f7adb | Michael S. Tsirkin | IOPortWriteFunc *write; |
59 | 049f7adb | Michael S. Tsirkin | IOPortReadFunc *read; |
60 | 049f7adb | Michael S. Tsirkin | int r;
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61 | 049f7adb | Michael S. Tsirkin | switch (size) {
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62 | 049f7adb | Michael S. Tsirkin | case 1: |
63 | 049f7adb | Michael S. Tsirkin | write = ioport_simple_writeb; |
64 | 049f7adb | Michael S. Tsirkin | read = ioport_simple_readb; |
65 | 049f7adb | Michael S. Tsirkin | break;
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66 | 049f7adb | Michael S. Tsirkin | case 2: |
67 | 049f7adb | Michael S. Tsirkin | write = ioport_simple_writew; |
68 | 049f7adb | Michael S. Tsirkin | read = ioport_simple_readw; |
69 | 049f7adb | Michael S. Tsirkin | break;
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70 | 049f7adb | Michael S. Tsirkin | default:
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71 | 049f7adb | Michael S. Tsirkin | write = ioport_simple_writel; |
72 | 049f7adb | Michael S. Tsirkin | read = ioport_simple_readl; |
73 | 049f7adb | Michael S. Tsirkin | } |
74 | 049f7adb | Michael S. Tsirkin | if (handler->write) {
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75 | 049f7adb | Michael S. Tsirkin | r = register_ioport_write(start, length, size, write, handler); |
76 | 049f7adb | Michael S. Tsirkin | if (r < 0) { |
77 | 049f7adb | Michael S. Tsirkin | return r;
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78 | 049f7adb | Michael S. Tsirkin | } |
79 | 049f7adb | Michael S. Tsirkin | } |
80 | 049f7adb | Michael S. Tsirkin | if (handler->read) {
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81 | 049f7adb | Michael S. Tsirkin | r = register_ioport_read(start, length, size, read, handler); |
82 | 049f7adb | Michael S. Tsirkin | if (r < 0) { |
83 | 049f7adb | Michael S. Tsirkin | return r;
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84 | 049f7adb | Michael S. Tsirkin | } |
85 | 049f7adb | Michael S. Tsirkin | } |
86 | 049f7adb | Michael S. Tsirkin | return 0; |
87 | 049f7adb | Michael S. Tsirkin | } |