target-mips: Fix compilation
TCGv t1 needs tcg_temp_free instead of tcg_temp_free_i32.
Cc: Nathan Froyd <froydnj@codesourcery.com>Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: add microMIPS exception handler support
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exceptionhandlers. The ISA mode is selectable via a user-writable CP0.Config3flag.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
linux-user: honor low bit of entry PC for MIPS
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
hw: honor low bit in mipssim machine
tcg: get rid of DEF2 in tcg-opc.h
Now that tcg-opc.h is only used in TCG code, get rid of DEF2 intcg-opc.h.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: define constants for magic numbers
Add FMT_* constants for the floating-point format field in opcodes andtweak a few places to use them. Add enums for various invocations ofFOP and tweak gen_farith and its lone caller accordingly.
target-mips: move FP FMT comments closer to the definitions
target-mips: refactor c{, abs}.cond.fmt insns
Move all knowledge about coprocessor-checking and register numberinginto the gen_cmp* helper functions.
target-mips: mips16 cleanups
Change code handling mips16-specific branches to use ISA-neutral specialopcodes. Since there are several places where the delay slotrequirements for microMIPS branches differ from mips16 branches, usingopcodes is easier than checking hflags, then checking mips16...
target-mips: microMIPS ASE support
Add instruction decoding for the microMIPS ASE. All we do is decode andthen forward to the existing gen_* routines.
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