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tcg: Add muluh and mulsh opcodes
Use them in places where mulu2 and muls2 are used.Optimize mulx2 with dead low part to mulxh.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Change flush_icache_range arguments to uintptr_t
tcg-arm: Make use of conditional availability of opcodes for divide
We can now detect and use divide instructions at runtime, rather thanhaving to restrict their availability to compile-time.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Don't implement rem
tcg: Split rem requirement from div requirement
There are several hosts with only a "div" insn. Remainder is computedmanually from the quotient and inputs. We can do this generically.
tcg-arm: Implement deposit for armv7
We have BFI and BFC available for implementing it.
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Implement division instructions
An armv7 extension implements division, present on Cortex A15.
tcg-arm: Use bic to implement and with constant
This greatly improves the code we can produce for depositwithout armv7 support.
tcg-arm: Implement muls2_i32
We even had the encoding of smull already handy...
Cc: Andrzej Zaborowski <balrogg@gmail.com>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg: Add signed multiword multiplication operations
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
janitor: add guards to headers
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Merge branch 'linux-user-for-upstream' of git://git.linaro.org/people/rikuvoipio/qemu
tcg/arm: Implement movcond_i32
Implement movcond_i32 for ARM, as the sequence mov dst, v2 (implicitly done by the tcg common code) cmp c1, c2 movCC dst, v1
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Remove TCG_TARGET_HAS_GUEST_BASE define
GUEST_BASE support is now supported by all TCG backends, and isnow mandatory. Drop the now-pointless TCG_TARGET_HAS_GUEST_BASEdefine (set by every backend) and the error if it is unset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
tcg: Introduce movcond
Implemented with setcond if the target does not providethe optional opcode.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Remove unused CONFIG_TCG_PASS_AREG0 and dead code
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.
Remove dyngen-exec.h and all references to it. Although included byhw/spapr_hcall.c, it does not seem to use it....
w64: Change data type of parameters for flush_icache_range
The TCG targets i386 and tci needed a change of the functionprototype for w64.
This change is currently not needed for the other TCG targets,but it can be applied to avoid code differences.
Cc: Blue Swirl <blauwirbel@gmail.com>...
tcg/arm: Use r6 as TCG_AREG0 to avoid clash with Thumb framepointer
On ARM, in Thumb mode r7 is used for the framepointer; this meantthat we would fail to compile in debug mode because we were using r7for TCG_AREG0. Shift to r6 instead to avoid this clash....
tcg: Standardize on TCGReg as the enum for hard registers
Most targets did not name the enum; tci used TCGRegister.
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Stefan Weil <sw@weilnetz.de>...
tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.h
It is now declared for all tcg targets in tcg.h,so the tcg target specific declarations are redundant.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg: Always define all of the TCGOpcode enum members.
By always defining these symbols, we can eliminate a lot of ifdefs.
To allow this to be checked reliably, the semantics of theTCG_TARGET_HAS_* macros must be changed from def/undef to true/false.This allows even more ifdefs to be removed, converting them into...
tcg/arm: add rotation ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: add ext16u op
Add an ext16u op, either using the uxth instruction on ARMv6+ or twoshifts on previous ARM versions. In both cases the result use the samenumber or less instructions than the pure TCG version.
Also move all sign extension code to separate functions, so that they...
tcg/arm: add bswap ops
Add an bswap16 and bswap32 ops, either using the rev and rev16instructions on ARMv6+ or shifts and logical operations on previousARM versions. In both cases the result use less instructions thanthe pure TCG version.
These ops are also needed by the qemu_ld/st functions....
tcg/arm: explicitely list clobbered/reserved regs
Instead of writing very compact code, declare all registers that areclobbered or reserved one by one. This makes the code easier to read.
Also declare all the 16 registers to TCG, and mark pc as reserved....
tcg/arm: align 64-bit arguments in function calls
As specified by the "Procedure Call Standard for the ARM Architecture".
tcg: Allow target-specific implementation of NOR.
tcg: Allow target-specific implementation of NAND.
tcg: Allow target-specific implementation of EQV.
remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: use helpers for divu/remu
tcg: add div/rem 32-bit helpers
Some targets like ARM would benefit to use 32-bit helpers fordiv/rem/divu/remu.
Create a #define for div2 so that targets can select betweendiv, div2 and helper implementation. Use the helper version if noneof the #define are present....
tcg/arm: implement andc op
tcg/arm: merge the two sets of #define for optional ops
tcg: Add comments for all optional instructions not implemented.
ARM back-end: Add TCG not
this patch:
- implements TCG not.
Laurent
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
this patch improves the ARM back-end in the following way:
- use movw/movt to load immediate values for ARMv7-A- implement add/sub/and/or/xor with immediate (only 8-bit)
Userspace guest address offsetting
Re-implement GUEST_BASE support.Offset guest ddress space by default if the guest binary containsregions below the host mmap_min_addr.Implement support for i386, x86-64 and arm hosts.
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>...
ARM host fixes
Minor TCG cleanups and warning fixes for ARM hosts.
Signed-off-by: Paul Brook <paul@codesourcery.com>
tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
Prune unused TCG_AREGs
Remove definitions for TCG_AREGs corresponding to AREG definitionsremoved in r6778.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
Use libgcc __clear_cache to clean icache, when available.
Calling the clear cache syscall directly generates an illegal instructionon some (armv4) kernels.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5843 c046a42c-6fe2-441c-8c8c-71466251a162
Define TCG_TARGET_CALL_STACK_OFFSET on arm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4541 c046a42c-6fe2-441c-8c8c-71466251a162
Implement neg_i32, clean-up.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162
ARM host support for TCG targets.
Updated from previous version to use the tcg prologue/epilogue mechanism, may be slower than direct call.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4500 c046a42c-6fe2-441c-8c8c-71466251a162