Archipelago » qemu

/*

 *  i386 CPUID helper functions

 *

 *  Copyright (c) 2003 Fabrice Bellard

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "sysemu/kvm.h"

#include "sysemu/cpus.h"

#include "topology.h"

#include "qemu/option.h"

#include "qemu/config-file.h"

#include "qapi/qmp/qerror.h"

#include "qapi-types.h"

#include "qapi-visit.h"

#include "qapi/visitor.h"

#include "sysemu/arch_init.h"

#include "hw/hw.h"

#if defined(CONFIG_KVM)

#include <linux/kvm_para.h>

#endif

#include "sysemu/sysemu.h"

#include "hw/qdev-properties.h"

#include "hw/cpu/icc_bus.h"

#ifndef CONFIG_USER_ONLY

#include "hw/xen/xen.h"

#include "hw/i386/apic_internal.h"

#endif

/* Cache topology CPUID constants: */

/* CPUID Leaf 2 Descriptors */

#define CPUID_2_L1D_32KB_8WAY_64B 0x2c

#define CPUID_2_L1I_32KB_8WAY_64B 0x30

#define CPUID_2_L2_2MB_8WAY_64B   0x7d

/* CPUID Leaf 4 constants: */

/* EAX: */

#define CPUID_4_TYPE_DCACHE  1

#define CPUID_4_TYPE_ICACHE  2

#define CPUID_4_TYPE_UNIFIED 3

#define CPUID_4_LEVEL(l)          ((l) << 5)

#define CPUID_4_SELF_INIT_LEVEL (1 << 8)

#define CPUID_4_FULLY_ASSOC     (1 << 9)

/* EDX: */

#define CPUID_4_NO_INVD_SHARING (1 << 0)

#define CPUID_4_INCLUSIVE       (1 << 1)

#define CPUID_4_COMPLEX_IDX     (1 << 2)

#define ASSOC_FULL 0xFF

/* AMD associativity encoding used on CPUID Leaf 0x80000006: */

#define AMD_ENC_ASSOC(a) (a <=   1 ? a   : \

                          a ==   2 ? 0x2 : \

                          a ==   4 ? 0x4 : \

                          a ==   8 ? 0x6 : \

                          a ==  16 ? 0x8 : \

                          a ==  32 ? 0xA : \

                          a ==  48 ? 0xB : \

                          a ==  64 ? 0xC : \

                          a ==  96 ? 0xD : \

                          a == 128 ? 0xE : \

                          a == ASSOC_FULL ? 0xF : \

                          0 /* invalid value */)

/* Definitions of the hardcoded cache entries we expose: */

/* L1 data cache: */

#define L1D_LINE_SIZE         64

#define L1D_ASSOCIATIVITY      8

#define L1D_SETS              64

#define L1D_PARTITIONS         1

/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */

#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B

/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */

#define L1D_LINES_PER_TAG      1

#define L1D_SIZE_KB_AMD       64

#define L1D_ASSOCIATIVITY_AMD  2

/* L1 instruction cache: */

#define L1I_LINE_SIZE         64

#define L1I_ASSOCIATIVITY      8

#define L1I_SETS              64

#define L1I_PARTITIONS         1

/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */

#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B

/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */

#define L1I_LINES_PER_TAG      1

#define L1I_SIZE_KB_AMD       64

#define L1I_ASSOCIATIVITY_AMD  2

/* Level 2 unified cache: */

#define L2_LINE_SIZE          64

#define L2_ASSOCIATIVITY      16

#define L2_SETS             4096

#define L2_PARTITIONS          1

/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */

/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */

#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B

/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */

#define L2_LINES_PER_TAG       1

#define L2_SIZE_KB_AMD       512

/* No L3 cache: */

#define L3_SIZE_KB             0 /* disabled */

#define L3_ASSOCIATIVITY       0 /* disabled */

#define L3_LINES_PER_TAG       0 /* disabled */

#define L3_LINE_SIZE           0 /* disabled */

/* TLB definitions: */

#define L1_DTLB_2M_ASSOC       1

#define L1_DTLB_2M_ENTRIES   255

#define L1_DTLB_4K_ASSOC       1

#define L1_DTLB_4K_ENTRIES   255

#define L1_ITLB_2M_ASSOC       1

#define L1_ITLB_2M_ENTRIES   255

#define L1_ITLB_4K_ASSOC       1

#define L1_ITLB_4K_ENTRIES   255

#define L2_DTLB_2M_ASSOC       0 /* disabled */

#define L2_DTLB_2M_ENTRIES     0 /* disabled */

#define L2_DTLB_4K_ASSOC       4

#define L2_DTLB_4K_ENTRIES   512

#define L2_ITLB_2M_ASSOC       0 /* disabled */

#define L2_ITLB_2M_ENTRIES     0 /* disabled */

#define L2_ITLB_4K_ASSOC       4

#define L2_ITLB_4K_ENTRIES   512

static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,

                                     uint32_t vendor2, uint32_t vendor3)

{

    int i;

    for (i = 0; i < 4; i++) {

        dst[i] = vendor1 >> (8 * i);

        dst[i + 4] = vendor2 >> (8 * i);

        dst[i + 8] = vendor3 >> (8 * i);

    }

    dst[CPUID_VENDOR_SZ] = '\0';

}

/* feature flags taken from "Intel Processor Identification and the CPUID

 * Instruction" and AMD's "CPUID Specification".  In cases of disagreement

 * between feature naming conventions, aliases may be added.

 */

static const char *feature_name[] = {

    "fpu", "vme", "de", "pse",

    "tsc", "msr", "pae", "mce",

    "cx8", "apic", NULL, "sep",

    "mtrr", "pge", "mca", "cmov",

    "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,

    NULL, "ds" /* Intel dts */, "acpi", "mmx",

    "fxsr", "sse", "sse2", "ss",

    "ht" /* Intel htt */, "tm", "ia64", "pbe",

};

static const char *ext_feature_name[] = {

    "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",

    "ds_cpl", "vmx", "smx", "est",

    "tm2", "ssse3", "cid", NULL,

    "fma", "cx16", "xtpr", "pdcm",

    NULL, "pcid", "dca", "sse4.1|sse4_1",

    "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",

    "tsc-deadline", "aes", "xsave", "osxsave",

    "avx", "f16c", "rdrand", "hypervisor",

};

/* Feature names that are already defined on feature_name[] but are set on

 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on

 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features

 * if and only if CPU vendor is AMD.

 */

static const char *ext2_feature_name[] = {

    NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,

    NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,

    NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",

    NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,

    NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,

    "nx|xd", NULL, "mmxext", NULL /* mmx */,

    NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",

    NULL, "lm|i64", "3dnowext", "3dnow",

};

static const char *ext3_feature_name[] = {

    "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,

    "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",

    "3dnowprefetch", "osvw", "ibs", "xop",

    "skinit", "wdt", NULL, "lwp",

    "fma4", "tce", NULL, "nodeid_msr",

    NULL, "tbm", "topoext", "perfctr_core",

    "perfctr_nb", NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

};

static const char *ext4_feature_name[] = {

    NULL, NULL, "xstore", "xstore-en",

    NULL, NULL, "xcrypt", "xcrypt-en",

    "ace2", "ace2-en", "phe", "phe-en",

    "pmm", "pmm-en", NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

};

static const char *kvm_feature_name[] = {

    "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",

    "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

};

static const char *svm_feature_name[] = {

    "npt", "lbrv", "svm_lock", "nrip_save",

    "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",

    NULL, NULL, "pause_filter", NULL,

    "pfthreshold", NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

};

static const char *cpuid_7_0_ebx_feature_name[] = {

    "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",

    "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,

    NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,

    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

};

typedef struct FeatureWordInfo {

    const char **feat_names;

    uint32_t cpuid_eax;   /* Input EAX for CPUID */

    bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */

    uint32_t cpuid_ecx;   /* Input ECX value for CPUID */

    int cpuid_reg;        /* output register (R_* constant) */

} FeatureWordInfo;

static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {

    [FEAT_1_EDX] = {

        .feat_names = feature_name,

        .cpuid_eax = 1, .cpuid_reg = R_EDX,

    },

    [FEAT_1_ECX] = {

        .feat_names = ext_feature_name,

        .cpuid_eax = 1, .cpuid_reg = R_ECX,

    },

    [FEAT_8000_0001_EDX] = {

        .feat_names = ext2_feature_name,

        .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,

    },

    [FEAT_8000_0001_ECX] = {

        .feat_names = ext3_feature_name,

        .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,

    },

    [FEAT_C000_0001_EDX] = {

        .feat_names = ext4_feature_name,

        .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,

    },

    [FEAT_KVM] = {

        .feat_names = kvm_feature_name,

        .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,

    },

    [FEAT_SVM] = {

        .feat_names = svm_feature_name,

        .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,

    },

    [FEAT_7_0_EBX] = {

        .feat_names = cpuid_7_0_ebx_feature_name,

        .cpuid_eax = 7,

        .cpuid_needs_ecx = true, .cpuid_ecx = 0,

        .cpuid_reg = R_EBX,

    },

};

typedef struct X86RegisterInfo32 {

    /* Name of register */

    const char *name;

    /* QAPI enum value register */

    X86CPURegister32 qapi_enum;

} X86RegisterInfo32;

#define REGISTER(reg) \

    [R_##reg] = { .name = #reg, .qapi_enum = X86_C_P_U_REGISTER32_##reg }

X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {

    REGISTER(EAX),

    REGISTER(ECX),

    REGISTER(EDX),

    REGISTER(EBX),

    REGISTER(ESP),

    REGISTER(EBP),

    REGISTER(ESI),

    REGISTER(EDI),

};

#undef REGISTER

typedef struct ExtSaveArea {

    uint32_t feature, bits;

    uint32_t offset, size;

} ExtSaveArea;

static const ExtSaveArea ext_save_areas[] = {

    [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,

            .offset = 0x240, .size = 0x100 },

};

const char *get_register_name_32(unsigned int reg)

{

    if (reg >= CPU_NB_REGS32) {

        return NULL;

    }

    return x86_reg_info_32[reg].name;

}

/* collects per-function cpuid data

 */

typedef struct model_features_t {

    uint32_t *guest_feat;

    uint32_t *host_feat;

    FeatureWord feat_word;

} model_features_t;

int check_cpuid = 0;

int enforce_cpuid = 0;

static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |

        (1 << KVM_FEATURE_NOP_IO_DELAY) |

        (1 << KVM_FEATURE_CLOCKSOURCE2) |

        (1 << KVM_FEATURE_ASYNC_PF) |

        (1 << KVM_FEATURE_STEAL_TIME) |

        (1 << KVM_FEATURE_PV_EOI) |

        (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);

void disable_kvm_pv_eoi(void)

{

    kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);

}

void host_cpuid(uint32_t function, uint32_t count,

                uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)

{

#if defined(CONFIG_KVM)

    uint32_t vec[4];

#ifdef __x86_64__

    asm volatile("cpuid"

                 : "=a"(vec[0]), "=b"(vec[1]),

                   "=c"(vec[2]), "=d"(vec[3])

                 : "0"(function), "c"(count) : "cc");

#else

    asm volatile("pusha \n\t"

                 "cpuid \n\t"

                 "mov %%eax, 0(%2) \n\t"

                 "mov %%ebx, 4(%2) \n\t"

                 "mov %%ecx, 8(%2) \n\t"

                 "mov %%edx, 12(%2) \n\t"

                 "popa"

                 : : "a"(function), "c"(count), "S"(vec)

                 : "memory", "cc");

#endif

    if (eax)

        *eax = vec[0];

    if (ebx)

        *ebx = vec[1];

    if (ecx)

        *ecx = vec[2];

    if (edx)

        *edx = vec[3];

#endif

}

#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))

/* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of

 * a substring.  ex if !NULL points to the first char after a substring,

 * otherwise the string is assumed to sized by a terminating nul.

 * Return lexical ordering of *s1:*s2.

 */

static int sstrcmp(const char *s1, const char *e1, const char *s2,

    const char *e2)

{

    for (;;) {

        if (!*s1 || !*s2 || *s1 != *s2)

            return (*s1 - *s2);

        ++s1, ++s2;

        if (s1 == e1 && s2 == e2)

            return (0);

        else if (s1 == e1)

            return (*s2);

        else if (s2 == e2)

            return (*s1);

    }

}

/* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple

 * '|' delimited (possibly empty) strings in which case search for a match

 * within the alternatives proceeds left to right.  Return 0 for success,

 * non-zero otherwise.

 */

static int altcmp(const char *s, const char *e, const char *altstr)

{

    const char *p, *q;

    for (q = p = altstr; ; ) {

        while (*p && *p != '|')

            ++p;

        if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))

            return (0);

        if (!*p)

            return (1);

        else

            q = ++p;

    }

}

/* search featureset for flag *[s..e), if found set corresponding bit in

 * *pval and return true, otherwise return false

 */

static bool lookup_feature(uint32_t *pval, const char *s, const char *e,

                           const char **featureset)

{

    uint32_t mask;

    const char **ppc;

    bool found = false;

    for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {

        if (*ppc && !altcmp(s, e, *ppc)) {

            *pval |= mask;

            found = true;

        }

    }

    return found;

}

static void add_flagname_to_bitmaps(const char *flagname,

                                    FeatureWordArray words)

{

    FeatureWord w;

    for (w = 0; w < FEATURE_WORDS; w++) {

        FeatureWordInfo *wi = &feature_word_info[w];

        if (wi->feat_names &&

            lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {

            break;

        }

    }

    if (w == FEATURE_WORDS) {

        fprintf(stderr, "CPU feature %s not found\n", flagname);

    }

}

typedef struct x86_def_t {

    const char *name;

    uint32_t level;

    uint32_t xlevel;

    uint32_t xlevel2;

    /* vendor is zero-terminated, 12 character ASCII string */

    char vendor[CPUID_VENDOR_SZ + 1];

    int family;

    int model;

    int stepping;

    FeatureWordArray features;

    char model_id[48];

    bool cache_info_passthrough;

} x86_def_t;

#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)

#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \

          CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)

#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \

          CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \

          CPUID_PSE36 | CPUID_FXSR)

#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)

#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \

          CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \

          CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \

          CPUID_PAE | CPUID_SEP | CPUID_APIC)

#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \

          CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \

          CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \

          CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \

          CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)

          /* partly implemented:

          CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)

          CPUID_PSE36 (needed for Solaris) */

          /* missing:

          CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */

#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \

          CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \

          CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \

          CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)

          /* missing:

          CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,

          CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,

          CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,

          CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,

          CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,

          CPUID_EXT_RDRAND */

#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \

          CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \

          CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)

          /* missing:

          CPUID_EXT2_PDPE1GB */

#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \

          CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)

#define TCG_SVM_FEATURES 0

#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \

          CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)

          /* missing:

          CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,

          CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,

          CPUID_7_0_EBX_RDSEED */

/* built-in CPU model definitions

 */

static x86_def_t builtin_x86_defs[] = {

    {

        .name = "qemu64",

        .level = 4,

        .vendor = CPUID_VENDOR_AMD,

        .family = 6,

        .model = 6,

        .stepping = 3,

        .features[FEAT_1_EDX] =

            PPRO_FEATURES |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |

            CPUID_PSE36,

        .features[FEAT_1_ECX] =

            CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,

        .features[FEAT_8000_0001_EDX] =

            (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |

            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |

            CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,

        .xlevel = 0x8000000A,

    },

    {

        .name = "phenom",

        .level = 5,

        .vendor = CPUID_VENDOR_AMD,

        .family = 16,

        .model = 2,

        .stepping = 3,

        .features[FEAT_1_EDX] =

            PPRO_FEATURES |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |

            CPUID_PSE36 | CPUID_VME | CPUID_HT,

        .features[FEAT_1_ECX] =

            CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |

            CPUID_EXT_POPCNT,

        .features[FEAT_8000_0001_EDX] =

            (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |

            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |

            CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |

            CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,

        /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,

                    CPUID_EXT3_CR8LEG,

                    CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,

                    CPUID_EXT3_OSVW, CPUID_EXT3_IBS */

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |

            CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,

        .features[FEAT_SVM] =

            CPUID_SVM_NPT | CPUID_SVM_LBRV,

        .xlevel = 0x8000001A,

        .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"

    },

    {

        .name = "core2duo",

        .level = 10,

        .vendor = CPUID_VENDOR_INTEL,

        .family = 6,

        .model = 15,

        .stepping = 11,

        .features[FEAT_1_EDX] =

            PPRO_FEATURES |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |

            CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |

            CPUID_HT | CPUID_TM | CPUID_PBE,

        .features[FEAT_1_ECX] =

            CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |

            CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |

            CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,

        .features[FEAT_8000_0001_EDX] =

            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_LAHF_LM,

        .xlevel = 0x80000008,

        .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",

    },

    {

        .name = "kvm64",

        .level = 5,

        .vendor = CPUID_VENDOR_INTEL,

        .family = 15,

        .model = 6,

        .stepping = 1,

        /* Missing: CPUID_VME, CPUID_HT */

        .features[FEAT_1_EDX] =

            PPRO_FEATURES |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |

            CPUID_PSE36,

        /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */

        .features[FEAT_1_ECX] =

            CPUID_EXT_SSE3 | CPUID_EXT_CX16,

        /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */

        .features[FEAT_8000_0001_EDX] =

            (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |

            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,

        /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,

                    CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,

                    CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,

                    CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */

        .features[FEAT_8000_0001_ECX] =

            0,

        .xlevel = 0x80000008,

        .model_id = "Common KVM processor"

    },

    {

        .name = "qemu32",

        .level = 4,

        .vendor = CPUID_VENDOR_INTEL,

        .family = 6,

        .model = 6,

        .stepping = 3,

        .features[FEAT_1_EDX] =

            PPRO_FEATURES,

        .features[FEAT_1_ECX] =

            CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,

        .xlevel = 0x80000004,

    },

    {

        .name = "kvm32",

        .level = 5,

        .vendor = CPUID_VENDOR_INTEL,

        .family = 15,

        .model = 6,

        .stepping = 1,

        .features[FEAT_1_EDX] =

            PPRO_FEATURES |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,

        .features[FEAT_1_ECX] =

            CPUID_EXT_SSE3,

        .features[FEAT_8000_0001_EDX] =

            PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,

        .features[FEAT_8000_0001_ECX] =

            0,

        .xlevel = 0x80000008,

        .model_id = "Common 32-bit KVM processor"

    },

    {

        .name = "coreduo",

        .level = 10,

        .vendor = CPUID_VENDOR_INTEL,

        .family = 6,

        .model = 14,

        .stepping = 8,

        .features[FEAT_1_EDX] =

            PPRO_FEATURES | CPUID_VME |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |

            CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,

        .features[FEAT_1_ECX] =

            CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |

            CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,

        .features[FEAT_8000_0001_EDX] =

            CPUID_EXT2_NX,

        .xlevel = 0x80000008,

        .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",

    },

    {

        .name = "486",

        .level = 1,

        .vendor = CPUID_VENDOR_INTEL,

        .family = 4,

        .model = 8,

        .stepping = 0,

        .features[FEAT_1_EDX] =

            I486_FEATURES,

        .xlevel = 0,

    },

    {

        .name = "pentium",

        .level = 1,

        .vendor = CPUID_VENDOR_INTEL,

        .family = 5,

        .model = 4,

        .stepping = 3,

        .features[FEAT_1_EDX] =

            PENTIUM_FEATURES,

        .xlevel = 0,

    },

    {

        .name = "pentium2",

        .level = 2,

        .vendor = CPUID_VENDOR_INTEL,

        .family = 6,

        .model = 5,

        .stepping = 2,

        .features[FEAT_1_EDX] =

            PENTIUM2_FEATURES,

        .xlevel = 0,

    },

    {

        .name = "pentium3",

        .level = 2,

        .vendor = CPUID_VENDOR_INTEL,

        .family = 6,

        .model = 7,

        .stepping = 3,

        .features[FEAT_1_EDX] =

            PENTIUM3_FEATURES,

        .xlevel = 0,

    },

    {

        .name = "athlon",

        .level = 2,

        .vendor = CPUID_VENDOR_AMD,

        .family = 6,

        .model = 2,

        .stepping = 3,

        .features[FEAT_1_EDX] =

            PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |

            CPUID_MCA,

        .features[FEAT_8000_0001_EDX] =

            (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |

            CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,

        .xlevel = 0x80000008,

    },

    {

        .name = "n270",

        /* original is on level 10 */

        .level = 5,

        .vendor = CPUID_VENDOR_INTEL,

        .family = 6,

        .model = 28,

        .stepping = 2,

        .features[FEAT_1_EDX] =

            PPRO_FEATURES |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |

            CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,

            /* Some CPUs got no CPUID_SEP */

        .features[FEAT_1_ECX] =

            CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |

            CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |

            CPUID_EXT_MOVBE,

        .features[FEAT_8000_0001_EDX] =

            (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |

            CPUID_EXT2_NX,

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_LAHF_LM,

        .xlevel = 0x8000000A,

        .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",

    },

    {

        .name = "Conroe",

        .level = 4,

        .vendor = CPUID_VENDOR_INTEL,

        .family = 6,

        .model = 15,

        .stepping = 3,

        .features[FEAT_1_EDX] =

            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |

             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |

             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |

             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |

             CPUID_DE | CPUID_FP87,

        .features[FEAT_1_ECX] =

            CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,

        .features[FEAT_8000_0001_EDX] =

            CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_LAHF_LM,

        .xlevel = 0x8000000A,

        .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",

    },