root / hw / pflash_cfi02.c @ 37952117
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1 | 29133e9a | bellard | /*
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2 | 29133e9a | bellard | * CFI parallel flash with AMD command set emulation
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3 | 5fafdf24 | ths | *
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4 | 29133e9a | bellard | * Copyright (c) 2005 Jocelyn Mayer
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5 | 29133e9a | bellard | *
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6 | 29133e9a | bellard | * This library is free software; you can redistribute it and/or
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7 | 29133e9a | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 29133e9a | bellard | * License as published by the Free Software Foundation; either
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9 | 29133e9a | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 29133e9a | bellard | *
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11 | 29133e9a | bellard | * This library is distributed in the hope that it will be useful,
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12 | 29133e9a | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 29133e9a | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 29133e9a | bellard | * Lesser General Public License for more details.
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15 | 29133e9a | bellard | *
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16 | 29133e9a | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 29133e9a | bellard | */
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19 | 29133e9a | bellard | |
20 | 29133e9a | bellard | /*
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21 | 29133e9a | bellard | * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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22 | 29133e9a | bellard | * Supported commands/modes are:
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23 | 29133e9a | bellard | * - flash read
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24 | 29133e9a | bellard | * - flash write
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25 | 29133e9a | bellard | * - flash ID read
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26 | 29133e9a | bellard | * - sector erase
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27 | 29133e9a | bellard | * - chip erase
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28 | 29133e9a | bellard | * - unlock bypass command
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29 | 29133e9a | bellard | * - CFI queries
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30 | 29133e9a | bellard | *
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31 | 29133e9a | bellard | * It does not support flash interleaving.
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32 | 29133e9a | bellard | * It does not implement boot blocs with reduced size
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33 | 29133e9a | bellard | * It does not implement software data protection as found in many real chips
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34 | 29133e9a | bellard | * It does not implement erase suspend/resume commands
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35 | 29133e9a | bellard | * It does not implement multiple sectors erase
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36 | 29133e9a | bellard | */
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37 | 29133e9a | bellard | |
38 | 87ecb68b | pbrook | #include "hw.h" |
39 | 87ecb68b | pbrook | #include "flash.h" |
40 | 87ecb68b | pbrook | #include "qemu-timer.h" |
41 | 87ecb68b | pbrook | #include "block.h" |
42 | cfe5f011 | Avi Kivity | #include "exec-memory.h" |
43 | 29133e9a | bellard | |
44 | 29133e9a | bellard | //#define PFLASH_DEBUG
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45 | 29133e9a | bellard | #ifdef PFLASH_DEBUG
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46 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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47 | 29133e9a | bellard | do { \
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48 | 001faf32 | Blue Swirl | printf("PFLASH: " fmt , ## __VA_ARGS__); \ |
49 | 29133e9a | bellard | } while (0) |
50 | 29133e9a | bellard | #else
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51 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do { } while (0) |
52 | 29133e9a | bellard | #endif
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53 | 29133e9a | bellard | |
54 | 661bfc80 | Jan Kiszka | #define PFLASH_LAZY_ROMD_THRESHOLD 42 |
55 | 661bfc80 | Jan Kiszka | |
56 | c227f099 | Anthony Liguori | struct pflash_t {
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57 | 29133e9a | bellard | BlockDriverState *bs; |
58 | c227f099 | Anthony Liguori | target_phys_addr_t base; |
59 | 71db710f | blueswir1 | uint32_t sector_len; |
60 | 4fbd24ba | balrog | uint32_t chip_len; |
61 | 4fbd24ba | balrog | int mappings;
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62 | 29133e9a | bellard | int width;
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63 | 29133e9a | bellard | int wcycle; /* if 0, the flash is read normally */ |
64 | 29133e9a | bellard | int bypass;
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65 | 29133e9a | bellard | int ro;
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66 | 29133e9a | bellard | uint8_t cmd; |
67 | 29133e9a | bellard | uint8_t status; |
68 | 29133e9a | bellard | uint16_t ident[4];
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69 | 6725070d | balrog | uint16_t unlock_addr[2];
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70 | 29133e9a | bellard | uint8_t cfi_len; |
71 | 29133e9a | bellard | uint8_t cfi_table[0x52];
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72 | 29133e9a | bellard | QEMUTimer *timer; |
73 | cfe5f011 | Avi Kivity | /* The device replicates the flash memory across its memory space. Emulate
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74 | cfe5f011 | Avi Kivity | * that by having a container (.mem) filled with an array of aliases
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75 | cfe5f011 | Avi Kivity | * (.mem_mappings) pointing to the flash memory (.orig_mem).
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76 | cfe5f011 | Avi Kivity | */
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77 | cfe5f011 | Avi Kivity | MemoryRegion mem; |
78 | cfe5f011 | Avi Kivity | MemoryRegion *mem_mappings; /* array; one per mapping */
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79 | cfe5f011 | Avi Kivity | MemoryRegion orig_mem; |
80 | 9c9bb6c8 | balrog | int rom_mode;
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81 | 661bfc80 | Jan Kiszka | int read_counter; /* used for lazy switch-back to rom mode */ |
82 | 29133e9a | bellard | void *storage;
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83 | 29133e9a | bellard | }; |
84 | 29133e9a | bellard | |
85 | cfe5f011 | Avi Kivity | /*
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86 | cfe5f011 | Avi Kivity | * Set up replicated mappings of the same region.
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87 | cfe5f011 | Avi Kivity | */
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88 | cfe5f011 | Avi Kivity | static void pflash_setup_mappings(pflash_t *pfl) |
89 | c8a50e59 | Avi Kivity | { |
90 | cfe5f011 | Avi Kivity | unsigned i;
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91 | cfe5f011 | Avi Kivity | target_phys_addr_t size = memory_region_size(&pfl->orig_mem); |
92 | cfe5f011 | Avi Kivity | |
93 | cfe5f011 | Avi Kivity | memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
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94 | cfe5f011 | Avi Kivity | pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); |
95 | cfe5f011 | Avi Kivity | for (i = 0; i < pfl->mappings; ++i) { |
96 | cfe5f011 | Avi Kivity | memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias",
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97 | cfe5f011 | Avi Kivity | &pfl->orig_mem, 0, size);
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98 | cfe5f011 | Avi Kivity | memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]); |
99 | cfe5f011 | Avi Kivity | } |
100 | cfe5f011 | Avi Kivity | } |
101 | 01e0451a | Anthony Liguori | |
102 | cfe5f011 | Avi Kivity | static void pflash_register_memory(pflash_t *pfl, int rom_mode) |
103 | cfe5f011 | Avi Kivity | { |
104 | cfe5f011 | Avi Kivity | memory_region_rom_device_set_readable(&pfl->orig_mem, rom_mode); |
105 | bda254da | Jan Kiszka | pfl->rom_mode = rom_mode; |
106 | 4fbd24ba | balrog | } |
107 | 4fbd24ba | balrog | |
108 | 29133e9a | bellard | static void pflash_timer (void *opaque) |
109 | 29133e9a | bellard | { |
110 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
111 | 29133e9a | bellard | |
112 | 29133e9a | bellard | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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113 | 29133e9a | bellard | /* Reset flash */
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114 | 29133e9a | bellard | pfl->status ^= 0x80;
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115 | 29133e9a | bellard | if (pfl->bypass) {
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116 | 29133e9a | bellard | pfl->wcycle = 2;
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117 | 29133e9a | bellard | } else {
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118 | 4fbd24ba | balrog | pflash_register_memory(pfl, 1);
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119 | 29133e9a | bellard | pfl->wcycle = 0;
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120 | 29133e9a | bellard | } |
121 | 29133e9a | bellard | pfl->cmd = 0;
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122 | 29133e9a | bellard | } |
123 | 29133e9a | bellard | |
124 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
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125 | 5f9fc5ad | Blue Swirl | int width, int be) |
126 | 29133e9a | bellard | { |
127 | f8be67ee | Blue Swirl | target_phys_addr_t boff; |
128 | 29133e9a | bellard | uint32_t ret; |
129 | 29133e9a | bellard | uint8_t *p; |
130 | 29133e9a | bellard | |
131 | f8be67ee | Blue Swirl | DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset); |
132 | 29133e9a | bellard | ret = -1;
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133 | 661bfc80 | Jan Kiszka | /* Lazy reset to ROMD mode after a certain amount of read accesses */
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134 | 661bfc80 | Jan Kiszka | if (!pfl->rom_mode && pfl->wcycle == 0 && |
135 | 661bfc80 | Jan Kiszka | ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { |
136 | 661bfc80 | Jan Kiszka | pflash_register_memory(pfl, 1);
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137 | 0f459d16 | pbrook | } |
138 | 4fbd24ba | balrog | offset &= pfl->chip_len - 1;
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139 | 29133e9a | bellard | boff = offset & 0xFF;
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140 | 29133e9a | bellard | if (pfl->width == 2) |
141 | 29133e9a | bellard | boff = boff >> 1;
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142 | 29133e9a | bellard | else if (pfl->width == 4) |
143 | 29133e9a | bellard | boff = boff >> 2;
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144 | 29133e9a | bellard | switch (pfl->cmd) {
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145 | 29133e9a | bellard | default:
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146 | 29133e9a | bellard | /* This should never happen : reset state & treat it as a read*/
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147 | 29133e9a | bellard | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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148 | 29133e9a | bellard | pfl->wcycle = 0;
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149 | 29133e9a | bellard | pfl->cmd = 0;
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150 | 29133e9a | bellard | case 0x80: |
151 | 29133e9a | bellard | /* We accept reads during second unlock sequence... */
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152 | 29133e9a | bellard | case 0x00: |
153 | 29133e9a | bellard | flash_read:
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154 | 29133e9a | bellard | /* Flash area read */
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155 | 29133e9a | bellard | p = pfl->storage; |
156 | 29133e9a | bellard | switch (width) {
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157 | 29133e9a | bellard | case 1: |
158 | 29133e9a | bellard | ret = p[offset]; |
159 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
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160 | 29133e9a | bellard | break;
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161 | 29133e9a | bellard | case 2: |
162 | 5f9fc5ad | Blue Swirl | if (be) {
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163 | 5f9fc5ad | Blue Swirl | ret = p[offset] << 8;
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164 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 1];
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165 | 5f9fc5ad | Blue Swirl | } else {
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166 | 5f9fc5ad | Blue Swirl | ret = p[offset]; |
167 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 1] << 8; |
168 | 5f9fc5ad | Blue Swirl | } |
169 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
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170 | 29133e9a | bellard | break;
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171 | 29133e9a | bellard | case 4: |
172 | 5f9fc5ad | Blue Swirl | if (be) {
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173 | 5f9fc5ad | Blue Swirl | ret = p[offset] << 24;
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174 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 1] << 16; |
175 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 2] << 8; |
176 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 3];
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177 | 5f9fc5ad | Blue Swirl | } else {
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178 | 5f9fc5ad | Blue Swirl | ret = p[offset]; |
179 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 1] << 8; |
180 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 2] << 16; |
181 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 3] << 24; |
182 | 5f9fc5ad | Blue Swirl | } |
183 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
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184 | 29133e9a | bellard | break;
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185 | 29133e9a | bellard | } |
186 | 29133e9a | bellard | break;
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187 | 29133e9a | bellard | case 0x90: |
188 | 29133e9a | bellard | /* flash ID read */
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189 | 29133e9a | bellard | switch (boff) {
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190 | 29133e9a | bellard | case 0x00: |
191 | 29133e9a | bellard | case 0x01: |
192 | 29133e9a | bellard | ret = pfl->ident[boff & 0x01];
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193 | 29133e9a | bellard | break;
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194 | 29133e9a | bellard | case 0x02: |
195 | 29133e9a | bellard | ret = 0x00; /* Pretend all sectors are unprotected */ |
196 | 29133e9a | bellard | break;
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197 | 29133e9a | bellard | case 0x0E: |
198 | 29133e9a | bellard | case 0x0F: |
199 | 29133e9a | bellard | if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1) |
200 | 29133e9a | bellard | goto flash_read;
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201 | 29133e9a | bellard | ret = pfl->ident[2 + (boff & 0x01)]; |
202 | 29133e9a | bellard | break;
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203 | 29133e9a | bellard | default:
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204 | 29133e9a | bellard | goto flash_read;
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205 | 29133e9a | bellard | } |
206 | b9055c3c | Stefan Weil | DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret); |
207 | 29133e9a | bellard | break;
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208 | 29133e9a | bellard | case 0xA0: |
209 | 29133e9a | bellard | case 0x10: |
210 | 29133e9a | bellard | case 0x30: |
211 | 29133e9a | bellard | /* Status register read */
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212 | 29133e9a | bellard | ret = pfl->status; |
213 | 29133e9a | bellard | DPRINTF("%s: status %x\n", __func__, ret);
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214 | 29133e9a | bellard | /* Toggle bit 6 */
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215 | 29133e9a | bellard | pfl->status ^= 0x40;
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216 | 29133e9a | bellard | break;
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217 | 29133e9a | bellard | case 0x98: |
218 | 29133e9a | bellard | /* CFI query mode */
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219 | 29133e9a | bellard | if (boff > pfl->cfi_len)
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220 | 29133e9a | bellard | ret = 0;
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221 | 29133e9a | bellard | else
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222 | 29133e9a | bellard | ret = pfl->cfi_table[boff]; |
223 | 29133e9a | bellard | break;
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224 | 29133e9a | bellard | } |
225 | 29133e9a | bellard | |
226 | 29133e9a | bellard | return ret;
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227 | 29133e9a | bellard | } |
228 | 29133e9a | bellard | |
229 | 29133e9a | bellard | /* update flash content on disk */
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230 | c227f099 | Anthony Liguori | static void pflash_update(pflash_t *pfl, int offset, |
231 | 29133e9a | bellard | int size)
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232 | 29133e9a | bellard | { |
233 | 29133e9a | bellard | int offset_end;
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234 | 29133e9a | bellard | if (pfl->bs) {
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235 | 29133e9a | bellard | offset_end = offset + size; |
236 | 29133e9a | bellard | /* round to sectors */
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237 | 29133e9a | bellard | offset = offset >> 9;
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238 | 29133e9a | bellard | offset_end = (offset_end + 511) >> 9; |
239 | 5fafdf24 | ths | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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240 | 29133e9a | bellard | offset_end - offset); |
241 | 29133e9a | bellard | } |
242 | 29133e9a | bellard | } |
243 | 29133e9a | bellard | |
244 | f8be67ee | Blue Swirl | static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, |
245 | 5f9fc5ad | Blue Swirl | uint32_t value, int width, int be) |
246 | 29133e9a | bellard | { |
247 | f8be67ee | Blue Swirl | target_phys_addr_t boff; |
248 | 29133e9a | bellard | uint8_t *p; |
249 | 29133e9a | bellard | uint8_t cmd; |
250 | 29133e9a | bellard | |
251 | 95d1f3ed | j_mayer | cmd = value; |
252 | 95d1f3ed | j_mayer | if (pfl->cmd != 0xA0 && cmd == 0xF0) { |
253 | 95d1f3ed | j_mayer | #if 0
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254 | 95d1f3ed | j_mayer | DPRINTF("%s: flash reset asked (%02x %02x)\n",
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255 | 95d1f3ed | j_mayer | __func__, pfl->cmd, cmd);
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256 | 95d1f3ed | j_mayer | #endif
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257 | 95d1f3ed | j_mayer | goto reset_flash;
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258 | 95d1f3ed | j_mayer | } |
259 | f8be67ee | Blue Swirl | DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__, |
260 | 95d1f3ed | j_mayer | offset, value, width, pfl->wcycle); |
261 | 4fbd24ba | balrog | offset &= pfl->chip_len - 1;
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262 | 3b46e624 | ths | |
263 | f8be67ee | Blue Swirl | DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__, |
264 | e96efcfc | j_mayer | offset, value, width); |
265 | 29133e9a | bellard | boff = offset & (pfl->sector_len - 1);
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266 | 29133e9a | bellard | if (pfl->width == 2) |
267 | 29133e9a | bellard | boff = boff >> 1;
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268 | 29133e9a | bellard | else if (pfl->width == 4) |
269 | 29133e9a | bellard | boff = boff >> 2;
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270 | 29133e9a | bellard | switch (pfl->wcycle) {
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271 | 29133e9a | bellard | case 0: |
272 | 9c9bb6c8 | balrog | /* Set the device in I/O access mode if required */
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273 | 9c9bb6c8 | balrog | if (pfl->rom_mode)
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274 | 9c9bb6c8 | balrog | pflash_register_memory(pfl, 0);
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275 | 661bfc80 | Jan Kiszka | pfl->read_counter = 0;
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276 | 29133e9a | bellard | /* We're in read mode */
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277 | 29133e9a | bellard | check_unlock0:
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278 | 29133e9a | bellard | if (boff == 0x55 && cmd == 0x98) { |
279 | 29133e9a | bellard | enter_CFI_mode:
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280 | 29133e9a | bellard | /* Enter CFI query mode */
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281 | 29133e9a | bellard | pfl->wcycle = 7;
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282 | 29133e9a | bellard | pfl->cmd = 0x98;
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283 | 29133e9a | bellard | return;
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284 | 29133e9a | bellard | } |
285 | 6725070d | balrog | if (boff != pfl->unlock_addr[0] || cmd != 0xAA) { |
286 | f8be67ee | Blue Swirl | DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", |
287 | 6725070d | balrog | __func__, boff, cmd, pfl->unlock_addr[0]);
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288 | 29133e9a | bellard | goto reset_flash;
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289 | 29133e9a | bellard | } |
290 | 29133e9a | bellard | DPRINTF("%s: unlock sequence started\n", __func__);
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291 | 29133e9a | bellard | break;
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292 | 29133e9a | bellard | case 1: |
293 | 29133e9a | bellard | /* We started an unlock sequence */
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294 | 29133e9a | bellard | check_unlock1:
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295 | 6725070d | balrog | if (boff != pfl->unlock_addr[1] || cmd != 0x55) { |
296 | f8be67ee | Blue Swirl | DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, |
297 | e96efcfc | j_mayer | boff, cmd); |
298 | 29133e9a | bellard | goto reset_flash;
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299 | 29133e9a | bellard | } |
300 | 29133e9a | bellard | DPRINTF("%s: unlock sequence done\n", __func__);
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301 | 29133e9a | bellard | break;
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302 | 29133e9a | bellard | case 2: |
303 | 29133e9a | bellard | /* We finished an unlock sequence */
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304 | 6725070d | balrog | if (!pfl->bypass && boff != pfl->unlock_addr[0]) { |
305 | f8be67ee | Blue Swirl | DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, |
306 | e96efcfc | j_mayer | boff, cmd); |
307 | 29133e9a | bellard | goto reset_flash;
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308 | 29133e9a | bellard | } |
309 | 29133e9a | bellard | switch (cmd) {
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310 | 29133e9a | bellard | case 0x20: |
311 | 29133e9a | bellard | pfl->bypass = 1;
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312 | 29133e9a | bellard | goto do_bypass;
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313 | 29133e9a | bellard | case 0x80: |
314 | 29133e9a | bellard | case 0x90: |
315 | 29133e9a | bellard | case 0xA0: |
316 | 29133e9a | bellard | pfl->cmd = cmd; |
317 | 29133e9a | bellard | DPRINTF("%s: starting command %02x\n", __func__, cmd);
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318 | 29133e9a | bellard | break;
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319 | 29133e9a | bellard | default:
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320 | 29133e9a | bellard | DPRINTF("%s: unknown command %02x\n", __func__, cmd);
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321 | 29133e9a | bellard | goto reset_flash;
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322 | 29133e9a | bellard | } |
323 | 29133e9a | bellard | break;
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324 | 29133e9a | bellard | case 3: |
325 | 29133e9a | bellard | switch (pfl->cmd) {
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326 | 29133e9a | bellard | case 0x80: |
327 | 29133e9a | bellard | /* We need another unlock sequence */
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328 | 29133e9a | bellard | goto check_unlock0;
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329 | 29133e9a | bellard | case 0xA0: |
330 | f8be67ee | Blue Swirl | DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n", |
331 | 29133e9a | bellard | __func__, offset, value, width); |
332 | 29133e9a | bellard | p = pfl->storage; |
333 | de8efe8f | Jordan Justen | if (!pfl->ro) {
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334 | de8efe8f | Jordan Justen | switch (width) {
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335 | de8efe8f | Jordan Justen | case 1: |
336 | 5f9fc5ad | Blue Swirl | p[offset] &= value; |
337 | de8efe8f | Jordan Justen | pflash_update(pfl, offset, 1);
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338 | de8efe8f | Jordan Justen | break;
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339 | de8efe8f | Jordan Justen | case 2: |
340 | de8efe8f | Jordan Justen | if (be) {
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341 | de8efe8f | Jordan Justen | p[offset] &= value >> 8;
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342 | de8efe8f | Jordan Justen | p[offset + 1] &= value;
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343 | de8efe8f | Jordan Justen | } else {
|
344 | de8efe8f | Jordan Justen | p[offset] &= value; |
345 | de8efe8f | Jordan Justen | p[offset + 1] &= value >> 8; |
346 | de8efe8f | Jordan Justen | } |
347 | de8efe8f | Jordan Justen | pflash_update(pfl, offset, 2);
|
348 | de8efe8f | Jordan Justen | break;
|
349 | de8efe8f | Jordan Justen | case 4: |
350 | de8efe8f | Jordan Justen | if (be) {
|
351 | de8efe8f | Jordan Justen | p[offset] &= value >> 24;
|
352 | de8efe8f | Jordan Justen | p[offset + 1] &= value >> 16; |
353 | de8efe8f | Jordan Justen | p[offset + 2] &= value >> 8; |
354 | de8efe8f | Jordan Justen | p[offset + 3] &= value;
|
355 | de8efe8f | Jordan Justen | } else {
|
356 | de8efe8f | Jordan Justen | p[offset] &= value; |
357 | de8efe8f | Jordan Justen | p[offset + 1] &= value >> 8; |
358 | de8efe8f | Jordan Justen | p[offset + 2] &= value >> 16; |
359 | de8efe8f | Jordan Justen | p[offset + 3] &= value >> 24; |
360 | de8efe8f | Jordan Justen | } |
361 | de8efe8f | Jordan Justen | pflash_update(pfl, offset, 4);
|
362 | de8efe8f | Jordan Justen | break;
|
363 | 5f9fc5ad | Blue Swirl | } |
364 | 29133e9a | bellard | } |
365 | 29133e9a | bellard | pfl->status = 0x00 | ~(value & 0x80); |
366 | 29133e9a | bellard | /* Let's pretend write is immediate */
|
367 | 29133e9a | bellard | if (pfl->bypass)
|
368 | 29133e9a | bellard | goto do_bypass;
|
369 | 29133e9a | bellard | goto reset_flash;
|
370 | 29133e9a | bellard | case 0x90: |
371 | 29133e9a | bellard | if (pfl->bypass && cmd == 0x00) { |
372 | 29133e9a | bellard | /* Unlock bypass reset */
|
373 | 29133e9a | bellard | goto reset_flash;
|
374 | 29133e9a | bellard | } |
375 | 29133e9a | bellard | /* We can enter CFI query mode from autoselect mode */
|
376 | 29133e9a | bellard | if (boff == 0x55 && cmd == 0x98) |
377 | 29133e9a | bellard | goto enter_CFI_mode;
|
378 | 29133e9a | bellard | /* No break here */
|
379 | 29133e9a | bellard | default:
|
380 | 29133e9a | bellard | DPRINTF("%s: invalid write for command %02x\n",
|
381 | 29133e9a | bellard | __func__, pfl->cmd); |
382 | 29133e9a | bellard | goto reset_flash;
|
383 | 29133e9a | bellard | } |
384 | 29133e9a | bellard | case 4: |
385 | 29133e9a | bellard | switch (pfl->cmd) {
|
386 | 29133e9a | bellard | case 0xA0: |
387 | a1c7273b | Stefan Weil | /* Ignore writes while flash data write is occurring */
|
388 | 29133e9a | bellard | /* As we suppose write is immediate, this should never happen */
|
389 | 29133e9a | bellard | return;
|
390 | 29133e9a | bellard | case 0x80: |
391 | 29133e9a | bellard | goto check_unlock1;
|
392 | 29133e9a | bellard | default:
|
393 | 29133e9a | bellard | /* Should never happen */
|
394 | 29133e9a | bellard | DPRINTF("%s: invalid command state %02x (wc 4)\n",
|
395 | 29133e9a | bellard | __func__, pfl->cmd); |
396 | 29133e9a | bellard | goto reset_flash;
|
397 | 29133e9a | bellard | } |
398 | 29133e9a | bellard | break;
|
399 | 29133e9a | bellard | case 5: |
400 | 29133e9a | bellard | switch (cmd) {
|
401 | 29133e9a | bellard | case 0x10: |
402 | 6725070d | balrog | if (boff != pfl->unlock_addr[0]) { |
403 | f8be67ee | Blue Swirl | DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", |
404 | 29133e9a | bellard | __func__, offset); |
405 | 29133e9a | bellard | goto reset_flash;
|
406 | 29133e9a | bellard | } |
407 | 29133e9a | bellard | /* Chip erase */
|
408 | 29133e9a | bellard | DPRINTF("%s: start chip erase\n", __func__);
|
409 | de8efe8f | Jordan Justen | if (!pfl->ro) {
|
410 | de8efe8f | Jordan Justen | memset(pfl->storage, 0xFF, pfl->chip_len);
|
411 | de8efe8f | Jordan Justen | pflash_update(pfl, 0, pfl->chip_len);
|
412 | de8efe8f | Jordan Justen | } |
413 | 29133e9a | bellard | pfl->status = 0x00;
|
414 | 29133e9a | bellard | /* Let's wait 5 seconds before chip erase is done */
|
415 | 5fafdf24 | ths | qemu_mod_timer(pfl->timer, |
416 | 74475455 | Paolo Bonzini | qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() * 5));
|
417 | 29133e9a | bellard | break;
|
418 | 29133e9a | bellard | case 0x30: |
419 | 29133e9a | bellard | /* Sector erase */
|
420 | 29133e9a | bellard | p = pfl->storage; |
421 | 29133e9a | bellard | offset &= ~(pfl->sector_len - 1);
|
422 | f8be67ee | Blue Swirl | DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__, |
423 | e96efcfc | j_mayer | offset); |
424 | de8efe8f | Jordan Justen | if (!pfl->ro) {
|
425 | de8efe8f | Jordan Justen | memset(p + offset, 0xFF, pfl->sector_len);
|
426 | de8efe8f | Jordan Justen | pflash_update(pfl, offset, pfl->sector_len); |
427 | de8efe8f | Jordan Justen | } |
428 | 29133e9a | bellard | pfl->status = 0x00;
|
429 | 29133e9a | bellard | /* Let's wait 1/2 second before sector erase is done */
|
430 | 5fafdf24 | ths | qemu_mod_timer(pfl->timer, |
431 | 74475455 | Paolo Bonzini | qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 2));
|
432 | 29133e9a | bellard | break;
|
433 | 29133e9a | bellard | default:
|
434 | 29133e9a | bellard | DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
|
435 | 29133e9a | bellard | goto reset_flash;
|
436 | 29133e9a | bellard | } |
437 | 29133e9a | bellard | pfl->cmd = cmd; |
438 | 29133e9a | bellard | break;
|
439 | 29133e9a | bellard | case 6: |
440 | 29133e9a | bellard | switch (pfl->cmd) {
|
441 | 29133e9a | bellard | case 0x10: |
442 | 29133e9a | bellard | /* Ignore writes during chip erase */
|
443 | 29133e9a | bellard | return;
|
444 | 29133e9a | bellard | case 0x30: |
445 | 29133e9a | bellard | /* Ignore writes during sector erase */
|
446 | 29133e9a | bellard | return;
|
447 | 29133e9a | bellard | default:
|
448 | 29133e9a | bellard | /* Should never happen */
|
449 | 29133e9a | bellard | DPRINTF("%s: invalid command state %02x (wc 6)\n",
|
450 | 29133e9a | bellard | __func__, pfl->cmd); |
451 | 29133e9a | bellard | goto reset_flash;
|
452 | 29133e9a | bellard | } |
453 | 29133e9a | bellard | break;
|
454 | 29133e9a | bellard | case 7: /* Special value for CFI queries */ |
455 | 29133e9a | bellard | DPRINTF("%s: invalid write in CFI query mode\n", __func__);
|
456 | 29133e9a | bellard | goto reset_flash;
|
457 | 29133e9a | bellard | default:
|
458 | 29133e9a | bellard | /* Should never happen */
|
459 | 29133e9a | bellard | DPRINTF("%s: invalid write state (wc 7)\n", __func__);
|
460 | 29133e9a | bellard | goto reset_flash;
|
461 | 29133e9a | bellard | } |
462 | 29133e9a | bellard | pfl->wcycle++; |
463 | 29133e9a | bellard | |
464 | 29133e9a | bellard | return;
|
465 | 29133e9a | bellard | |
466 | 29133e9a | bellard | /* Reset flash */
|
467 | 29133e9a | bellard | reset_flash:
|
468 | 29133e9a | bellard | pfl->bypass = 0;
|
469 | 29133e9a | bellard | pfl->wcycle = 0;
|
470 | 29133e9a | bellard | pfl->cmd = 0;
|
471 | 29133e9a | bellard | return;
|
472 | 29133e9a | bellard | |
473 | 29133e9a | bellard | do_bypass:
|
474 | 29133e9a | bellard | pfl->wcycle = 2;
|
475 | 29133e9a | bellard | pfl->cmd = 0;
|
476 | 29133e9a | bellard | return;
|
477 | 29133e9a | bellard | } |
478 | 29133e9a | bellard | |
479 | 29133e9a | bellard | |
480 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr) |
481 | 5f9fc5ad | Blue Swirl | { |
482 | 5f9fc5ad | Blue Swirl | return pflash_read(opaque, addr, 1, 1); |
483 | 5f9fc5ad | Blue Swirl | } |
484 | 5f9fc5ad | Blue Swirl | |
485 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr) |
486 | 5f9fc5ad | Blue Swirl | { |
487 | 5f9fc5ad | Blue Swirl | return pflash_read(opaque, addr, 1, 0); |
488 | 5f9fc5ad | Blue Swirl | } |
489 | 5f9fc5ad | Blue Swirl | |
490 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr) |
491 | 5f9fc5ad | Blue Swirl | { |
492 | 5f9fc5ad | Blue Swirl | pflash_t *pfl = opaque; |
493 | 5f9fc5ad | Blue Swirl | |
494 | 5f9fc5ad | Blue Swirl | return pflash_read(pfl, addr, 2, 1); |
495 | 5f9fc5ad | Blue Swirl | } |
496 | 5f9fc5ad | Blue Swirl | |
497 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr) |
498 | 5f9fc5ad | Blue Swirl | { |
499 | 5f9fc5ad | Blue Swirl | pflash_t *pfl = opaque; |
500 | 5f9fc5ad | Blue Swirl | |
501 | 5f9fc5ad | Blue Swirl | return pflash_read(pfl, addr, 2, 0); |
502 | 5f9fc5ad | Blue Swirl | } |
503 | 5f9fc5ad | Blue Swirl | |
504 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr) |
505 | 29133e9a | bellard | { |
506 | 5f9fc5ad | Blue Swirl | pflash_t *pfl = opaque; |
507 | 5f9fc5ad | Blue Swirl | |
508 | 5f9fc5ad | Blue Swirl | return pflash_read(pfl, addr, 4, 1); |
509 | 29133e9a | bellard | } |
510 | 29133e9a | bellard | |
511 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr) |
512 | 29133e9a | bellard | { |
513 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
514 | 29133e9a | bellard | |
515 | 5f9fc5ad | Blue Swirl | return pflash_read(pfl, addr, 4, 0); |
516 | 5f9fc5ad | Blue Swirl | } |
517 | 5f9fc5ad | Blue Swirl | |
518 | 5f9fc5ad | Blue Swirl | static void pflash_writeb_be(void *opaque, target_phys_addr_t addr, |
519 | 5f9fc5ad | Blue Swirl | uint32_t value) |
520 | 5f9fc5ad | Blue Swirl | { |
521 | 5f9fc5ad | Blue Swirl | pflash_write(opaque, addr, value, 1, 1); |
522 | 29133e9a | bellard | } |
523 | 29133e9a | bellard | |
524 | 5f9fc5ad | Blue Swirl | static void pflash_writeb_le(void *opaque, target_phys_addr_t addr, |
525 | 5f9fc5ad | Blue Swirl | uint32_t value) |
526 | 5f9fc5ad | Blue Swirl | { |
527 | 5f9fc5ad | Blue Swirl | pflash_write(opaque, addr, value, 1, 0); |
528 | 5f9fc5ad | Blue Swirl | } |
529 | 5f9fc5ad | Blue Swirl | |
530 | 5f9fc5ad | Blue Swirl | static void pflash_writew_be(void *opaque, target_phys_addr_t addr, |
531 | 5f9fc5ad | Blue Swirl | uint32_t value) |
532 | 29133e9a | bellard | { |
533 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
534 | 29133e9a | bellard | |
535 | 5f9fc5ad | Blue Swirl | pflash_write(pfl, addr, value, 2, 1); |
536 | 29133e9a | bellard | } |
537 | 29133e9a | bellard | |
538 | 5f9fc5ad | Blue Swirl | static void pflash_writew_le(void *opaque, target_phys_addr_t addr, |
539 | 5f9fc5ad | Blue Swirl | uint32_t value) |
540 | 29133e9a | bellard | { |
541 | 5f9fc5ad | Blue Swirl | pflash_t *pfl = opaque; |
542 | 5f9fc5ad | Blue Swirl | |
543 | 5f9fc5ad | Blue Swirl | pflash_write(pfl, addr, value, 2, 0); |
544 | 29133e9a | bellard | } |
545 | 29133e9a | bellard | |
546 | 5f9fc5ad | Blue Swirl | static void pflash_writel_be(void *opaque, target_phys_addr_t addr, |
547 | 5f9fc5ad | Blue Swirl | uint32_t value) |
548 | 29133e9a | bellard | { |
549 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
550 | 29133e9a | bellard | |
551 | 5f9fc5ad | Blue Swirl | pflash_write(pfl, addr, value, 4, 1); |
552 | 29133e9a | bellard | } |
553 | 29133e9a | bellard | |
554 | 5f9fc5ad | Blue Swirl | static void pflash_writel_le(void *opaque, target_phys_addr_t addr, |
555 | 5f9fc5ad | Blue Swirl | uint32_t value) |
556 | 29133e9a | bellard | { |
557 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
558 | 29133e9a | bellard | |
559 | 5f9fc5ad | Blue Swirl | pflash_write(pfl, addr, value, 4, 0); |
560 | 29133e9a | bellard | } |
561 | 29133e9a | bellard | |
562 | cfe5f011 | Avi Kivity | static const MemoryRegionOps pflash_cfi02_ops_be = { |
563 | cfe5f011 | Avi Kivity | .old_mmio = { |
564 | cfe5f011 | Avi Kivity | .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, |
565 | cfe5f011 | Avi Kivity | .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, |
566 | cfe5f011 | Avi Kivity | }, |
567 | cfe5f011 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
568 | 5f9fc5ad | Blue Swirl | }; |
569 | 5f9fc5ad | Blue Swirl | |
570 | cfe5f011 | Avi Kivity | static const MemoryRegionOps pflash_cfi02_ops_le = { |
571 | cfe5f011 | Avi Kivity | .old_mmio = { |
572 | cfe5f011 | Avi Kivity | .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, |
573 | cfe5f011 | Avi Kivity | .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, |
574 | cfe5f011 | Avi Kivity | }, |
575 | cfe5f011 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
576 | 29133e9a | bellard | }; |
577 | 29133e9a | bellard | |
578 | 29133e9a | bellard | /* Count trailing zeroes of a 32 bits quantity */
|
579 | 29133e9a | bellard | static int ctz32 (uint32_t n) |
580 | 29133e9a | bellard | { |
581 | 29133e9a | bellard | int ret;
|
582 | 29133e9a | bellard | |
583 | 29133e9a | bellard | ret = 0;
|
584 | 29133e9a | bellard | if (!(n & 0xFFFF)) { |
585 | 29133e9a | bellard | ret += 16;
|
586 | 29133e9a | bellard | n = n >> 16;
|
587 | 29133e9a | bellard | } |
588 | 29133e9a | bellard | if (!(n & 0xFF)) { |
589 | 29133e9a | bellard | ret += 8;
|
590 | 29133e9a | bellard | n = n >> 8;
|
591 | 29133e9a | bellard | } |
592 | 29133e9a | bellard | if (!(n & 0xF)) { |
593 | 29133e9a | bellard | ret += 4;
|
594 | 29133e9a | bellard | n = n >> 4;
|
595 | 29133e9a | bellard | } |
596 | 29133e9a | bellard | if (!(n & 0x3)) { |
597 | 29133e9a | bellard | ret += 2;
|
598 | 29133e9a | bellard | n = n >> 2;
|
599 | 29133e9a | bellard | } |
600 | 29133e9a | bellard | if (!(n & 0x1)) { |
601 | 29133e9a | bellard | ret++; |
602 | 22ed1d34 | Blue Swirl | #if 0 /* This is not necessary as n is never 0 */
|
603 | 29133e9a | bellard | n = n >> 1;
|
604 | 22ed1d34 | Blue Swirl | #endif
|
605 | 29133e9a | bellard | } |
606 | 29133e9a | bellard | #if 0 /* This is not necessary as n is never 0 */
|
607 | 29133e9a | bellard | if (!n)
|
608 | 29133e9a | bellard | ret++;
|
609 | 29133e9a | bellard | #endif
|
610 | 29133e9a | bellard | |
611 | 29133e9a | bellard | return ret;
|
612 | 29133e9a | bellard | } |
613 | 29133e9a | bellard | |
614 | cfe5f011 | Avi Kivity | pflash_t *pflash_cfi02_register(target_phys_addr_t base, |
615 | cfe5f011 | Avi Kivity | DeviceState *qdev, const char *name, |
616 | cfe5f011 | Avi Kivity | target_phys_addr_t size, |
617 | cf6d9118 | balrog | BlockDriverState *bs, uint32_t sector_len, |
618 | 4fbd24ba | balrog | int nb_blocs, int nb_mappings, int width, |
619 | 88eeee0a | balrog | uint16_t id0, uint16_t id1, |
620 | 6725070d | balrog | uint16_t id2, uint16_t id3, |
621 | 01e0451a | Anthony Liguori | uint16_t unlock_addr0, uint16_t unlock_addr1, |
622 | 01e0451a | Anthony Liguori | int be)
|
623 | 29133e9a | bellard | { |
624 | c227f099 | Anthony Liguori | pflash_t *pfl; |
625 | 4fbd24ba | balrog | int32_t chip_len; |
626 | d0e7605e | Vijay Kumar | int ret;
|
627 | 29133e9a | bellard | |
628 | 4fbd24ba | balrog | chip_len = sector_len * nb_blocs; |
629 | 29133e9a | bellard | /* XXX: to be fixed */
|
630 | 95d1f3ed | j_mayer | #if 0
|
631 | 29133e9a | bellard | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
632 | 29133e9a | bellard | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
633 | 29133e9a | bellard | return NULL;
|
634 | 95d1f3ed | j_mayer | #endif
|
635 | 7267c094 | Anthony Liguori | pfl = g_malloc0(sizeof(pflash_t));
|
636 | cfe5f011 | Avi Kivity | memory_region_init_rom_device( |
637 | cfe5f011 | Avi Kivity | &pfl->orig_mem, be ? &pflash_cfi02_ops_be : &pflash_cfi02_ops_le, pfl, |
638 | c5705a77 | Avi Kivity | name, size); |
639 | c5705a77 | Avi Kivity | vmstate_register_ram(&pfl->orig_mem, qdev); |
640 | cfe5f011 | Avi Kivity | pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); |
641 | 4fbd24ba | balrog | pfl->base = base; |
642 | 4fbd24ba | balrog | pfl->chip_len = chip_len; |
643 | 4fbd24ba | balrog | pfl->mappings = nb_mappings; |
644 | 29133e9a | bellard | pfl->bs = bs; |
645 | 29133e9a | bellard | if (pfl->bs) {
|
646 | 29133e9a | bellard | /* read the initial flash content */
|
647 | d0e7605e | Vijay Kumar | ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); |
648 | d0e7605e | Vijay Kumar | if (ret < 0) { |
649 | 7267c094 | Anthony Liguori | g_free(pfl); |
650 | d0e7605e | Vijay Kumar | return NULL; |
651 | d0e7605e | Vijay Kumar | } |
652 | fa879d62 | Markus Armbruster | bdrv_attach_dev_nofail(pfl->bs, pfl); |
653 | 29133e9a | bellard | } |
654 | de8efe8f | Jordan Justen | |
655 | cfe5f011 | Avi Kivity | pflash_setup_mappings(pfl); |
656 | cfe5f011 | Avi Kivity | pfl->rom_mode = 1;
|
657 | cfe5f011 | Avi Kivity | memory_region_add_subregion(get_system_memory(), pfl->base, &pfl->mem); |
658 | de8efe8f | Jordan Justen | |
659 | de8efe8f | Jordan Justen | if (pfl->bs) {
|
660 | de8efe8f | Jordan Justen | pfl->ro = bdrv_is_read_only(pfl->bs); |
661 | de8efe8f | Jordan Justen | } else {
|
662 | de8efe8f | Jordan Justen | pfl->ro = 0;
|
663 | de8efe8f | Jordan Justen | } |
664 | de8efe8f | Jordan Justen | |
665 | 74475455 | Paolo Bonzini | pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); |
666 | 29133e9a | bellard | pfl->sector_len = sector_len; |
667 | 29133e9a | bellard | pfl->width = width; |
668 | 29133e9a | bellard | pfl->wcycle = 0;
|
669 | 29133e9a | bellard | pfl->cmd = 0;
|
670 | 29133e9a | bellard | pfl->status = 0;
|
671 | 29133e9a | bellard | pfl->ident[0] = id0;
|
672 | 29133e9a | bellard | pfl->ident[1] = id1;
|
673 | 29133e9a | bellard | pfl->ident[2] = id2;
|
674 | 29133e9a | bellard | pfl->ident[3] = id3;
|
675 | 6725070d | balrog | pfl->unlock_addr[0] = unlock_addr0;
|
676 | 6725070d | balrog | pfl->unlock_addr[1] = unlock_addr1;
|
677 | 29133e9a | bellard | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
678 | 29133e9a | bellard | pfl->cfi_len = 0x52;
|
679 | 29133e9a | bellard | /* Standard "QRY" string */
|
680 | 29133e9a | bellard | pfl->cfi_table[0x10] = 'Q'; |
681 | 29133e9a | bellard | pfl->cfi_table[0x11] = 'R'; |
682 | 29133e9a | bellard | pfl->cfi_table[0x12] = 'Y'; |
683 | 29133e9a | bellard | /* Command set (AMD/Fujitsu) */
|
684 | 29133e9a | bellard | pfl->cfi_table[0x13] = 0x02; |
685 | 29133e9a | bellard | pfl->cfi_table[0x14] = 0x00; |
686 | 78556820 | edgar_igl | /* Primary extended table address */
|
687 | 78556820 | edgar_igl | pfl->cfi_table[0x15] = 0x31; |
688 | 29133e9a | bellard | pfl->cfi_table[0x16] = 0x00; |
689 | 29133e9a | bellard | /* Alternate command set (none) */
|
690 | 29133e9a | bellard | pfl->cfi_table[0x17] = 0x00; |
691 | 29133e9a | bellard | pfl->cfi_table[0x18] = 0x00; |
692 | 29133e9a | bellard | /* Alternate extended table (none) */
|
693 | 29133e9a | bellard | pfl->cfi_table[0x19] = 0x00; |
694 | 29133e9a | bellard | pfl->cfi_table[0x1A] = 0x00; |
695 | 29133e9a | bellard | /* Vcc min */
|
696 | 29133e9a | bellard | pfl->cfi_table[0x1B] = 0x27; |
697 | 29133e9a | bellard | /* Vcc max */
|
698 | 29133e9a | bellard | pfl->cfi_table[0x1C] = 0x36; |
699 | 29133e9a | bellard | /* Vpp min (no Vpp pin) */
|
700 | 29133e9a | bellard | pfl->cfi_table[0x1D] = 0x00; |
701 | 29133e9a | bellard | /* Vpp max (no Vpp pin) */
|
702 | 29133e9a | bellard | pfl->cfi_table[0x1E] = 0x00; |
703 | 29133e9a | bellard | /* Reserved */
|
704 | 29133e9a | bellard | pfl->cfi_table[0x1F] = 0x07; |
705 | 78556820 | edgar_igl | /* Timeout for min size buffer write (NA) */
|
706 | 78556820 | edgar_igl | pfl->cfi_table[0x20] = 0x00; |
707 | 29133e9a | bellard | /* Typical timeout for block erase (512 ms) */
|
708 | 29133e9a | bellard | pfl->cfi_table[0x21] = 0x09; |
709 | 29133e9a | bellard | /* Typical timeout for full chip erase (4096 ms) */
|
710 | 29133e9a | bellard | pfl->cfi_table[0x22] = 0x0C; |
711 | 29133e9a | bellard | /* Reserved */
|
712 | 29133e9a | bellard | pfl->cfi_table[0x23] = 0x01; |
713 | 78556820 | edgar_igl | /* Max timeout for buffer write (NA) */
|
714 | 78556820 | edgar_igl | pfl->cfi_table[0x24] = 0x00; |
715 | 29133e9a | bellard | /* Max timeout for block erase */
|
716 | 29133e9a | bellard | pfl->cfi_table[0x25] = 0x0A; |
717 | 29133e9a | bellard | /* Max timeout for chip erase */
|
718 | 29133e9a | bellard | pfl->cfi_table[0x26] = 0x0D; |
719 | 29133e9a | bellard | /* Device size */
|
720 | 78556820 | edgar_igl | pfl->cfi_table[0x27] = ctz32(chip_len);
|
721 | 29133e9a | bellard | /* Flash device interface (8 & 16 bits) */
|
722 | 29133e9a | bellard | pfl->cfi_table[0x28] = 0x02; |
723 | 29133e9a | bellard | pfl->cfi_table[0x29] = 0x00; |
724 | 29133e9a | bellard | /* Max number of bytes in multi-bytes write */
|
725 | 95d1f3ed | j_mayer | /* XXX: disable buffered write as it's not supported */
|
726 | 95d1f3ed | j_mayer | // pfl->cfi_table[0x2A] = 0x05;
|
727 | 95d1f3ed | j_mayer | pfl->cfi_table[0x2A] = 0x00; |
728 | 29133e9a | bellard | pfl->cfi_table[0x2B] = 0x00; |
729 | 29133e9a | bellard | /* Number of erase block regions (uniform) */
|
730 | 29133e9a | bellard | pfl->cfi_table[0x2C] = 0x01; |
731 | 29133e9a | bellard | /* Erase block region 1 */
|
732 | 29133e9a | bellard | pfl->cfi_table[0x2D] = nb_blocs - 1; |
733 | 29133e9a | bellard | pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
734 | 29133e9a | bellard | pfl->cfi_table[0x2F] = sector_len >> 8; |
735 | 29133e9a | bellard | pfl->cfi_table[0x30] = sector_len >> 16; |
736 | 29133e9a | bellard | |
737 | 78556820 | edgar_igl | /* Extended */
|
738 | 78556820 | edgar_igl | pfl->cfi_table[0x31] = 'P'; |
739 | 78556820 | edgar_igl | pfl->cfi_table[0x32] = 'R'; |
740 | 78556820 | edgar_igl | pfl->cfi_table[0x33] = 'I'; |
741 | 78556820 | edgar_igl | |
742 | 78556820 | edgar_igl | pfl->cfi_table[0x34] = '1'; |
743 | 78556820 | edgar_igl | pfl->cfi_table[0x35] = '0'; |
744 | 78556820 | edgar_igl | |
745 | 78556820 | edgar_igl | pfl->cfi_table[0x36] = 0x00; |
746 | 78556820 | edgar_igl | pfl->cfi_table[0x37] = 0x00; |
747 | 78556820 | edgar_igl | pfl->cfi_table[0x38] = 0x00; |
748 | 78556820 | edgar_igl | pfl->cfi_table[0x39] = 0x00; |
749 | 78556820 | edgar_igl | |
750 | 78556820 | edgar_igl | pfl->cfi_table[0x3a] = 0x00; |
751 | 78556820 | edgar_igl | |
752 | 78556820 | edgar_igl | pfl->cfi_table[0x3b] = 0x00; |
753 | 78556820 | edgar_igl | pfl->cfi_table[0x3c] = 0x00; |
754 | 78556820 | edgar_igl | |
755 | 29133e9a | bellard | return pfl;
|
756 | 29133e9a | bellard | } |