Statistics
| Branch: | Revision:

root / target-arm @ 37952117

Name Size
Makefile.objs 195 Bytes
arm-semi.c 16 kB
cpu-qom.h 3 kB
cpu.c 25.7 kB
cpu.h 26 kB
helper.c 98.5 kB
helper.h 17 kB
iwmmxt_helper.c 24.8 kB
machine.c 7.5 kB
neon_helper.c 52.9 kB
op_addsub.h 1.8 kB
op_helper.c 10.3 kB
translate.c 344.1 kB

Latest revisions

# Date Author Comment
b2d06f96 06/20/2012 03:13 pm Peter Maydell

target-arm: Remove ARM_CPUID_* macros

All the uses of ARM_CPUID() to vary behaviour have now been
removed, so we can delete the ARM_CPUID_* macros now.
The one exception is the TI915T/925T, because of its odd behaviour
where the MIDR value can be changed at runtime....
4a9a539f 06/20/2012 03:13 pm Peter Maydell

target-arm: Remove remaining old cp15 infrastructure

There are now no uses of the old cp15 infrastructure,
so it can be deleted.

Signed-off-by: Peter Maydell <>
30b05bba 06/20/2012 03:12 pm Peter Maydell

target-arm: Move block cache ops to new cp15 framework

Move the v6 optional block cache ops to the new cp15 framework.
This includes only providing them on the CPUs which implemented
them, rather than the previous blunderbuss approach of making
all MCRR instructions on all CPUs act as NOPs....
b22af022 06/20/2012 03:11 pm Peter Maydell

target-arm: Remove c0_cachetype CPUARMState field

Remove the no-longer-used CPUARMState c0_cachetype field.
Although this was a constant register we had it in our
migration state. Drop this (with resulting version bump)
because for ARM currently we prefer cleaner migration...
7884849c 06/20/2012 03:11 pm Peter Maydell

target-arm: Convert final ID registers

Convert the final ID registers to the new cp15 scheme.

Signed-off-by: Peter Maydell <>
81bdde9d 06/20/2012 03:10 pm Peter Maydell

target-arm: Convert MPIDR

Convert the MPIDR to the new cp15 register scheme.
This includes giving it its own feature bit rather
than doing a CPUID value check.

Signed-off-by: Peter Maydell <>
776d4e5c 06/20/2012 03:10 pm Peter Maydell

target-arm: Convert cp15 cache ID registers

Convert the cp15 cache ID registers to the new scheme.

Signed-off-by: Peter Maydell <>
8515a092 06/20/2012 03:09 pm Peter Maydell

target-arm: Convert cp15 crn=0 crm={1,2} feature registers

Convert the cp15 crn=0 crm={1,2} features registers to
the new cp reg framework.

Signed-off-by: Peter Maydell <>
2771db27 06/20/2012 03:08 pm Peter Maydell

target-arm: Convert cp15 crn=1 registers

Convert the cp15 crn=1 registers to the new scheme.

Signed-off-by: Peter Maydell <>
34f90529 06/20/2012 03:08 pm Peter Maydell

target-arm: Convert cp15 crn=9 registers

Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme.

Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is
a change from previous behaviour, but a return to the behaviour of commit...

View revisions

Also available in: Atom