root / hw / sun4u.c @ 37f32f0f
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1 | 3475187d | bellard | /*
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2 | c7ba218d | blueswir1 | * QEMU Sun4u/Sun4v System Emulator
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 18e08a55 | Michael S. Tsirkin | #include "apb_pci.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 87ecb68b | pbrook | #include "nvram.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "net.h" |
31 | 87ecb68b | pbrook | #include "qemu-timer.h" |
32 | 87ecb68b | pbrook | #include "sysemu.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
35 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
36 | 1baffa46 | Blue Swirl | #include "sysbus.h" |
37 | 977e1244 | Gerd Hoffmann | #include "ide.h" |
38 | ca20cf32 | Blue Swirl | #include "loader.h" |
39 | ca20cf32 | Blue Swirl | #include "elf.h" |
40 | 2446333c | Blue Swirl | #include "blockdev.h" |
41 | 39186d8a | Richard Henderson | #include "exec-memory.h" |
42 | 3475187d | bellard | |
43 | 9d926598 | blueswir1 | //#define DEBUG_IRQ
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44 | b430a225 | Blue Swirl | //#define DEBUG_EBUS
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45 | 8f4efc55 | Igor V. Kovalenko | //#define DEBUG_TIMER
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46 | 9d926598 | blueswir1 | |
47 | 9d926598 | blueswir1 | #ifdef DEBUG_IRQ
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48 | b430a225 | Blue Swirl | #define CPUIRQ_DPRINTF(fmt, ...) \
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49 | 001faf32 | Blue Swirl | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
50 | 9d926598 | blueswir1 | #else
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51 | b430a225 | Blue Swirl | #define CPUIRQ_DPRINTF(fmt, ...)
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52 | b430a225 | Blue Swirl | #endif
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53 | b430a225 | Blue Swirl | |
54 | b430a225 | Blue Swirl | #ifdef DEBUG_EBUS
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55 | b430a225 | Blue Swirl | #define EBUS_DPRINTF(fmt, ...) \
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56 | b430a225 | Blue Swirl | do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) |
57 | b430a225 | Blue Swirl | #else
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58 | b430a225 | Blue Swirl | #define EBUS_DPRINTF(fmt, ...)
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59 | 9d926598 | blueswir1 | #endif
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60 | 9d926598 | blueswir1 | |
61 | 8f4efc55 | Igor V. Kovalenko | #ifdef DEBUG_TIMER
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62 | 8f4efc55 | Igor V. Kovalenko | #define TIMER_DPRINTF(fmt, ...) \
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63 | 8f4efc55 | Igor V. Kovalenko | do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) |
64 | 8f4efc55 | Igor V. Kovalenko | #else
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65 | 8f4efc55 | Igor V. Kovalenko | #define TIMER_DPRINTF(fmt, ...)
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66 | 8f4efc55 | Igor V. Kovalenko | #endif
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67 | 8f4efc55 | Igor V. Kovalenko | |
68 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
69 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
70 | 83469015 | bellard | #define INITRD_LOAD_ADDR 0x00300000 |
71 | ac2e9d66 | blueswir1 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
72 | f930d07e | blueswir1 | #define PROM_VADDR 0x000ffd00000ULL |
73 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
74 | f930d07e | blueswir1 | #define APB_MEM_BASE 0x1ff00000000ULL |
75 | d63baf92 | Igor V. Kovalenko | #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) |
76 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc64" |
77 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
78 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
79 | 3cce6243 | blueswir1 | #define BIOS_CFG_IOPORT 0x510 |
80 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
81 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
82 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
83 | 3475187d | bellard | |
84 | 9d926598 | blueswir1 | #define MAX_PILS 16 |
85 | 9d926598 | blueswir1 | |
86 | 8fa211e8 | blueswir1 | #define TICK_MAX 0x7fffffffffffffffULL |
87 | 8fa211e8 | blueswir1 | |
88 | c7ba218d | blueswir1 | struct hwdef {
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89 | c7ba218d | blueswir1 | const char * const default_cpu_model; |
90 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
91 | e87231d4 | blueswir1 | uint64_t prom_addr; |
92 | e87231d4 | blueswir1 | uint64_t console_serial_base; |
93 | c7ba218d | blueswir1 | }; |
94 | c7ba218d | blueswir1 | |
95 | c5e6fb7e | Avi Kivity | typedef struct EbusState { |
96 | c5e6fb7e | Avi Kivity | PCIDevice pci_dev; |
97 | c5e6fb7e | Avi Kivity | MemoryRegion bar0; |
98 | c5e6fb7e | Avi Kivity | MemoryRegion bar1; |
99 | c5e6fb7e | Avi Kivity | } EbusState; |
100 | c5e6fb7e | Avi Kivity | |
101 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
102 | 3475187d | bellard | { |
103 | 3475187d | bellard | return 0; |
104 | 3475187d | bellard | } |
105 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
106 | 3475187d | bellard | { |
107 | 3475187d | bellard | return 0; |
108 | 3475187d | bellard | } |
109 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
110 | 3475187d | bellard | { |
111 | 3475187d | bellard | return 0; |
112 | 3475187d | bellard | } |
113 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
114 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
115 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
116 | 4556bd8b | Blue Swirl | |
117 | 4556bd8b | Blue Swirl | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
118 | 4556bd8b | Blue Swirl | { |
119 | 4556bd8b | Blue Swirl | } |
120 | 4556bd8b | Blue Swirl | |
121 | 3475187d | bellard | void DMA_register_channel (int nchan, |
122 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
123 | 3475187d | bellard | void *opaque)
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124 | 3475187d | bellard | { |
125 | 3475187d | bellard | } |
126 | 3475187d | bellard | |
127 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
128 | 81864572 | blueswir1 | { |
129 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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130 | 81864572 | blueswir1 | return 0; |
131 | 81864572 | blueswir1 | } |
132 | 81864572 | blueswir1 | |
133 | 43a34704 | Blue Swirl | static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size, |
134 | 43a34704 | Blue Swirl | const char *arch, ram_addr_t RAM_size, |
135 | 43a34704 | Blue Swirl | const char *boot_devices, |
136 | 43a34704 | Blue Swirl | uint32_t kernel_image, uint32_t kernel_size, |
137 | 43a34704 | Blue Swirl | const char *cmdline, |
138 | 43a34704 | Blue Swirl | uint32_t initrd_image, uint32_t initrd_size, |
139 | 43a34704 | Blue Swirl | uint32_t NVRAM_image, |
140 | 43a34704 | Blue Swirl | int width, int height, int depth, |
141 | 43a34704 | Blue Swirl | const uint8_t *macaddr)
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142 | 83469015 | bellard | { |
143 | 66508601 | blueswir1 | unsigned int i; |
144 | 66508601 | blueswir1 | uint32_t start, end; |
145 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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146 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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147 | d2c63fc1 | blueswir1 | |
148 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
149 | d2c63fc1 | blueswir1 | |
150 | 513f789f | blueswir1 | start = 0;
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151 | 83469015 | bellard | |
152 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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153 | 66508601 | blueswir1 | // Variable partition
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154 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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155 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
156 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
157 | 66508601 | blueswir1 | |
158 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
159 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
160 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
161 | d2c63fc1 | blueswir1 | |
162 | d2c63fc1 | blueswir1 | // End marker
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163 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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164 | 66508601 | blueswir1 | |
165 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
166 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
167 | 66508601 | blueswir1 | |
168 | 66508601 | blueswir1 | // free partition
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169 | 66508601 | blueswir1 | start = end; |
170 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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171 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
172 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
173 | 66508601 | blueswir1 | |
174 | 66508601 | blueswir1 | end = 0x1fd0;
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175 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
176 | d2c63fc1 | blueswir1 | |
177 | 0d31cb99 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
178 | 0d31cb99 | blueswir1 | |
179 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
180 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
181 | 66508601 | blueswir1 | |
182 | 83469015 | bellard | return 0; |
183 | 3475187d | bellard | } |
184 | 636aa70a | Blue Swirl | static unsigned long sun4u_load_kernel(const char *kernel_filename, |
185 | 636aa70a | Blue Swirl | const char *initrd_filename, |
186 | c227f099 | Anthony Liguori | ram_addr_t RAM_size, long *initrd_size)
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187 | 636aa70a | Blue Swirl | { |
188 | 636aa70a | Blue Swirl | int linux_boot;
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189 | 636aa70a | Blue Swirl | unsigned int i; |
190 | 636aa70a | Blue Swirl | long kernel_size;
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191 | 6908d9ce | Blue Swirl | uint8_t *ptr; |
192 | 636aa70a | Blue Swirl | |
193 | 636aa70a | Blue Swirl | linux_boot = (kernel_filename != NULL);
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194 | 636aa70a | Blue Swirl | |
195 | 636aa70a | Blue Swirl | kernel_size = 0;
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196 | 636aa70a | Blue Swirl | if (linux_boot) {
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197 | ca20cf32 | Blue Swirl | int bswap_needed;
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198 | ca20cf32 | Blue Swirl | |
199 | ca20cf32 | Blue Swirl | #ifdef BSWAP_NEEDED
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200 | ca20cf32 | Blue Swirl | bswap_needed = 1;
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201 | ca20cf32 | Blue Swirl | #else
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202 | ca20cf32 | Blue Swirl | bswap_needed = 0;
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203 | ca20cf32 | Blue Swirl | #endif
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204 | 409dbce5 | Aurelien Jarno | kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, |
205 | 409dbce5 | Aurelien Jarno | NULL, NULL, 1, ELF_MACHINE, 0); |
206 | 636aa70a | Blue Swirl | if (kernel_size < 0) |
207 | 636aa70a | Blue Swirl | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
208 | ca20cf32 | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
209 | ca20cf32 | Blue Swirl | TARGET_PAGE_SIZE); |
210 | 636aa70a | Blue Swirl | if (kernel_size < 0) |
211 | 636aa70a | Blue Swirl | kernel_size = load_image_targphys(kernel_filename, |
212 | 636aa70a | Blue Swirl | KERNEL_LOAD_ADDR, |
213 | 636aa70a | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR); |
214 | 636aa70a | Blue Swirl | if (kernel_size < 0) { |
215 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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216 | 636aa70a | Blue Swirl | kernel_filename); |
217 | 636aa70a | Blue Swirl | exit(1);
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218 | 636aa70a | Blue Swirl | } |
219 | 636aa70a | Blue Swirl | |
220 | 636aa70a | Blue Swirl | /* load initrd */
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221 | 636aa70a | Blue Swirl | *initrd_size = 0;
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222 | 636aa70a | Blue Swirl | if (initrd_filename) {
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223 | 636aa70a | Blue Swirl | *initrd_size = load_image_targphys(initrd_filename, |
224 | 636aa70a | Blue Swirl | INITRD_LOAD_ADDR, |
225 | 636aa70a | Blue Swirl | RAM_size - INITRD_LOAD_ADDR); |
226 | 636aa70a | Blue Swirl | if (*initrd_size < 0) { |
227 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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228 | 636aa70a | Blue Swirl | initrd_filename); |
229 | 636aa70a | Blue Swirl | exit(1);
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230 | 636aa70a | Blue Swirl | } |
231 | 636aa70a | Blue Swirl | } |
232 | 636aa70a | Blue Swirl | if (*initrd_size > 0) { |
233 | 636aa70a | Blue Swirl | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
234 | 6908d9ce | Blue Swirl | ptr = rom_ptr(KERNEL_LOAD_ADDR + i); |
235 | 6908d9ce | Blue Swirl | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
236 | 6908d9ce | Blue Swirl | stl_p(ptr + 24, INITRD_LOAD_ADDR + KERNEL_LOAD_ADDR - 0x4000); |
237 | 6908d9ce | Blue Swirl | stl_p(ptr + 28, *initrd_size);
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238 | 636aa70a | Blue Swirl | break;
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239 | 636aa70a | Blue Swirl | } |
240 | 636aa70a | Blue Swirl | } |
241 | 636aa70a | Blue Swirl | } |
242 | 636aa70a | Blue Swirl | } |
243 | 636aa70a | Blue Swirl | return kernel_size;
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244 | 636aa70a | Blue Swirl | } |
245 | 3475187d | bellard | |
246 | 9d926598 | blueswir1 | void cpu_check_irqs(CPUState *env)
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247 | 9d926598 | blueswir1 | { |
248 | d532b26c | Igor V. Kovalenko | uint32_t pil = env->pil_in | |
249 | d532b26c | Igor V. Kovalenko | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); |
250 | d532b26c | Igor V. Kovalenko | |
251 | d532b26c | Igor V. Kovalenko | /* check if TM or SM in SOFTINT are set
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252 | d532b26c | Igor V. Kovalenko | setting these also causes interrupt 14 */
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253 | d532b26c | Igor V. Kovalenko | if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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254 | d532b26c | Igor V. Kovalenko | pil |= 1 << 14; |
255 | d532b26c | Igor V. Kovalenko | } |
256 | d532b26c | Igor V. Kovalenko | |
257 | 9f94778c | Artyom Tarasenko | /* The bit corresponding to psrpil is (1<< psrpil), the next bit
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258 | 9f94778c | Artyom Tarasenko | is (2 << psrpil). */
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259 | 9f94778c | Artyom Tarasenko | if (pil < (2 << env->psrpil)){ |
260 | d532b26c | Igor V. Kovalenko | if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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261 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
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262 | d532b26c | Igor V. Kovalenko | env->interrupt_index); |
263 | d532b26c | Igor V. Kovalenko | env->interrupt_index = 0;
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264 | d532b26c | Igor V. Kovalenko | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
265 | d532b26c | Igor V. Kovalenko | } |
266 | d532b26c | Igor V. Kovalenko | return;
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267 | d532b26c | Igor V. Kovalenko | } |
268 | d532b26c | Igor V. Kovalenko | |
269 | d532b26c | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
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270 | 9d926598 | blueswir1 | |
271 | 9d926598 | blueswir1 | unsigned int i; |
272 | 9d926598 | blueswir1 | |
273 | d532b26c | Igor V. Kovalenko | for (i = 15; i > env->psrpil; i--) { |
274 | 9d926598 | blueswir1 | if (pil & (1 << i)) { |
275 | 9d926598 | blueswir1 | int old_interrupt = env->interrupt_index;
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276 | d532b26c | Igor V. Kovalenko | int new_interrupt = TT_EXTINT | i;
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277 | d532b26c | Igor V. Kovalenko | |
278 | d532b26c | Igor V. Kovalenko | if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) { |
279 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
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280 | d532b26c | Igor V. Kovalenko | "current %x >= pending %x\n",
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281 | d532b26c | Igor V. Kovalenko | env->tl, cpu_tsptr(env)->tt, new_interrupt); |
282 | d532b26c | Igor V. Kovalenko | } else if (old_interrupt != new_interrupt) { |
283 | d532b26c | Igor V. Kovalenko | env->interrupt_index = new_interrupt; |
284 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
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285 | d532b26c | Igor V. Kovalenko | old_interrupt, new_interrupt); |
286 | 9d926598 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
287 | 9d926598 | blueswir1 | } |
288 | 9d926598 | blueswir1 | break;
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289 | 9d926598 | blueswir1 | } |
290 | 9d926598 | blueswir1 | } |
291 | 9f94778c | Artyom Tarasenko | } else if (env->interrupt_request & CPU_INTERRUPT_HARD) { |
292 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
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293 | d532b26c | Igor V. Kovalenko | "current interrupt %x\n",
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294 | d532b26c | Igor V. Kovalenko | pil, env->pil_in, env->softint, env->interrupt_index); |
295 | 9f94778c | Artyom Tarasenko | env->interrupt_index = 0;
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296 | 9f94778c | Artyom Tarasenko | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
297 | 9d926598 | blueswir1 | } |
298 | 9d926598 | blueswir1 | } |
299 | 9d926598 | blueswir1 | |
300 | 8f4efc55 | Igor V. Kovalenko | static void cpu_kick_irq(CPUState *env) |
301 | 8f4efc55 | Igor V. Kovalenko | { |
302 | 8f4efc55 | Igor V. Kovalenko | env->halted = 0;
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303 | 8f4efc55 | Igor V. Kovalenko | cpu_check_irqs(env); |
304 | 94ad5b00 | Paolo Bonzini | qemu_cpu_kick(env); |
305 | 8f4efc55 | Igor V. Kovalenko | } |
306 | 8f4efc55 | Igor V. Kovalenko | |
307 | 9d926598 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
308 | 9d926598 | blueswir1 | { |
309 | 9d926598 | blueswir1 | CPUState *env = opaque; |
310 | 9d926598 | blueswir1 | |
311 | 9d926598 | blueswir1 | if (level) {
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312 | b430a225 | Blue Swirl | CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
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313 | 9d926598 | blueswir1 | env->pil_in |= 1 << irq;
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314 | 94ad5b00 | Paolo Bonzini | cpu_kick_irq(env); |
315 | 9d926598 | blueswir1 | } else {
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316 | b430a225 | Blue Swirl | CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
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317 | 9d926598 | blueswir1 | env->pil_in &= ~(1 << irq);
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318 | 9d926598 | blueswir1 | cpu_check_irqs(env); |
319 | 9d926598 | blueswir1 | } |
320 | 9d926598 | blueswir1 | } |
321 | 9d926598 | blueswir1 | |
322 | e87231d4 | blueswir1 | typedef struct ResetData { |
323 | e87231d4 | blueswir1 | CPUState *env; |
324 | 44a99354 | Blue Swirl | uint64_t prom_addr; |
325 | e87231d4 | blueswir1 | } ResetData; |
326 | e87231d4 | blueswir1 | |
327 | 8f4efc55 | Igor V. Kovalenko | void cpu_put_timer(QEMUFile *f, CPUTimer *s)
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328 | 8f4efc55 | Igor V. Kovalenko | { |
329 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be32s(f, &s->frequency); |
330 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be32s(f, &s->disabled); |
331 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be64s(f, &s->disabled_mask); |
332 | 8f4efc55 | Igor V. Kovalenko | qemu_put_sbe64s(f, &s->clock_offset); |
333 | 8f4efc55 | Igor V. Kovalenko | |
334 | 8f4efc55 | Igor V. Kovalenko | qemu_put_timer(f, s->qtimer); |
335 | 8f4efc55 | Igor V. Kovalenko | } |
336 | 8f4efc55 | Igor V. Kovalenko | |
337 | 8f4efc55 | Igor V. Kovalenko | void cpu_get_timer(QEMUFile *f, CPUTimer *s)
|
338 | 8f4efc55 | Igor V. Kovalenko | { |
339 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be32s(f, &s->frequency); |
340 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be32s(f, &s->disabled); |
341 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be64s(f, &s->disabled_mask); |
342 | 8f4efc55 | Igor V. Kovalenko | qemu_get_sbe64s(f, &s->clock_offset); |
343 | 8f4efc55 | Igor V. Kovalenko | |
344 | 8f4efc55 | Igor V. Kovalenko | qemu_get_timer(f, s->qtimer); |
345 | 8f4efc55 | Igor V. Kovalenko | } |
346 | 8f4efc55 | Igor V. Kovalenko | |
347 | 8f4efc55 | Igor V. Kovalenko | static CPUTimer* cpu_timer_create(const char* name, CPUState *env, |
348 | 8f4efc55 | Igor V. Kovalenko | QEMUBHFunc *cb, uint32_t frequency, |
349 | 8f4efc55 | Igor V. Kovalenko | uint64_t disabled_mask) |
350 | 8f4efc55 | Igor V. Kovalenko | { |
351 | 7267c094 | Anthony Liguori | CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
|
352 | 8f4efc55 | Igor V. Kovalenko | |
353 | 8f4efc55 | Igor V. Kovalenko | timer->name = name; |
354 | 8f4efc55 | Igor V. Kovalenko | timer->frequency = frequency; |
355 | 8f4efc55 | Igor V. Kovalenko | timer->disabled_mask = disabled_mask; |
356 | 8f4efc55 | Igor V. Kovalenko | |
357 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = 1;
|
358 | 74475455 | Paolo Bonzini | timer->clock_offset = qemu_get_clock_ns(vm_clock); |
359 | 8f4efc55 | Igor V. Kovalenko | |
360 | 74475455 | Paolo Bonzini | timer->qtimer = qemu_new_timer_ns(vm_clock, cb, env); |
361 | 8f4efc55 | Igor V. Kovalenko | |
362 | 8f4efc55 | Igor V. Kovalenko | return timer;
|
363 | 8f4efc55 | Igor V. Kovalenko | } |
364 | 8f4efc55 | Igor V. Kovalenko | |
365 | 8f4efc55 | Igor V. Kovalenko | static void cpu_timer_reset(CPUTimer *timer) |
366 | 8f4efc55 | Igor V. Kovalenko | { |
367 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = 1;
|
368 | 74475455 | Paolo Bonzini | timer->clock_offset = qemu_get_clock_ns(vm_clock); |
369 | 8f4efc55 | Igor V. Kovalenko | |
370 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
371 | 8f4efc55 | Igor V. Kovalenko | } |
372 | 8f4efc55 | Igor V. Kovalenko | |
373 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
374 | c68ea704 | bellard | { |
375 | e87231d4 | blueswir1 | ResetData *s = (ResetData *)opaque; |
376 | e87231d4 | blueswir1 | CPUState *env = s->env; |
377 | 44a99354 | Blue Swirl | static unsigned int nr_resets; |
378 | 20c9f095 | blueswir1 | |
379 | c68ea704 | bellard | cpu_reset(env); |
380 | 8f4efc55 | Igor V. Kovalenko | |
381 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->tick); |
382 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->stick); |
383 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->hstick); |
384 | 8f4efc55 | Igor V. Kovalenko | |
385 | e87231d4 | blueswir1 | env->gregs[1] = 0; // Memory start |
386 | e87231d4 | blueswir1 | env->gregs[2] = ram_size; // Memory size |
387 | e87231d4 | blueswir1 | env->gregs[3] = 0; // Machine description XXX |
388 | 44a99354 | Blue Swirl | if (nr_resets++ == 0) { |
389 | 44a99354 | Blue Swirl | /* Power on reset */
|
390 | 44a99354 | Blue Swirl | env->pc = s->prom_addr + 0x20ULL;
|
391 | 44a99354 | Blue Swirl | } else {
|
392 | 44a99354 | Blue Swirl | env->pc = s->prom_addr + 0x40ULL;
|
393 | 44a99354 | Blue Swirl | } |
394 | e87231d4 | blueswir1 | env->npc = env->pc + 4;
|
395 | 20c9f095 | blueswir1 | } |
396 | 20c9f095 | blueswir1 | |
397 | 22548760 | blueswir1 | static void tick_irq(void *opaque) |
398 | 20c9f095 | blueswir1 | { |
399 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
400 | 20c9f095 | blueswir1 | |
401 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->tick; |
402 | 8f4efc55 | Igor V. Kovalenko | |
403 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
404 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
|
405 | 8f4efc55 | Igor V. Kovalenko | return;
|
406 | 8f4efc55 | Igor V. Kovalenko | } else {
|
407 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("tick: fire\n");
|
408 | 8fa211e8 | blueswir1 | } |
409 | 8f4efc55 | Igor V. Kovalenko | |
410 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_TIMER; |
411 | 8f4efc55 | Igor V. Kovalenko | cpu_kick_irq(env); |
412 | 20c9f095 | blueswir1 | } |
413 | 20c9f095 | blueswir1 | |
414 | 22548760 | blueswir1 | static void stick_irq(void *opaque) |
415 | 20c9f095 | blueswir1 | { |
416 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
417 | 20c9f095 | blueswir1 | |
418 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->stick; |
419 | 8f4efc55 | Igor V. Kovalenko | |
420 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
421 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
|
422 | 8f4efc55 | Igor V. Kovalenko | return;
|
423 | 8f4efc55 | Igor V. Kovalenko | } else {
|
424 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("stick: fire\n");
|
425 | 8fa211e8 | blueswir1 | } |
426 | 8f4efc55 | Igor V. Kovalenko | |
427 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_STIMER; |
428 | 8f4efc55 | Igor V. Kovalenko | cpu_kick_irq(env); |
429 | 20c9f095 | blueswir1 | } |
430 | 20c9f095 | blueswir1 | |
431 | 22548760 | blueswir1 | static void hstick_irq(void *opaque) |
432 | 20c9f095 | blueswir1 | { |
433 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
434 | 20c9f095 | blueswir1 | |
435 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->hstick; |
436 | 8f4efc55 | Igor V. Kovalenko | |
437 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
438 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
|
439 | 8f4efc55 | Igor V. Kovalenko | return;
|
440 | 8f4efc55 | Igor V. Kovalenko | } else {
|
441 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("hstick: fire\n");
|
442 | 8fa211e8 | blueswir1 | } |
443 | 8f4efc55 | Igor V. Kovalenko | |
444 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_STIMER; |
445 | 8f4efc55 | Igor V. Kovalenko | cpu_kick_irq(env); |
446 | 8f4efc55 | Igor V. Kovalenko | } |
447 | 8f4efc55 | Igor V. Kovalenko | |
448 | 8f4efc55 | Igor V. Kovalenko | static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
|
449 | 8f4efc55 | Igor V. Kovalenko | { |
450 | 8f4efc55 | Igor V. Kovalenko | return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
|
451 | 8f4efc55 | Igor V. Kovalenko | } |
452 | 8f4efc55 | Igor V. Kovalenko | |
453 | 8f4efc55 | Igor V. Kovalenko | static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
|
454 | 8f4efc55 | Igor V. Kovalenko | { |
455 | 8f4efc55 | Igor V. Kovalenko | return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
|
456 | c68ea704 | bellard | } |
457 | c68ea704 | bellard | |
458 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
|
459 | f4b1a842 | blueswir1 | { |
460 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_count = count & ~timer->disabled_mask; |
461 | 8f4efc55 | Igor V. Kovalenko | uint64_t disabled_bit = count & timer->disabled_mask; |
462 | 8f4efc55 | Igor V. Kovalenko | |
463 | 74475455 | Paolo Bonzini | int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) - |
464 | 8f4efc55 | Igor V. Kovalenko | cpu_to_timer_ticks(real_count, timer->frequency); |
465 | 8f4efc55 | Igor V. Kovalenko | |
466 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
|
467 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_count, |
468 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", timer); |
469 | 8f4efc55 | Igor V. Kovalenko | |
470 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = disabled_bit ? 1 : 0; |
471 | 8f4efc55 | Igor V. Kovalenko | timer->clock_offset = vm_clock_offset; |
472 | f4b1a842 | blueswir1 | } |
473 | f4b1a842 | blueswir1 | |
474 | 8f4efc55 | Igor V. Kovalenko | uint64_t cpu_tick_get_count(CPUTimer *timer) |
475 | f4b1a842 | blueswir1 | { |
476 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_count = timer_to_cpu_ticks( |
477 | 74475455 | Paolo Bonzini | qemu_get_clock_ns(vm_clock) - timer->clock_offset, |
478 | 8f4efc55 | Igor V. Kovalenko | timer->frequency); |
479 | 8f4efc55 | Igor V. Kovalenko | |
480 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
|
481 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_count, |
482 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", timer); |
483 | 8f4efc55 | Igor V. Kovalenko | |
484 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled)
|
485 | 8f4efc55 | Igor V. Kovalenko | real_count |= timer->disabled_mask; |
486 | 8f4efc55 | Igor V. Kovalenko | |
487 | 8f4efc55 | Igor V. Kovalenko | return real_count;
|
488 | f4b1a842 | blueswir1 | } |
489 | f4b1a842 | blueswir1 | |
490 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
|
491 | f4b1a842 | blueswir1 | { |
492 | 74475455 | Paolo Bonzini | int64_t now = qemu_get_clock_ns(vm_clock); |
493 | 8f4efc55 | Igor V. Kovalenko | |
494 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_limit = limit & ~timer->disabled_mask; |
495 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; |
496 | 8f4efc55 | Igor V. Kovalenko | |
497 | 8f4efc55 | Igor V. Kovalenko | int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + |
498 | 8f4efc55 | Igor V. Kovalenko | timer->clock_offset; |
499 | 8f4efc55 | Igor V. Kovalenko | |
500 | 8f4efc55 | Igor V. Kovalenko | if (expires < now) {
|
501 | 8f4efc55 | Igor V. Kovalenko | expires = now + 1;
|
502 | 8f4efc55 | Igor V. Kovalenko | } |
503 | 8f4efc55 | Igor V. Kovalenko | |
504 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
|
505 | 8f4efc55 | Igor V. Kovalenko | "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
|
506 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_limit, |
507 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", |
508 | 8f4efc55 | Igor V. Kovalenko | timer, limit, |
509 | 8f4efc55 | Igor V. Kovalenko | timer_to_cpu_ticks(now - timer->clock_offset, |
510 | 8f4efc55 | Igor V. Kovalenko | timer->frequency), |
511 | 8f4efc55 | Igor V. Kovalenko | timer_to_cpu_ticks(expires - now, timer->frequency)); |
512 | 8f4efc55 | Igor V. Kovalenko | |
513 | 8f4efc55 | Igor V. Kovalenko | if (!real_limit) {
|
514 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
|
515 | 8f4efc55 | Igor V. Kovalenko | timer->name); |
516 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
517 | 8f4efc55 | Igor V. Kovalenko | } else if (timer->disabled) { |
518 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
519 | 8f4efc55 | Igor V. Kovalenko | } else {
|
520 | 8f4efc55 | Igor V. Kovalenko | qemu_mod_timer(timer->qtimer, expires); |
521 | 8f4efc55 | Igor V. Kovalenko | } |
522 | f4b1a842 | blueswir1 | } |
523 | f4b1a842 | blueswir1 | |
524 | 1387fe4a | Blue Swirl | static void dummy_isa_irq_handler(void *opaque, int n, int level) |
525 | 1387fe4a | Blue Swirl | { |
526 | 1387fe4a | Blue Swirl | } |
527 | 1387fe4a | Blue Swirl | |
528 | c190ea07 | blueswir1 | /* EBUS (Eight bit bus) bridge */
|
529 | 48a18b3c | Hervé Poussineau | static ISABus *
|
530 | c190ea07 | blueswir1 | pci_ebus_init(PCIBus *bus, int devfn)
|
531 | c190ea07 | blueswir1 | { |
532 | 1387fe4a | Blue Swirl | qemu_irq *isa_irq; |
533 | ab953e28 | Hervé Poussineau | PCIDevice *pci_dev; |
534 | 48a18b3c | Hervé Poussineau | ISABus *isa_bus; |
535 | 1387fe4a | Blue Swirl | |
536 | ab953e28 | Hervé Poussineau | pci_dev = pci_create_simple(bus, devfn, "ebus");
|
537 | ab953e28 | Hervé Poussineau | isa_bus = DO_UPCAST(ISABus, qbus, |
538 | ab953e28 | Hervé Poussineau | qdev_get_child_bus(&pci_dev->qdev, "isa.0"));
|
539 | 1387fe4a | Blue Swirl | isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16); |
540 | 48a18b3c | Hervé Poussineau | isa_bus_irqs(isa_bus, isa_irq); |
541 | 48a18b3c | Hervé Poussineau | return isa_bus;
|
542 | 53e3c4f9 | Blue Swirl | } |
543 | c190ea07 | blueswir1 | |
544 | 81a322d4 | Gerd Hoffmann | static int |
545 | c5e6fb7e | Avi Kivity | pci_ebus_init1(PCIDevice *pci_dev) |
546 | 53e3c4f9 | Blue Swirl | { |
547 | c5e6fb7e | Avi Kivity | EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); |
548 | c5e6fb7e | Avi Kivity | |
549 | c2d0d012 | Richard Henderson | isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev)); |
550 | c5e6fb7e | Avi Kivity | |
551 | c5e6fb7e | Avi Kivity | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem |
552 | c5e6fb7e | Avi Kivity | pci_dev->config[0x05] = 0x00; |
553 | c5e6fb7e | Avi Kivity | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
554 | c5e6fb7e | Avi Kivity | pci_dev->config[0x07] = 0x03; // status = medium devsel |
555 | c5e6fb7e | Avi Kivity | pci_dev->config[0x09] = 0x00; // programming i/f |
556 | c5e6fb7e | Avi Kivity | pci_dev->config[0x0D] = 0x0a; // latency_timer |
557 | c5e6fb7e | Avi Kivity | |
558 | c5e6fb7e | Avi Kivity | isa_mmio_setup(&s->bar0, 0x1000000);
|
559 | e824b2cc | Avi Kivity | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
|
560 | c5e6fb7e | Avi Kivity | isa_mmio_setup(&s->bar1, 0x800000);
|
561 | e824b2cc | Avi Kivity | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
|
562 | 81a322d4 | Gerd Hoffmann | return 0; |
563 | c190ea07 | blueswir1 | } |
564 | c190ea07 | blueswir1 | |
565 | 40021f08 | Anthony Liguori | static void ebus_class_init(ObjectClass *klass, void *data) |
566 | 40021f08 | Anthony Liguori | { |
567 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
568 | 40021f08 | Anthony Liguori | |
569 | 40021f08 | Anthony Liguori | k->init = pci_ebus_init1; |
570 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_SUN; |
571 | 40021f08 | Anthony Liguori | k->device_id = PCI_DEVICE_ID_SUN_EBUS; |
572 | 40021f08 | Anthony Liguori | k->revision = 0x01;
|
573 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_BRIDGE_OTHER; |
574 | 40021f08 | Anthony Liguori | } |
575 | 40021f08 | Anthony Liguori | |
576 | 39bffca2 | Anthony Liguori | static TypeInfo ebus_info = {
|
577 | 39bffca2 | Anthony Liguori | .name = "ebus",
|
578 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
579 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(EbusState),
|
580 | 39bffca2 | Anthony Liguori | .class_init = ebus_class_init, |
581 | 53e3c4f9 | Blue Swirl | }; |
582 | 53e3c4f9 | Blue Swirl | |
583 | 53e3c4f9 | Blue Swirl | static void pci_ebus_register(void) |
584 | 53e3c4f9 | Blue Swirl | { |
585 | 39bffca2 | Anthony Liguori | type_register_static(&ebus_info); |
586 | 53e3c4f9 | Blue Swirl | } |
587 | 53e3c4f9 | Blue Swirl | |
588 | 53e3c4f9 | Blue Swirl | device_init(pci_ebus_register); |
589 | 53e3c4f9 | Blue Swirl | |
590 | d4edce38 | Avi Kivity | typedef struct PROMState { |
591 | d4edce38 | Avi Kivity | SysBusDevice busdev; |
592 | d4edce38 | Avi Kivity | MemoryRegion prom; |
593 | d4edce38 | Avi Kivity | } PROMState; |
594 | d4edce38 | Avi Kivity | |
595 | 409dbce5 | Aurelien Jarno | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
596 | 409dbce5 | Aurelien Jarno | { |
597 | 409dbce5 | Aurelien Jarno | target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque; |
598 | 409dbce5 | Aurelien Jarno | return addr + *base_addr - PROM_VADDR;
|
599 | 409dbce5 | Aurelien Jarno | } |
600 | 409dbce5 | Aurelien Jarno | |
601 | 1baffa46 | Blue Swirl | /* Boot PROM (OpenBIOS) */
|
602 | c227f099 | Anthony Liguori | static void prom_init(target_phys_addr_t addr, const char *bios_name) |
603 | 1baffa46 | Blue Swirl | { |
604 | 1baffa46 | Blue Swirl | DeviceState *dev; |
605 | 1baffa46 | Blue Swirl | SysBusDevice *s; |
606 | 1baffa46 | Blue Swirl | char *filename;
|
607 | 1baffa46 | Blue Swirl | int ret;
|
608 | 1baffa46 | Blue Swirl | |
609 | 1baffa46 | Blue Swirl | dev = qdev_create(NULL, "openprom"); |
610 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
611 | 1baffa46 | Blue Swirl | s = sysbus_from_qdev(dev); |
612 | 1baffa46 | Blue Swirl | |
613 | 1baffa46 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
614 | 1baffa46 | Blue Swirl | |
615 | 1baffa46 | Blue Swirl | /* load boot prom */
|
616 | 1baffa46 | Blue Swirl | if (bios_name == NULL) { |
617 | 1baffa46 | Blue Swirl | bios_name = PROM_FILENAME; |
618 | 1baffa46 | Blue Swirl | } |
619 | 1baffa46 | Blue Swirl | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
620 | 1baffa46 | Blue Swirl | if (filename) {
|
621 | 409dbce5 | Aurelien Jarno | ret = load_elf(filename, translate_prom_address, &addr, |
622 | 409dbce5 | Aurelien Jarno | NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
623 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
624 | 1baffa46 | Blue Swirl | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
625 | 1baffa46 | Blue Swirl | } |
626 | 7267c094 | Anthony Liguori | g_free(filename); |
627 | 1baffa46 | Blue Swirl | } else {
|
628 | 1baffa46 | Blue Swirl | ret = -1;
|
629 | 1baffa46 | Blue Swirl | } |
630 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
631 | 1baffa46 | Blue Swirl | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
632 | 1baffa46 | Blue Swirl | exit(1);
|
633 | 1baffa46 | Blue Swirl | } |
634 | 1baffa46 | Blue Swirl | } |
635 | 1baffa46 | Blue Swirl | |
636 | 81a322d4 | Gerd Hoffmann | static int prom_init1(SysBusDevice *dev) |
637 | 1baffa46 | Blue Swirl | { |
638 | d4edce38 | Avi Kivity | PROMState *s = FROM_SYSBUS(PROMState, dev); |
639 | 1baffa46 | Blue Swirl | |
640 | c5705a77 | Avi Kivity | memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX);
|
641 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&s->prom); |
642 | d4edce38 | Avi Kivity | memory_region_set_readonly(&s->prom, true);
|
643 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->prom); |
644 | 81a322d4 | Gerd Hoffmann | return 0; |
645 | 1baffa46 | Blue Swirl | } |
646 | 1baffa46 | Blue Swirl | |
647 | 999e12bb | Anthony Liguori | static Property prom_properties[] = {
|
648 | 999e12bb | Anthony Liguori | {/* end of property list */},
|
649 | 999e12bb | Anthony Liguori | }; |
650 | 999e12bb | Anthony Liguori | |
651 | 999e12bb | Anthony Liguori | static void prom_class_init(ObjectClass *klass, void *data) |
652 | 999e12bb | Anthony Liguori | { |
653 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
654 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
655 | 999e12bb | Anthony Liguori | |
656 | 999e12bb | Anthony Liguori | k->init = prom_init1; |
657 | 39bffca2 | Anthony Liguori | dc->props = prom_properties; |
658 | 999e12bb | Anthony Liguori | } |
659 | 999e12bb | Anthony Liguori | |
660 | 39bffca2 | Anthony Liguori | static TypeInfo prom_info = {
|
661 | 39bffca2 | Anthony Liguori | .name = "openprom",
|
662 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
663 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PROMState),
|
664 | 39bffca2 | Anthony Liguori | .class_init = prom_class_init, |
665 | 1baffa46 | Blue Swirl | }; |
666 | 1baffa46 | Blue Swirl | |
667 | 1baffa46 | Blue Swirl | static void prom_register_devices(void) |
668 | 1baffa46 | Blue Swirl | { |
669 | 39bffca2 | Anthony Liguori | type_register_static(&prom_info); |
670 | 1baffa46 | Blue Swirl | } |
671 | 1baffa46 | Blue Swirl | |
672 | 1baffa46 | Blue Swirl | device_init(prom_register_devices); |
673 | 1baffa46 | Blue Swirl | |
674 | bda42033 | Blue Swirl | |
675 | bda42033 | Blue Swirl | typedef struct RamDevice |
676 | bda42033 | Blue Swirl | { |
677 | bda42033 | Blue Swirl | SysBusDevice busdev; |
678 | d4edce38 | Avi Kivity | MemoryRegion ram; |
679 | 04843626 | Blue Swirl | uint64_t size; |
680 | bda42033 | Blue Swirl | } RamDevice; |
681 | bda42033 | Blue Swirl | |
682 | bda42033 | Blue Swirl | /* System RAM */
|
683 | 81a322d4 | Gerd Hoffmann | static int ram_init1(SysBusDevice *dev) |
684 | bda42033 | Blue Swirl | { |
685 | bda42033 | Blue Swirl | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
686 | bda42033 | Blue Swirl | |
687 | c5705a77 | Avi Kivity | memory_region_init_ram(&d->ram, "sun4u.ram", d->size);
|
688 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&d->ram); |
689 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &d->ram); |
690 | 81a322d4 | Gerd Hoffmann | return 0; |
691 | bda42033 | Blue Swirl | } |
692 | bda42033 | Blue Swirl | |
693 | c227f099 | Anthony Liguori | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) |
694 | bda42033 | Blue Swirl | { |
695 | bda42033 | Blue Swirl | DeviceState *dev; |
696 | bda42033 | Blue Swirl | SysBusDevice *s; |
697 | bda42033 | Blue Swirl | RamDevice *d; |
698 | bda42033 | Blue Swirl | |
699 | bda42033 | Blue Swirl | /* allocate RAM */
|
700 | bda42033 | Blue Swirl | dev = qdev_create(NULL, "memory"); |
701 | bda42033 | Blue Swirl | s = sysbus_from_qdev(dev); |
702 | bda42033 | Blue Swirl | |
703 | bda42033 | Blue Swirl | d = FROM_SYSBUS(RamDevice, s); |
704 | bda42033 | Blue Swirl | d->size = RAM_size; |
705 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
706 | bda42033 | Blue Swirl | |
707 | bda42033 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
708 | bda42033 | Blue Swirl | } |
709 | bda42033 | Blue Swirl | |
710 | 999e12bb | Anthony Liguori | static Property ram_properties[] = {
|
711 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
712 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
713 | 999e12bb | Anthony Liguori | }; |
714 | 999e12bb | Anthony Liguori | |
715 | 999e12bb | Anthony Liguori | static void ram_class_init(ObjectClass *klass, void *data) |
716 | 999e12bb | Anthony Liguori | { |
717 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
718 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
719 | 999e12bb | Anthony Liguori | |
720 | 999e12bb | Anthony Liguori | k->init = ram_init1; |
721 | 39bffca2 | Anthony Liguori | dc->props = ram_properties; |
722 | 999e12bb | Anthony Liguori | } |
723 | 999e12bb | Anthony Liguori | |
724 | 39bffca2 | Anthony Liguori | static TypeInfo ram_info = {
|
725 | 39bffca2 | Anthony Liguori | .name = "memory",
|
726 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
727 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(RamDevice),
|
728 | 39bffca2 | Anthony Liguori | .class_init = ram_class_init, |
729 | bda42033 | Blue Swirl | }; |
730 | bda42033 | Blue Swirl | |
731 | bda42033 | Blue Swirl | static void ram_register_devices(void) |
732 | bda42033 | Blue Swirl | { |
733 | 39bffca2 | Anthony Liguori | type_register_static(&ram_info); |
734 | bda42033 | Blue Swirl | } |
735 | bda42033 | Blue Swirl | |
736 | bda42033 | Blue Swirl | device_init(ram_register_devices); |
737 | bda42033 | Blue Swirl | |
738 | 7b833f5b | Blue Swirl | static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
739 | 3475187d | bellard | { |
740 | c68ea704 | bellard | CPUState *env; |
741 | e87231d4 | blueswir1 | ResetData *reset_info; |
742 | 3475187d | bellard | |
743 | 8f4efc55 | Igor V. Kovalenko | uint32_t tick_frequency = 100*1000000; |
744 | 8f4efc55 | Igor V. Kovalenko | uint32_t stick_frequency = 100*1000000; |
745 | 8f4efc55 | Igor V. Kovalenko | uint32_t hstick_frequency = 100*1000000; |
746 | 8f4efc55 | Igor V. Kovalenko | |
747 | c7ba218d | blueswir1 | if (!cpu_model)
|
748 | c7ba218d | blueswir1 | cpu_model = hwdef->default_cpu_model; |
749 | aaed909a | bellard | env = cpu_init(cpu_model); |
750 | aaed909a | bellard | if (!env) {
|
751 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
752 | 62724a37 | blueswir1 | exit(1);
|
753 | 62724a37 | blueswir1 | } |
754 | 20c9f095 | blueswir1 | |
755 | 8f4efc55 | Igor V. Kovalenko | env->tick = cpu_timer_create("tick", env, tick_irq,
|
756 | 8f4efc55 | Igor V. Kovalenko | tick_frequency, TICK_NPT_MASK); |
757 | 8f4efc55 | Igor V. Kovalenko | |
758 | 8f4efc55 | Igor V. Kovalenko | env->stick = cpu_timer_create("stick", env, stick_irq,
|
759 | 8f4efc55 | Igor V. Kovalenko | stick_frequency, TICK_INT_DIS); |
760 | 20c9f095 | blueswir1 | |
761 | 8f4efc55 | Igor V. Kovalenko | env->hstick = cpu_timer_create("hstick", env, hstick_irq,
|
762 | 8f4efc55 | Igor V. Kovalenko | hstick_frequency, TICK_INT_DIS); |
763 | e87231d4 | blueswir1 | |
764 | 7267c094 | Anthony Liguori | reset_info = g_malloc0(sizeof(ResetData));
|
765 | e87231d4 | blueswir1 | reset_info->env = env; |
766 | 44a99354 | Blue Swirl | reset_info->prom_addr = hwdef->prom_addr; |
767 | a08d4367 | Jan Kiszka | qemu_register_reset(main_cpu_reset, reset_info); |
768 | c68ea704 | bellard | |
769 | 7b833f5b | Blue Swirl | return env;
|
770 | 7b833f5b | Blue Swirl | } |
771 | 7b833f5b | Blue Swirl | |
772 | 38bc50f7 | Richard Henderson | static void sun4uv_init(MemoryRegion *address_space_mem, |
773 | 38bc50f7 | Richard Henderson | ram_addr_t RAM_size, |
774 | 7b833f5b | Blue Swirl | const char *boot_devices, |
775 | 7b833f5b | Blue Swirl | const char *kernel_filename, const char *kernel_cmdline, |
776 | 7b833f5b | Blue Swirl | const char *initrd_filename, const char *cpu_model, |
777 | 7b833f5b | Blue Swirl | const struct hwdef *hwdef) |
778 | 7b833f5b | Blue Swirl | { |
779 | 7b833f5b | Blue Swirl | CPUState *env; |
780 | 43a34704 | Blue Swirl | M48t59State *nvram; |
781 | 7b833f5b | Blue Swirl | unsigned int i; |
782 | 7b833f5b | Blue Swirl | long initrd_size, kernel_size;
|
783 | 7b833f5b | Blue Swirl | PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
784 | 48a18b3c | Hervé Poussineau | ISABus *isa_bus; |
785 | 7b833f5b | Blue Swirl | qemu_irq *irq; |
786 | f455e98c | Gerd Hoffmann | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
787 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
788 | 7b833f5b | Blue Swirl | void *fw_cfg;
|
789 | 7b833f5b | Blue Swirl | |
790 | 7b833f5b | Blue Swirl | /* init CPUs */
|
791 | 7b833f5b | Blue Swirl | env = cpu_devinit(cpu_model, hwdef); |
792 | 7b833f5b | Blue Swirl | |
793 | bda42033 | Blue Swirl | /* set up devices */
|
794 | bda42033 | Blue Swirl | ram_init(0, RAM_size);
|
795 | 3475187d | bellard | |
796 | 1baffa46 | Blue Swirl | prom_init(hwdef->prom_addr, bios_name); |
797 | 3475187d | bellard | |
798 | 7d55273f | Igor Kovalenko | |
799 | 7d55273f | Igor Kovalenko | irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
800 | 7d55273f | Igor Kovalenko | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2, |
801 | c190ea07 | blueswir1 | &pci_bus3); |
802 | 78895427 | Gerd Hoffmann | pci_vga_init(pci_bus); |
803 | 83469015 | bellard | |
804 | c190ea07 | blueswir1 | // XXX Should be pci_bus3
|
805 | 48a18b3c | Hervé Poussineau | isa_bus = pci_ebus_init(pci_bus, -1);
|
806 | c190ea07 | blueswir1 | |
807 | e87231d4 | blueswir1 | i = 0;
|
808 | e87231d4 | blueswir1 | if (hwdef->console_serial_base) {
|
809 | 38bc50f7 | Richard Henderson | serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
|
810 | 39186d8a | Richard Henderson | NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); |
811 | e87231d4 | blueswir1 | i++; |
812 | e87231d4 | blueswir1 | } |
813 | e87231d4 | blueswir1 | for(; i < MAX_SERIAL_PORTS; i++) {
|
814 | 83469015 | bellard | if (serial_hds[i]) {
|
815 | 48a18b3c | Hervé Poussineau | serial_isa_init(isa_bus, i, serial_hds[i]); |
816 | 83469015 | bellard | } |
817 | 83469015 | bellard | } |
818 | 83469015 | bellard | |
819 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
820 | 83469015 | bellard | if (parallel_hds[i]) {
|
821 | 48a18b3c | Hervé Poussineau | parallel_init(isa_bus, i, parallel_hds[i]); |
822 | 83469015 | bellard | } |
823 | 83469015 | bellard | } |
824 | 83469015 | bellard | |
825 | cb457d76 | aliguori | for(i = 0; i < nb_nics; i++) |
826 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
827 | 83469015 | bellard | |
828 | 75717903 | Isaku Yamahata | ide_drive_get(hd, MAX_IDE_BUS); |
829 | e4bcb14c | ths | |
830 | 3b898dda | blueswir1 | pci_cmd646_ide_init(pci_bus, hd, 1);
|
831 | 3b898dda | blueswir1 | |
832 | 48a18b3c | Hervé Poussineau | isa_create_simple(isa_bus, "i8042");
|
833 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
834 | fd8014e1 | Gerd Hoffmann | fd[i] = drive_get(IF_FLOPPY, 0, i);
|
835 | e4bcb14c | ths | } |
836 | 48a18b3c | Hervé Poussineau | fdctrl_init_isa(isa_bus, fd); |
837 | 48a18b3c | Hervé Poussineau | nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59); |
838 | 636aa70a | Blue Swirl | |
839 | 636aa70a | Blue Swirl | initrd_size = 0;
|
840 | 636aa70a | Blue Swirl | kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, |
841 | 636aa70a | Blue Swirl | ram_size, &initrd_size); |
842 | 636aa70a | Blue Swirl | |
843 | 22548760 | blueswir1 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
844 | 0d31cb99 | blueswir1 | KERNEL_LOAD_ADDR, kernel_size, |
845 | 0d31cb99 | blueswir1 | kernel_cmdline, |
846 | 0d31cb99 | blueswir1 | INITRD_LOAD_ADDR, initrd_size, |
847 | 0d31cb99 | blueswir1 | /* XXX: need an option to load a NVRAM image */
|
848 | 0d31cb99 | blueswir1 | 0,
|
849 | 0d31cb99 | blueswir1 | graphic_width, graphic_height, graphic_depth, |
850 | 0d31cb99 | blueswir1 | (uint8_t *)&nd_table[0].macaddr);
|
851 | 83469015 | bellard | |
852 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
853 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
854 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
855 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
856 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
857 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
858 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
859 | 9c9b0512 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
860 | 9c9b0512 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
861 | 6bb4ca57 | Blue Swirl | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
862 | 6bb4ca57 | Blue Swirl | (uint8_t*)strdup(kernel_cmdline), |
863 | 6bb4ca57 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
864 | 513f789f | blueswir1 | } else {
|
865 | 9c9b0512 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
866 | 513f789f | blueswir1 | } |
867 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
868 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
869 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
|
870 | 7589690c | Blue Swirl | |
871 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); |
872 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); |
873 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); |
874 | 7589690c | Blue Swirl | |
875 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
876 | 3475187d | bellard | } |
877 | 3475187d | bellard | |
878 | 905fdcb5 | blueswir1 | enum {
|
879 | 905fdcb5 | blueswir1 | sun4u_id = 0,
|
880 | 905fdcb5 | blueswir1 | sun4v_id = 64,
|
881 | e87231d4 | blueswir1 | niagara_id, |
882 | 905fdcb5 | blueswir1 | }; |
883 | 905fdcb5 | blueswir1 | |
884 | c7ba218d | blueswir1 | static const struct hwdef hwdefs[] = { |
885 | c7ba218d | blueswir1 | /* Sun4u generic PC-like machine */
|
886 | c7ba218d | blueswir1 | { |
887 | 5910b047 | Igor V. Kovalenko | .default_cpu_model = "TI UltraSparc IIi",
|
888 | 905fdcb5 | blueswir1 | .machine_id = sun4u_id, |
889 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
890 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
891 | c7ba218d | blueswir1 | }, |
892 | c7ba218d | blueswir1 | /* Sun4v generic PC-like machine */
|
893 | c7ba218d | blueswir1 | { |
894 | c7ba218d | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
895 | 905fdcb5 | blueswir1 | .machine_id = sun4v_id, |
896 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
897 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
898 | e87231d4 | blueswir1 | }, |
899 | e87231d4 | blueswir1 | /* Sun4v generic Niagara machine */
|
900 | e87231d4 | blueswir1 | { |
901 | e87231d4 | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
902 | e87231d4 | blueswir1 | .machine_id = niagara_id, |
903 | e87231d4 | blueswir1 | .prom_addr = 0xfff0000000ULL,
|
904 | e87231d4 | blueswir1 | .console_serial_base = 0xfff0c2c000ULL,
|
905 | c7ba218d | blueswir1 | }, |
906 | c7ba218d | blueswir1 | }; |
907 | c7ba218d | blueswir1 | |
908 | c7ba218d | blueswir1 | /* Sun4u hardware initialisation */
|
909 | c227f099 | Anthony Liguori | static void sun4u_init(ram_addr_t RAM_size, |
910 | 3023f332 | aliguori | const char *boot_devices, |
911 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
912 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
913 | c7ba218d | blueswir1 | { |
914 | 38bc50f7 | Richard Henderson | sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
915 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
916 | c7ba218d | blueswir1 | } |
917 | c7ba218d | blueswir1 | |
918 | c7ba218d | blueswir1 | /* Sun4v hardware initialisation */
|
919 | c227f099 | Anthony Liguori | static void sun4v_init(ram_addr_t RAM_size, |
920 | 3023f332 | aliguori | const char *boot_devices, |
921 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
922 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
923 | c7ba218d | blueswir1 | { |
924 | 38bc50f7 | Richard Henderson | sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
925 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
926 | c7ba218d | blueswir1 | } |
927 | c7ba218d | blueswir1 | |
928 | e87231d4 | blueswir1 | /* Niagara hardware initialisation */
|
929 | c227f099 | Anthony Liguori | static void niagara_init(ram_addr_t RAM_size, |
930 | 3023f332 | aliguori | const char *boot_devices, |
931 | e87231d4 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
932 | e87231d4 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
933 | e87231d4 | blueswir1 | { |
934 | 38bc50f7 | Richard Henderson | sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
935 | e87231d4 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
936 | e87231d4 | blueswir1 | } |
937 | e87231d4 | blueswir1 | |
938 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4u_machine = {
|
939 | 66de733b | blueswir1 | .name = "sun4u",
|
940 | 66de733b | blueswir1 | .desc = "Sun4u platform",
|
941 | 66de733b | blueswir1 | .init = sun4u_init, |
942 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
943 | 0c257437 | Anthony Liguori | .is_default = 1,
|
944 | 3475187d | bellard | }; |
945 | c7ba218d | blueswir1 | |
946 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4v_machine = {
|
947 | 66de733b | blueswir1 | .name = "sun4v",
|
948 | 66de733b | blueswir1 | .desc = "Sun4v platform",
|
949 | 66de733b | blueswir1 | .init = sun4v_init, |
950 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
951 | c7ba218d | blueswir1 | }; |
952 | e87231d4 | blueswir1 | |
953 | f80f9ec9 | Anthony Liguori | static QEMUMachine niagara_machine = {
|
954 | e87231d4 | blueswir1 | .name = "Niagara",
|
955 | e87231d4 | blueswir1 | .desc = "Sun4v platform, Niagara",
|
956 | e87231d4 | blueswir1 | .init = niagara_init, |
957 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
958 | e87231d4 | blueswir1 | }; |
959 | f80f9ec9 | Anthony Liguori | |
960 | f80f9ec9 | Anthony Liguori | static void sun4u_machine_init(void) |
961 | f80f9ec9 | Anthony Liguori | { |
962 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4u_machine); |
963 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4v_machine); |
964 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&niagara_machine); |
965 | f80f9ec9 | Anthony Liguori | } |
966 | f80f9ec9 | Anthony Liguori | |
967 | f80f9ec9 | Anthony Liguori | machine_init(sun4u_machine_init); |