tcg/arm: remove SAVE_LR code
There is no need to save the LR register (r14) before a call to asubroutine. According to the "Procedure Call Standard for the ARMArchitecture", it is the job of the callee to save this register.Moreover, this register is already saved in the prologue/epilogue....
tcg/arm: Replace qemu_ld32u (left over from previous commit)
Commit 86feb1c860dc38e9c89e787c5210e8191800385edid not change all occurrences of INDEX_op_qemu_ld32ufor tcg/arm.
Please note that I could not test this patch(I have currently no arm system available)....
tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operandssign-extended in 64-bit registers (regardless of the "real" signof the operand). For that, we need to be able to distinguishbetween a 32-bit load with a 32-bit result and a 32-bit load with...
tcg: Allow target-specific implementation of NOR.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Allow target-specific implementation of NAND.
tcg: Allow target-specific implementation of EQV.
tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.Use that enumeration type instead of "int" whereever appropriate.
remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: don't save/restore r7 in prologue/epilogue
There is no need to save r7, it is used to store the addressof the env structure and is not modified by GCC.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: fix load/store definitions for 32-bit targets
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