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1 | 574bbf7b | bellard | /*
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2 | 574bbf7b | bellard | * APIC support
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3 | 5fafdf24 | ths | *
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4 | 574bbf7b | bellard | * Copyright (c) 2004-2005 Fabrice Bellard
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5 | 574bbf7b | bellard | *
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6 | 574bbf7b | bellard | * This library is free software; you can redistribute it and/or
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7 | 574bbf7b | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 574bbf7b | bellard | * License as published by the Free Software Foundation; either
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9 | 574bbf7b | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 574bbf7b | bellard | *
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11 | 574bbf7b | bellard | * This library is distributed in the hope that it will be useful,
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12 | 574bbf7b | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 574bbf7b | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 574bbf7b | bellard | * Lesser General Public License for more details.
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15 | 574bbf7b | bellard | *
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16 | 574bbf7b | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>
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18 | 574bbf7b | bellard | */
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19 | 87ecb68b | pbrook | #include "hw.h" |
20 | aa28b9bf | Blue Swirl | #include "apic.h" |
21 | 0280b571 | Jan Kiszka | #include "ioapic.h" |
22 | 87ecb68b | pbrook | #include "qemu-timer.h" |
23 | bb7e7293 | aurel32 | #include "host-utils.h" |
24 | 8546b099 | Blue Swirl | #include "sysbus.h" |
25 | d8023f31 | Blue Swirl | #include "trace.h" |
26 | 574bbf7b | bellard | |
27 | 574bbf7b | bellard | /* APIC Local Vector Table */
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28 | 574bbf7b | bellard | #define APIC_LVT_TIMER 0 |
29 | 574bbf7b | bellard | #define APIC_LVT_THERMAL 1 |
30 | 574bbf7b | bellard | #define APIC_LVT_PERFORM 2 |
31 | 574bbf7b | bellard | #define APIC_LVT_LINT0 3 |
32 | 574bbf7b | bellard | #define APIC_LVT_LINT1 4 |
33 | 574bbf7b | bellard | #define APIC_LVT_ERROR 5 |
34 | 574bbf7b | bellard | #define APIC_LVT_NB 6 |
35 | 574bbf7b | bellard | |
36 | 574bbf7b | bellard | /* APIC delivery modes */
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37 | 574bbf7b | bellard | #define APIC_DM_FIXED 0 |
38 | 574bbf7b | bellard | #define APIC_DM_LOWPRI 1 |
39 | 574bbf7b | bellard | #define APIC_DM_SMI 2 |
40 | 574bbf7b | bellard | #define APIC_DM_NMI 4 |
41 | 574bbf7b | bellard | #define APIC_DM_INIT 5 |
42 | 574bbf7b | bellard | #define APIC_DM_SIPI 6 |
43 | 574bbf7b | bellard | #define APIC_DM_EXTINT 7 |
44 | 574bbf7b | bellard | |
45 | d592d303 | bellard | /* APIC destination mode */
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46 | d592d303 | bellard | #define APIC_DESTMODE_FLAT 0xf |
47 | d592d303 | bellard | #define APIC_DESTMODE_CLUSTER 1 |
48 | d592d303 | bellard | |
49 | 574bbf7b | bellard | #define APIC_TRIGGER_EDGE 0 |
50 | 574bbf7b | bellard | #define APIC_TRIGGER_LEVEL 1 |
51 | 574bbf7b | bellard | |
52 | 574bbf7b | bellard | #define APIC_LVT_TIMER_PERIODIC (1<<17) |
53 | 574bbf7b | bellard | #define APIC_LVT_MASKED (1<<16) |
54 | 574bbf7b | bellard | #define APIC_LVT_LEVEL_TRIGGER (1<<15) |
55 | 574bbf7b | bellard | #define APIC_LVT_REMOTE_IRR (1<<14) |
56 | 574bbf7b | bellard | #define APIC_INPUT_POLARITY (1<<13) |
57 | 574bbf7b | bellard | #define APIC_SEND_PENDING (1<<12) |
58 | 574bbf7b | bellard | |
59 | 574bbf7b | bellard | #define ESR_ILLEGAL_ADDRESS (1 << 7) |
60 | 574bbf7b | bellard | |
61 | 0280b571 | Jan Kiszka | #define APIC_SV_DIRECTED_IO (1<<12) |
62 | 0280b571 | Jan Kiszka | #define APIC_SV_ENABLE (1<<8) |
63 | 574bbf7b | bellard | |
64 | d3e9db93 | bellard | #define MAX_APICS 255 |
65 | d3e9db93 | bellard | #define MAX_APIC_WORDS 8 |
66 | d3e9db93 | bellard | |
67 | 54c96da7 | Michael S. Tsirkin | /* Intel APIC constants: from include/asm/msidef.h */
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68 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_VECTOR_SHIFT 0 |
69 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_VECTOR_MASK 0x000000ff |
70 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_DELIVERY_MODE_SHIFT 8 |
71 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_TRIGGER_SHIFT 15 |
72 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_LEVEL_SHIFT 14 |
73 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_DEST_MODE_SHIFT 2 |
74 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_DEST_ID_SHIFT 12 |
75 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 |
76 | 54c96da7 | Michael S. Tsirkin | |
77 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_SIZE 0x100000 |
78 | 54c96da7 | Michael S. Tsirkin | |
79 | 92a16d7a | Blue Swirl | typedef struct APICState APICState; |
80 | 92a16d7a | Blue Swirl | |
81 | cf6d64bf | Blue Swirl | struct APICState {
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82 | 8546b099 | Blue Swirl | SysBusDevice busdev; |
83 | 8546b099 | Blue Swirl | void *cpu_env;
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84 | 574bbf7b | bellard | uint32_t apicbase; |
85 | 574bbf7b | bellard | uint8_t id; |
86 | d592d303 | bellard | uint8_t arb_id; |
87 | 574bbf7b | bellard | uint8_t tpr; |
88 | 574bbf7b | bellard | uint32_t spurious_vec; |
89 | d592d303 | bellard | uint8_t log_dest; |
90 | d592d303 | bellard | uint8_t dest_mode; |
91 | 574bbf7b | bellard | uint32_t isr[8]; /* in service register */ |
92 | 574bbf7b | bellard | uint32_t tmr[8]; /* trigger mode register */ |
93 | 574bbf7b | bellard | uint32_t irr[8]; /* interrupt request register */ |
94 | 574bbf7b | bellard | uint32_t lvt[APIC_LVT_NB]; |
95 | 574bbf7b | bellard | uint32_t esr; /* error register */
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96 | 574bbf7b | bellard | uint32_t icr[2];
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97 | 574bbf7b | bellard | |
98 | 574bbf7b | bellard | uint32_t divide_conf; |
99 | 574bbf7b | bellard | int count_shift;
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100 | 574bbf7b | bellard | uint32_t initial_count; |
101 | 574bbf7b | bellard | int64_t initial_count_load_time, next_time; |
102 | 678e12cc | Gleb Natapov | uint32_t idx; |
103 | 574bbf7b | bellard | QEMUTimer *timer; |
104 | b09ea7d5 | Gleb Natapov | int sipi_vector;
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105 | b09ea7d5 | Gleb Natapov | int wait_for_sipi;
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106 | cf6d64bf | Blue Swirl | }; |
107 | 574bbf7b | bellard | |
108 | d3e9db93 | bellard | static APICState *local_apics[MAX_APICS + 1]; |
109 | 73822ec8 | aliguori | static int apic_irq_delivered; |
110 | 73822ec8 | aliguori | |
111 | d592d303 | bellard | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
112 | d592d303 | bellard | static void apic_update_irq(APICState *s); |
113 | 610626af | aliguori | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
114 | 610626af | aliguori | uint8_t dest, uint8_t dest_mode); |
115 | d592d303 | bellard | |
116 | 3b63c04e | aurel32 | /* Find first bit starting from msb */
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117 | 3b63c04e | aurel32 | static int fls_bit(uint32_t value) |
118 | 3b63c04e | aurel32 | { |
119 | 3b63c04e | aurel32 | return 31 - clz32(value); |
120 | 3b63c04e | aurel32 | } |
121 | 3b63c04e | aurel32 | |
122 | e95f5491 | aurel32 | /* Find first bit starting from lsb */
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123 | d3e9db93 | bellard | static int ffs_bit(uint32_t value) |
124 | d3e9db93 | bellard | { |
125 | bb7e7293 | aurel32 | return ctz32(value);
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126 | d3e9db93 | bellard | } |
127 | d3e9db93 | bellard | |
128 | d3e9db93 | bellard | static inline void set_bit(uint32_t *tab, int index) |
129 | d3e9db93 | bellard | { |
130 | d3e9db93 | bellard | int i, mask;
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131 | d3e9db93 | bellard | i = index >> 5;
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132 | d3e9db93 | bellard | mask = 1 << (index & 0x1f); |
133 | d3e9db93 | bellard | tab[i] |= mask; |
134 | d3e9db93 | bellard | } |
135 | d3e9db93 | bellard | |
136 | d3e9db93 | bellard | static inline void reset_bit(uint32_t *tab, int index) |
137 | d3e9db93 | bellard | { |
138 | d3e9db93 | bellard | int i, mask;
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139 | d3e9db93 | bellard | i = index >> 5;
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140 | d3e9db93 | bellard | mask = 1 << (index & 0x1f); |
141 | d3e9db93 | bellard | tab[i] &= ~mask; |
142 | d3e9db93 | bellard | } |
143 | d3e9db93 | bellard | |
144 | 73822ec8 | aliguori | static inline int get_bit(uint32_t *tab, int index) |
145 | 73822ec8 | aliguori | { |
146 | 73822ec8 | aliguori | int i, mask;
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147 | 73822ec8 | aliguori | i = index >> 5;
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148 | 73822ec8 | aliguori | mask = 1 << (index & 0x1f); |
149 | 73822ec8 | aliguori | return !!(tab[i] & mask);
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150 | 73822ec8 | aliguori | } |
151 | 73822ec8 | aliguori | |
152 | cf6d64bf | Blue Swirl | static void apic_local_deliver(APICState *s, int vector) |
153 | a5b38b51 | aurel32 | { |
154 | a5b38b51 | aurel32 | uint32_t lvt = s->lvt[vector]; |
155 | a5b38b51 | aurel32 | int trigger_mode;
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156 | a5b38b51 | aurel32 | |
157 | d8023f31 | Blue Swirl | trace_apic_local_deliver(vector, (lvt >> 8) & 7); |
158 | d8023f31 | Blue Swirl | |
159 | a5b38b51 | aurel32 | if (lvt & APIC_LVT_MASKED)
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160 | a5b38b51 | aurel32 | return;
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161 | a5b38b51 | aurel32 | |
162 | a5b38b51 | aurel32 | switch ((lvt >> 8) & 7) { |
163 | a5b38b51 | aurel32 | case APIC_DM_SMI:
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164 | cf6d64bf | Blue Swirl | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); |
165 | a5b38b51 | aurel32 | break;
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166 | a5b38b51 | aurel32 | |
167 | a5b38b51 | aurel32 | case APIC_DM_NMI:
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168 | cf6d64bf | Blue Swirl | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); |
169 | a5b38b51 | aurel32 | break;
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170 | a5b38b51 | aurel32 | |
171 | a5b38b51 | aurel32 | case APIC_DM_EXTINT:
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172 | cf6d64bf | Blue Swirl | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
173 | a5b38b51 | aurel32 | break;
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174 | a5b38b51 | aurel32 | |
175 | a5b38b51 | aurel32 | case APIC_DM_FIXED:
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176 | a5b38b51 | aurel32 | trigger_mode = APIC_TRIGGER_EDGE; |
177 | a5b38b51 | aurel32 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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178 | a5b38b51 | aurel32 | (lvt & APIC_LVT_LEVEL_TRIGGER)) |
179 | a5b38b51 | aurel32 | trigger_mode = APIC_TRIGGER_LEVEL; |
180 | a5b38b51 | aurel32 | apic_set_irq(s, lvt & 0xff, trigger_mode);
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181 | a5b38b51 | aurel32 | } |
182 | a5b38b51 | aurel32 | } |
183 | a5b38b51 | aurel32 | |
184 | 92a16d7a | Blue Swirl | void apic_deliver_pic_intr(DeviceState *d, int level) |
185 | 1a7de94a | aurel32 | { |
186 | 92a16d7a | Blue Swirl | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
187 | 92a16d7a | Blue Swirl | |
188 | cf6d64bf | Blue Swirl | if (level) {
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189 | cf6d64bf | Blue Swirl | apic_local_deliver(s, APIC_LVT_LINT0); |
190 | cf6d64bf | Blue Swirl | } else {
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191 | 1a7de94a | aurel32 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
192 | 1a7de94a | aurel32 | |
193 | 1a7de94a | aurel32 | switch ((lvt >> 8) & 7) { |
194 | 1a7de94a | aurel32 | case APIC_DM_FIXED:
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195 | 1a7de94a | aurel32 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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196 | 1a7de94a | aurel32 | break;
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197 | 1a7de94a | aurel32 | reset_bit(s->irr, lvt & 0xff);
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198 | 1a7de94a | aurel32 | /* fall through */
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199 | 1a7de94a | aurel32 | case APIC_DM_EXTINT:
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200 | cf6d64bf | Blue Swirl | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
201 | 1a7de94a | aurel32 | break;
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202 | 1a7de94a | aurel32 | } |
203 | 1a7de94a | aurel32 | } |
204 | 1a7de94a | aurel32 | } |
205 | 1a7de94a | aurel32 | |
206 | d3e9db93 | bellard | #define foreach_apic(apic, deliver_bitmask, code) \
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207 | d3e9db93 | bellard | {\ |
208 | d3e9db93 | bellard | int __i, __j, __mask;\
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209 | d3e9db93 | bellard | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
210 | d3e9db93 | bellard | __mask = deliver_bitmask[__i];\ |
211 | d3e9db93 | bellard | if (__mask) {\
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212 | d3e9db93 | bellard | for(__j = 0; __j < 32; __j++) {\ |
213 | d3e9db93 | bellard | if (__mask & (1 << __j)) {\ |
214 | d3e9db93 | bellard | apic = local_apics[__i * 32 + __j];\
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215 | d3e9db93 | bellard | if (apic) {\
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216 | d3e9db93 | bellard | code;\ |
217 | d3e9db93 | bellard | }\ |
218 | d3e9db93 | bellard | }\ |
219 | d3e9db93 | bellard | }\ |
220 | d3e9db93 | bellard | }\ |
221 | d3e9db93 | bellard | }\ |
222 | d3e9db93 | bellard | } |
223 | d3e9db93 | bellard | |
224 | 5fafdf24 | ths | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
225 | d3e9db93 | bellard | uint8_t delivery_mode, |
226 | d592d303 | bellard | uint8_t vector_num, uint8_t polarity, |
227 | d592d303 | bellard | uint8_t trigger_mode) |
228 | d592d303 | bellard | { |
229 | d592d303 | bellard | APICState *apic_iter; |
230 | d592d303 | bellard | |
231 | d592d303 | bellard | switch (delivery_mode) {
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232 | d592d303 | bellard | case APIC_DM_LOWPRI:
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233 | 8dd69b8f | bellard | /* XXX: search for focus processor, arbitration */
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234 | d3e9db93 | bellard | { |
235 | d3e9db93 | bellard | int i, d;
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236 | d3e9db93 | bellard | d = -1;
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237 | d3e9db93 | bellard | for(i = 0; i < MAX_APIC_WORDS; i++) { |
238 | d3e9db93 | bellard | if (deliver_bitmask[i]) {
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239 | d3e9db93 | bellard | d = i * 32 + ffs_bit(deliver_bitmask[i]);
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240 | d3e9db93 | bellard | break;
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241 | d3e9db93 | bellard | } |
242 | d3e9db93 | bellard | } |
243 | d3e9db93 | bellard | if (d >= 0) { |
244 | d3e9db93 | bellard | apic_iter = local_apics[d]; |
245 | d3e9db93 | bellard | if (apic_iter) {
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246 | d3e9db93 | bellard | apic_set_irq(apic_iter, vector_num, trigger_mode); |
247 | d3e9db93 | bellard | } |
248 | d3e9db93 | bellard | } |
249 | 8dd69b8f | bellard | } |
250 | d3e9db93 | bellard | return;
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251 | 8dd69b8f | bellard | |
252 | d592d303 | bellard | case APIC_DM_FIXED:
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253 | d592d303 | bellard | break;
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254 | d592d303 | bellard | |
255 | d592d303 | bellard | case APIC_DM_SMI:
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256 | e2eb9d3e | aurel32 | foreach_apic(apic_iter, deliver_bitmask, |
257 | e2eb9d3e | aurel32 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); |
258 | e2eb9d3e | aurel32 | return;
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259 | e2eb9d3e | aurel32 | |
260 | d592d303 | bellard | case APIC_DM_NMI:
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261 | e2eb9d3e | aurel32 | foreach_apic(apic_iter, deliver_bitmask, |
262 | e2eb9d3e | aurel32 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); |
263 | e2eb9d3e | aurel32 | return;
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264 | d592d303 | bellard | |
265 | d592d303 | bellard | case APIC_DM_INIT:
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266 | d592d303 | bellard | /* normal INIT IPI sent to processors */
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267 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
268 | b09ea7d5 | Gleb Natapov | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
269 | d592d303 | bellard | return;
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270 | 3b46e624 | ths | |
271 | d592d303 | bellard | case APIC_DM_EXTINT:
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272 | b1fc0348 | bellard | /* handled in I/O APIC code */
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273 | d592d303 | bellard | break;
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274 | d592d303 | bellard | |
275 | d592d303 | bellard | default:
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276 | d592d303 | bellard | return;
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277 | d592d303 | bellard | } |
278 | d592d303 | bellard | |
279 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
280 | d3e9db93 | bellard | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
281 | d592d303 | bellard | } |
282 | 574bbf7b | bellard | |
283 | 610626af | aliguori | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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284 | 610626af | aliguori | uint8_t delivery_mode, uint8_t vector_num, |
285 | 610626af | aliguori | uint8_t polarity, uint8_t trigger_mode) |
286 | 610626af | aliguori | { |
287 | 610626af | aliguori | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
288 | 610626af | aliguori | |
289 | d8023f31 | Blue Swirl | trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, |
290 | d8023f31 | Blue Swirl | polarity, trigger_mode); |
291 | d8023f31 | Blue Swirl | |
292 | 610626af | aliguori | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
293 | 610626af | aliguori | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
294 | 610626af | aliguori | trigger_mode); |
295 | 610626af | aliguori | } |
296 | 610626af | aliguori | |
297 | 92a16d7a | Blue Swirl | void cpu_set_apic_base(DeviceState *d, uint64_t val)
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298 | 574bbf7b | bellard | { |
299 | 92a16d7a | Blue Swirl | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
300 | 92a16d7a | Blue Swirl | |
301 | d8023f31 | Blue Swirl | trace_cpu_set_apic_base(val); |
302 | d8023f31 | Blue Swirl | |
303 | 2c7c13d4 | aurel32 | if (!s)
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304 | 2c7c13d4 | aurel32 | return;
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305 | 5fafdf24 | ths | s->apicbase = (val & 0xfffff000) |
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306 | 574bbf7b | bellard | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
307 | 574bbf7b | bellard | /* if disabled, cannot be enabled again */
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308 | 574bbf7b | bellard | if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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309 | 574bbf7b | bellard | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
310 | 0e26b7b8 | Blue Swirl | cpu_clear_apic_feature(s->cpu_env); |
311 | 574bbf7b | bellard | s->spurious_vec &= ~APIC_SV_ENABLE; |
312 | 574bbf7b | bellard | } |
313 | 574bbf7b | bellard | } |
314 | 574bbf7b | bellard | |
315 | 92a16d7a | Blue Swirl | uint64_t cpu_get_apic_base(DeviceState *d) |
316 | 574bbf7b | bellard | { |
317 | 92a16d7a | Blue Swirl | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
318 | 92a16d7a | Blue Swirl | |
319 | d8023f31 | Blue Swirl | trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
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320 | d8023f31 | Blue Swirl | |
321 | 2c7c13d4 | aurel32 | return s ? s->apicbase : 0; |
322 | 574bbf7b | bellard | } |
323 | 574bbf7b | bellard | |
324 | 92a16d7a | Blue Swirl | void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
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325 | 9230e66e | bellard | { |
326 | 92a16d7a | Blue Swirl | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
327 | 92a16d7a | Blue Swirl | |
328 | 2c7c13d4 | aurel32 | if (!s)
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329 | 2c7c13d4 | aurel32 | return;
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330 | 9230e66e | bellard | s->tpr = (val & 0x0f) << 4; |
331 | d592d303 | bellard | apic_update_irq(s); |
332 | 9230e66e | bellard | } |
333 | 9230e66e | bellard | |
334 | 92a16d7a | Blue Swirl | uint8_t cpu_get_apic_tpr(DeviceState *d) |
335 | 9230e66e | bellard | { |
336 | 92a16d7a | Blue Swirl | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
337 | 92a16d7a | Blue Swirl | |
338 | 2c7c13d4 | aurel32 | return s ? s->tpr >> 4 : 0; |
339 | 9230e66e | bellard | } |
340 | 9230e66e | bellard | |
341 | d592d303 | bellard | /* return -1 if no bit is set */
|
342 | d592d303 | bellard | static int get_highest_priority_int(uint32_t *tab) |
343 | d592d303 | bellard | { |
344 | d592d303 | bellard | int i;
|
345 | d592d303 | bellard | for(i = 7; i >= 0; i--) { |
346 | d592d303 | bellard | if (tab[i] != 0) { |
347 | 3b63c04e | aurel32 | return i * 32 + fls_bit(tab[i]); |
348 | d592d303 | bellard | } |
349 | d592d303 | bellard | } |
350 | d592d303 | bellard | return -1; |
351 | d592d303 | bellard | } |
352 | d592d303 | bellard | |
353 | 574bbf7b | bellard | static int apic_get_ppr(APICState *s) |
354 | 574bbf7b | bellard | { |
355 | 574bbf7b | bellard | int tpr, isrv, ppr;
|
356 | 574bbf7b | bellard | |
357 | 574bbf7b | bellard | tpr = (s->tpr >> 4);
|
358 | 574bbf7b | bellard | isrv = get_highest_priority_int(s->isr); |
359 | 574bbf7b | bellard | if (isrv < 0) |
360 | 574bbf7b | bellard | isrv = 0;
|
361 | 574bbf7b | bellard | isrv >>= 4;
|
362 | 574bbf7b | bellard | if (tpr >= isrv)
|
363 | 574bbf7b | bellard | ppr = s->tpr; |
364 | 574bbf7b | bellard | else
|
365 | 574bbf7b | bellard | ppr = isrv << 4;
|
366 | 574bbf7b | bellard | return ppr;
|
367 | 574bbf7b | bellard | } |
368 | 574bbf7b | bellard | |
369 | d592d303 | bellard | static int apic_get_arb_pri(APICState *s) |
370 | d592d303 | bellard | { |
371 | d592d303 | bellard | /* XXX: arbitration */
|
372 | d592d303 | bellard | return 0; |
373 | d592d303 | bellard | } |
374 | d592d303 | bellard | |
375 | 0fbfbb59 | Gleb Natapov | |
376 | 0fbfbb59 | Gleb Natapov | /*
|
377 | 0fbfbb59 | Gleb Natapov | * <0 - low prio interrupt,
|
378 | 0fbfbb59 | Gleb Natapov | * 0 - no interrupt,
|
379 | 0fbfbb59 | Gleb Natapov | * >0 - interrupt number
|
380 | 0fbfbb59 | Gleb Natapov | */
|
381 | 0fbfbb59 | Gleb Natapov | static int apic_irq_pending(APICState *s) |
382 | 574bbf7b | bellard | { |
383 | d592d303 | bellard | int irrv, ppr;
|
384 | 574bbf7b | bellard | irrv = get_highest_priority_int(s->irr); |
385 | 0fbfbb59 | Gleb Natapov | if (irrv < 0) { |
386 | 0fbfbb59 | Gleb Natapov | return 0; |
387 | 0fbfbb59 | Gleb Natapov | } |
388 | d592d303 | bellard | ppr = apic_get_ppr(s); |
389 | 0fbfbb59 | Gleb Natapov | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { |
390 | 0fbfbb59 | Gleb Natapov | return -1; |
391 | 0fbfbb59 | Gleb Natapov | } |
392 | 0fbfbb59 | Gleb Natapov | |
393 | 0fbfbb59 | Gleb Natapov | return irrv;
|
394 | 0fbfbb59 | Gleb Natapov | } |
395 | 0fbfbb59 | Gleb Natapov | |
396 | 0fbfbb59 | Gleb Natapov | /* signal the CPU if an irq is pending */
|
397 | 0fbfbb59 | Gleb Natapov | static void apic_update_irq(APICState *s) |
398 | 0fbfbb59 | Gleb Natapov | { |
399 | 0fbfbb59 | Gleb Natapov | if (!(s->spurious_vec & APIC_SV_ENABLE)) {
|
400 | 574bbf7b | bellard | return;
|
401 | 0fbfbb59 | Gleb Natapov | } |
402 | 0fbfbb59 | Gleb Natapov | if (apic_irq_pending(s) > 0) { |
403 | 0fbfbb59 | Gleb Natapov | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
404 | 0fbfbb59 | Gleb Natapov | } |
405 | 574bbf7b | bellard | } |
406 | 574bbf7b | bellard | |
407 | 73822ec8 | aliguori | void apic_reset_irq_delivered(void) |
408 | 73822ec8 | aliguori | { |
409 | d8023f31 | Blue Swirl | trace_apic_reset_irq_delivered(apic_irq_delivered); |
410 | d8023f31 | Blue Swirl | |
411 | 73822ec8 | aliguori | apic_irq_delivered = 0;
|
412 | 73822ec8 | aliguori | } |
413 | 73822ec8 | aliguori | |
414 | 73822ec8 | aliguori | int apic_get_irq_delivered(void) |
415 | 73822ec8 | aliguori | { |
416 | d8023f31 | Blue Swirl | trace_apic_get_irq_delivered(apic_irq_delivered); |
417 | d8023f31 | Blue Swirl | |
418 | 73822ec8 | aliguori | return apic_irq_delivered;
|
419 | 73822ec8 | aliguori | } |
420 | 73822ec8 | aliguori | |
421 | 574bbf7b | bellard | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
422 | 574bbf7b | bellard | { |
423 | 73822ec8 | aliguori | apic_irq_delivered += !get_bit(s->irr, vector_num); |
424 | d8023f31 | Blue Swirl | |
425 | d8023f31 | Blue Swirl | trace_apic_set_irq(apic_irq_delivered); |
426 | 73822ec8 | aliguori | |
427 | 574bbf7b | bellard | set_bit(s->irr, vector_num); |
428 | 574bbf7b | bellard | if (trigger_mode)
|
429 | 574bbf7b | bellard | set_bit(s->tmr, vector_num); |
430 | 574bbf7b | bellard | else
|
431 | 574bbf7b | bellard | reset_bit(s->tmr, vector_num); |
432 | 574bbf7b | bellard | apic_update_irq(s); |
433 | 574bbf7b | bellard | } |
434 | 574bbf7b | bellard | |
435 | 574bbf7b | bellard | static void apic_eoi(APICState *s) |
436 | 574bbf7b | bellard | { |
437 | 574bbf7b | bellard | int isrv;
|
438 | 574bbf7b | bellard | isrv = get_highest_priority_int(s->isr); |
439 | 574bbf7b | bellard | if (isrv < 0) |
440 | 574bbf7b | bellard | return;
|
441 | 574bbf7b | bellard | reset_bit(s->isr, isrv); |
442 | 0280b571 | Jan Kiszka | if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
|
443 | 0280b571 | Jan Kiszka | ioapic_eoi_broadcast(isrv); |
444 | 0280b571 | Jan Kiszka | } |
445 | 574bbf7b | bellard | apic_update_irq(s); |
446 | 574bbf7b | bellard | } |
447 | 574bbf7b | bellard | |
448 | 678e12cc | Gleb Natapov | static int apic_find_dest(uint8_t dest) |
449 | 678e12cc | Gleb Natapov | { |
450 | 678e12cc | Gleb Natapov | APICState *apic = local_apics[dest]; |
451 | 678e12cc | Gleb Natapov | int i;
|
452 | 678e12cc | Gleb Natapov | |
453 | 678e12cc | Gleb Natapov | if (apic && apic->id == dest)
|
454 | 678e12cc | Gleb Natapov | return dest; /* shortcut in case apic->id == apic->idx */ |
455 | 678e12cc | Gleb Natapov | |
456 | 678e12cc | Gleb Natapov | for (i = 0; i < MAX_APICS; i++) { |
457 | 678e12cc | Gleb Natapov | apic = local_apics[i]; |
458 | 678e12cc | Gleb Natapov | if (apic && apic->id == dest)
|
459 | 678e12cc | Gleb Natapov | return i;
|
460 | b538e53e | Alex Williamson | if (!apic)
|
461 | b538e53e | Alex Williamson | break;
|
462 | 678e12cc | Gleb Natapov | } |
463 | 678e12cc | Gleb Natapov | |
464 | 678e12cc | Gleb Natapov | return -1; |
465 | 678e12cc | Gleb Natapov | } |
466 | 678e12cc | Gleb Natapov | |
467 | d3e9db93 | bellard | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
468 | d3e9db93 | bellard | uint8_t dest, uint8_t dest_mode) |
469 | d592d303 | bellard | { |
470 | d592d303 | bellard | APICState *apic_iter; |
471 | d3e9db93 | bellard | int i;
|
472 | d592d303 | bellard | |
473 | d592d303 | bellard | if (dest_mode == 0) { |
474 | d3e9db93 | bellard | if (dest == 0xff) { |
475 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); |
476 | d3e9db93 | bellard | } else {
|
477 | 678e12cc | Gleb Natapov | int idx = apic_find_dest(dest);
|
478 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
479 | 678e12cc | Gleb Natapov | if (idx >= 0) |
480 | 678e12cc | Gleb Natapov | set_bit(deliver_bitmask, idx); |
481 | d3e9db93 | bellard | } |
482 | d592d303 | bellard | } else {
|
483 | d592d303 | bellard | /* XXX: cluster mode */
|
484 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
485 | d3e9db93 | bellard | for(i = 0; i < MAX_APICS; i++) { |
486 | d3e9db93 | bellard | apic_iter = local_apics[i]; |
487 | d3e9db93 | bellard | if (apic_iter) {
|
488 | d3e9db93 | bellard | if (apic_iter->dest_mode == 0xf) { |
489 | d3e9db93 | bellard | if (dest & apic_iter->log_dest)
|
490 | d3e9db93 | bellard | set_bit(deliver_bitmask, i); |
491 | d3e9db93 | bellard | } else if (apic_iter->dest_mode == 0x0) { |
492 | d3e9db93 | bellard | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && |
493 | d3e9db93 | bellard | (dest & apic_iter->log_dest & 0x0f)) {
|
494 | d3e9db93 | bellard | set_bit(deliver_bitmask, i); |
495 | d3e9db93 | bellard | } |
496 | d3e9db93 | bellard | } |
497 | b538e53e | Alex Williamson | } else {
|
498 | b538e53e | Alex Williamson | break;
|
499 | d3e9db93 | bellard | } |
500 | d592d303 | bellard | } |
501 | d592d303 | bellard | } |
502 | d592d303 | bellard | } |
503 | d592d303 | bellard | |
504 | 92a16d7a | Blue Swirl | void apic_init_reset(DeviceState *d)
|
505 | d592d303 | bellard | { |
506 | 92a16d7a | Blue Swirl | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
507 | d592d303 | bellard | int i;
|
508 | d592d303 | bellard | |
509 | b09ea7d5 | Gleb Natapov | if (!s)
|
510 | b09ea7d5 | Gleb Natapov | return;
|
511 | b09ea7d5 | Gleb Natapov | |
512 | d592d303 | bellard | s->tpr = 0;
|
513 | d592d303 | bellard | s->spurious_vec = 0xff;
|
514 | d592d303 | bellard | s->log_dest = 0;
|
515 | e0fd8781 | bellard | s->dest_mode = 0xf;
|
516 | d592d303 | bellard | memset(s->isr, 0, sizeof(s->isr)); |
517 | d592d303 | bellard | memset(s->tmr, 0, sizeof(s->tmr)); |
518 | d592d303 | bellard | memset(s->irr, 0, sizeof(s->irr)); |
519 | b4511723 | bellard | for(i = 0; i < APIC_LVT_NB; i++) |
520 | b4511723 | bellard | s->lvt[i] = 1 << 16; /* mask LVT */ |
521 | d592d303 | bellard | s->esr = 0;
|
522 | d592d303 | bellard | memset(s->icr, 0, sizeof(s->icr)); |
523 | d592d303 | bellard | s->divide_conf = 0;
|
524 | d592d303 | bellard | s->count_shift = 0;
|
525 | d592d303 | bellard | s->initial_count = 0;
|
526 | d592d303 | bellard | s->initial_count_load_time = 0;
|
527 | d592d303 | bellard | s->next_time = 0;
|
528 | b09ea7d5 | Gleb Natapov | s->wait_for_sipi = 1;
|
529 | d592d303 | bellard | } |
530 | d592d303 | bellard | |
531 | e0fd8781 | bellard | static void apic_startup(APICState *s, int vector_num) |
532 | e0fd8781 | bellard | { |
533 | b09ea7d5 | Gleb Natapov | s->sipi_vector = vector_num; |
534 | b09ea7d5 | Gleb Natapov | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
535 | b09ea7d5 | Gleb Natapov | } |
536 | b09ea7d5 | Gleb Natapov | |
537 | 92a16d7a | Blue Swirl | void apic_sipi(DeviceState *d)
|
538 | b09ea7d5 | Gleb Natapov | { |
539 | 92a16d7a | Blue Swirl | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
540 | 92a16d7a | Blue Swirl | |
541 | 4a942cea | Blue Swirl | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
542 | b09ea7d5 | Gleb Natapov | |
543 | b09ea7d5 | Gleb Natapov | if (!s->wait_for_sipi)
|
544 | e0fd8781 | bellard | return;
|
545 | 0e26b7b8 | Blue Swirl | cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector); |
546 | b09ea7d5 | Gleb Natapov | s->wait_for_sipi = 0;
|
547 | e0fd8781 | bellard | } |
548 | e0fd8781 | bellard | |
549 | 92a16d7a | Blue Swirl | static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, |
550 | d592d303 | bellard | uint8_t delivery_mode, uint8_t vector_num, |
551 | d592d303 | bellard | uint8_t polarity, uint8_t trigger_mode) |
552 | d592d303 | bellard | { |
553 | 92a16d7a | Blue Swirl | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
554 | d3e9db93 | bellard | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
555 | d592d303 | bellard | int dest_shorthand = (s->icr[0] >> 18) & 3; |
556 | d592d303 | bellard | APICState *apic_iter; |
557 | d592d303 | bellard | |
558 | e0fd8781 | bellard | switch (dest_shorthand) {
|
559 | d3e9db93 | bellard | case 0: |
560 | d3e9db93 | bellard | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
561 | d3e9db93 | bellard | break;
|
562 | d3e9db93 | bellard | case 1: |
563 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); |
564 | 678e12cc | Gleb Natapov | set_bit(deliver_bitmask, s->idx); |
565 | d3e9db93 | bellard | break;
|
566 | d3e9db93 | bellard | case 2: |
567 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
568 | d3e9db93 | bellard | break;
|
569 | d3e9db93 | bellard | case 3: |
570 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
571 | 678e12cc | Gleb Natapov | reset_bit(deliver_bitmask, s->idx); |
572 | d3e9db93 | bellard | break;
|
573 | e0fd8781 | bellard | } |
574 | e0fd8781 | bellard | |
575 | d592d303 | bellard | switch (delivery_mode) {
|
576 | d592d303 | bellard | case APIC_DM_INIT:
|
577 | d592d303 | bellard | { |
578 | d592d303 | bellard | int trig_mode = (s->icr[0] >> 15) & 1; |
579 | d592d303 | bellard | int level = (s->icr[0] >> 14) & 1; |
580 | d592d303 | bellard | if (level == 0 && trig_mode == 1) { |
581 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
582 | d3e9db93 | bellard | apic_iter->arb_id = apic_iter->id ); |
583 | d592d303 | bellard | return;
|
584 | d592d303 | bellard | } |
585 | d592d303 | bellard | } |
586 | d592d303 | bellard | break;
|
587 | d592d303 | bellard | |
588 | d592d303 | bellard | case APIC_DM_SIPI:
|
589 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
590 | d3e9db93 | bellard | apic_startup(apic_iter, vector_num) ); |
591 | d592d303 | bellard | return;
|
592 | d592d303 | bellard | } |
593 | d592d303 | bellard | |
594 | d592d303 | bellard | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
595 | d592d303 | bellard | trigger_mode); |
596 | d592d303 | bellard | } |
597 | d592d303 | bellard | |
598 | 92a16d7a | Blue Swirl | int apic_get_interrupt(DeviceState *d)
|
599 | 574bbf7b | bellard | { |
600 | 92a16d7a | Blue Swirl | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
601 | 574bbf7b | bellard | int intno;
|
602 | 574bbf7b | bellard | |
603 | 574bbf7b | bellard | /* if the APIC is installed or enabled, we let the 8259 handle the
|
604 | 574bbf7b | bellard | IRQs */
|
605 | 574bbf7b | bellard | if (!s)
|
606 | 574bbf7b | bellard | return -1; |
607 | 574bbf7b | bellard | if (!(s->spurious_vec & APIC_SV_ENABLE))
|
608 | 574bbf7b | bellard | return -1; |
609 | 3b46e624 | ths | |
610 | 0fbfbb59 | Gleb Natapov | intno = apic_irq_pending(s); |
611 | 0fbfbb59 | Gleb Natapov | |
612 | 0fbfbb59 | Gleb Natapov | if (intno == 0) { |
613 | 574bbf7b | bellard | return -1; |
614 | 0fbfbb59 | Gleb Natapov | } else if (intno < 0) { |
615 | d592d303 | bellard | return s->spurious_vec & 0xff; |
616 | 0fbfbb59 | Gleb Natapov | } |
617 | b4511723 | bellard | reset_bit(s->irr, intno); |
618 | 574bbf7b | bellard | set_bit(s->isr, intno); |
619 | 574bbf7b | bellard | apic_update_irq(s); |
620 | 574bbf7b | bellard | return intno;
|
621 | 574bbf7b | bellard | } |
622 | 574bbf7b | bellard | |
623 | 92a16d7a | Blue Swirl | int apic_accept_pic_intr(DeviceState *d)
|
624 | 0e21e12b | ths | { |
625 | 92a16d7a | Blue Swirl | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
626 | 0e21e12b | ths | uint32_t lvt0; |
627 | 0e21e12b | ths | |
628 | 0e21e12b | ths | if (!s)
|
629 | 0e21e12b | ths | return -1; |
630 | 0e21e12b | ths | |
631 | 0e21e12b | ths | lvt0 = s->lvt[APIC_LVT_LINT0]; |
632 | 0e21e12b | ths | |
633 | a5b38b51 | aurel32 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
634 | a5b38b51 | aurel32 | (lvt0 & APIC_LVT_MASKED) == 0)
|
635 | 0e21e12b | ths | return 1; |
636 | 0e21e12b | ths | |
637 | 0e21e12b | ths | return 0; |
638 | 0e21e12b | ths | } |
639 | 0e21e12b | ths | |
640 | 574bbf7b | bellard | static uint32_t apic_get_current_count(APICState *s)
|
641 | 574bbf7b | bellard | { |
642 | 574bbf7b | bellard | int64_t d; |
643 | 574bbf7b | bellard | uint32_t val; |
644 | 74475455 | Paolo Bonzini | d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >> |
645 | 574bbf7b | bellard | s->count_shift; |
646 | 574bbf7b | bellard | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
647 | 574bbf7b | bellard | /* periodic */
|
648 | d592d303 | bellard | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
649 | 574bbf7b | bellard | } else {
|
650 | 574bbf7b | bellard | if (d >= s->initial_count)
|
651 | 574bbf7b | bellard | val = 0;
|
652 | 574bbf7b | bellard | else
|
653 | 574bbf7b | bellard | val = s->initial_count - d; |
654 | 574bbf7b | bellard | } |
655 | 574bbf7b | bellard | return val;
|
656 | 574bbf7b | bellard | } |
657 | 574bbf7b | bellard | |
658 | 574bbf7b | bellard | static void apic_timer_update(APICState *s, int64_t current_time) |
659 | 574bbf7b | bellard | { |
660 | 574bbf7b | bellard | int64_t next_time, d; |
661 | 3b46e624 | ths | |
662 | 574bbf7b | bellard | if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
|
663 | 5fafdf24 | ths | d = (current_time - s->initial_count_load_time) >> |
664 | 574bbf7b | bellard | s->count_shift; |
665 | 574bbf7b | bellard | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
666 | 681f8c29 | aliguori | if (!s->initial_count)
|
667 | 681f8c29 | aliguori | goto no_timer;
|
668 | d592d303 | bellard | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
669 | 574bbf7b | bellard | } else {
|
670 | 574bbf7b | bellard | if (d >= s->initial_count)
|
671 | 574bbf7b | bellard | goto no_timer;
|
672 | d592d303 | bellard | d = (uint64_t)s->initial_count + 1;
|
673 | 574bbf7b | bellard | } |
674 | 574bbf7b | bellard | next_time = s->initial_count_load_time + (d << s->count_shift); |
675 | 574bbf7b | bellard | qemu_mod_timer(s->timer, next_time); |
676 | 574bbf7b | bellard | s->next_time = next_time; |
677 | 574bbf7b | bellard | } else {
|
678 | 574bbf7b | bellard | no_timer:
|
679 | 574bbf7b | bellard | qemu_del_timer(s->timer); |
680 | 574bbf7b | bellard | } |
681 | 574bbf7b | bellard | } |
682 | 574bbf7b | bellard | |
683 | 574bbf7b | bellard | static void apic_timer(void *opaque) |
684 | 574bbf7b | bellard | { |
685 | 574bbf7b | bellard | APICState *s = opaque; |
686 | 574bbf7b | bellard | |
687 | cf6d64bf | Blue Swirl | apic_local_deliver(s, APIC_LVT_TIMER); |
688 | 574bbf7b | bellard | apic_timer_update(s, s->next_time); |
689 | 574bbf7b | bellard | } |
690 | 574bbf7b | bellard | |
691 | c227f099 | Anthony Liguori | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
692 | 574bbf7b | bellard | { |
693 | 574bbf7b | bellard | return 0; |
694 | 574bbf7b | bellard | } |
695 | 574bbf7b | bellard | |
696 | c227f099 | Anthony Liguori | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
697 | 574bbf7b | bellard | { |
698 | 574bbf7b | bellard | return 0; |
699 | 574bbf7b | bellard | } |
700 | 574bbf7b | bellard | |
701 | c227f099 | Anthony Liguori | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
702 | 574bbf7b | bellard | { |
703 | 574bbf7b | bellard | } |
704 | 574bbf7b | bellard | |
705 | c227f099 | Anthony Liguori | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
706 | 574bbf7b | bellard | { |
707 | 574bbf7b | bellard | } |
708 | 574bbf7b | bellard | |
709 | c227f099 | Anthony Liguori | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
710 | 574bbf7b | bellard | { |
711 | 92a16d7a | Blue Swirl | DeviceState *d; |
712 | 574bbf7b | bellard | APICState *s; |
713 | 574bbf7b | bellard | uint32_t val; |
714 | 574bbf7b | bellard | int index;
|
715 | 574bbf7b | bellard | |
716 | 92a16d7a | Blue Swirl | d = cpu_get_current_apic(); |
717 | 92a16d7a | Blue Swirl | if (!d) {
|
718 | 574bbf7b | bellard | return 0; |
719 | 0e26b7b8 | Blue Swirl | } |
720 | 92a16d7a | Blue Swirl | s = DO_UPCAST(APICState, busdev.qdev, d); |
721 | 574bbf7b | bellard | |
722 | 574bbf7b | bellard | index = (addr >> 4) & 0xff; |
723 | 574bbf7b | bellard | switch(index) {
|
724 | 574bbf7b | bellard | case 0x02: /* id */ |
725 | 574bbf7b | bellard | val = s->id << 24;
|
726 | 574bbf7b | bellard | break;
|
727 | 574bbf7b | bellard | case 0x03: /* version */ |
728 | 574bbf7b | bellard | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ |
729 | 574bbf7b | bellard | break;
|
730 | 574bbf7b | bellard | case 0x08: |
731 | 574bbf7b | bellard | val = s->tpr; |
732 | 574bbf7b | bellard | break;
|
733 | d592d303 | bellard | case 0x09: |
734 | d592d303 | bellard | val = apic_get_arb_pri(s); |
735 | d592d303 | bellard | break;
|
736 | 574bbf7b | bellard | case 0x0a: |
737 | 574bbf7b | bellard | /* ppr */
|
738 | 574bbf7b | bellard | val = apic_get_ppr(s); |
739 | 574bbf7b | bellard | break;
|
740 | b237db36 | aurel32 | case 0x0b: |
741 | b237db36 | aurel32 | val = 0;
|
742 | b237db36 | aurel32 | break;
|
743 | d592d303 | bellard | case 0x0d: |
744 | d592d303 | bellard | val = s->log_dest << 24;
|
745 | d592d303 | bellard | break;
|
746 | d592d303 | bellard | case 0x0e: |
747 | d592d303 | bellard | val = s->dest_mode << 28;
|
748 | d592d303 | bellard | break;
|
749 | 574bbf7b | bellard | case 0x0f: |
750 | 574bbf7b | bellard | val = s->spurious_vec; |
751 | 574bbf7b | bellard | break;
|
752 | 574bbf7b | bellard | case 0x10 ... 0x17: |
753 | 574bbf7b | bellard | val = s->isr[index & 7];
|
754 | 574bbf7b | bellard | break;
|
755 | 574bbf7b | bellard | case 0x18 ... 0x1f: |
756 | 574bbf7b | bellard | val = s->tmr[index & 7];
|
757 | 574bbf7b | bellard | break;
|
758 | 574bbf7b | bellard | case 0x20 ... 0x27: |
759 | 574bbf7b | bellard | val = s->irr[index & 7];
|
760 | 574bbf7b | bellard | break;
|
761 | 574bbf7b | bellard | case 0x28: |
762 | 574bbf7b | bellard | val = s->esr; |
763 | 574bbf7b | bellard | break;
|
764 | 574bbf7b | bellard | case 0x30: |
765 | 574bbf7b | bellard | case 0x31: |
766 | 574bbf7b | bellard | val = s->icr[index & 1];
|
767 | 574bbf7b | bellard | break;
|
768 | e0fd8781 | bellard | case 0x32 ... 0x37: |
769 | e0fd8781 | bellard | val = s->lvt[index - 0x32];
|
770 | e0fd8781 | bellard | break;
|
771 | 574bbf7b | bellard | case 0x38: |
772 | 574bbf7b | bellard | val = s->initial_count; |
773 | 574bbf7b | bellard | break;
|
774 | 574bbf7b | bellard | case 0x39: |
775 | 574bbf7b | bellard | val = apic_get_current_count(s); |
776 | 574bbf7b | bellard | break;
|
777 | 574bbf7b | bellard | case 0x3e: |
778 | 574bbf7b | bellard | val = s->divide_conf; |
779 | 574bbf7b | bellard | break;
|
780 | 574bbf7b | bellard | default:
|
781 | 574bbf7b | bellard | s->esr |= ESR_ILLEGAL_ADDRESS; |
782 | 574bbf7b | bellard | val = 0;
|
783 | 574bbf7b | bellard | break;
|
784 | 574bbf7b | bellard | } |
785 | d8023f31 | Blue Swirl | trace_apic_mem_readl(addr, val); |
786 | 574bbf7b | bellard | return val;
|
787 | 574bbf7b | bellard | } |
788 | 574bbf7b | bellard | |
789 | f5095c63 | Andreas Fรคrber | static void apic_send_msi(target_phys_addr_t addr, uint32_t data) |
790 | 54c96da7 | Michael S. Tsirkin | { |
791 | 54c96da7 | Michael S. Tsirkin | uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
792 | 54c96da7 | Michael S. Tsirkin | uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; |
793 | 54c96da7 | Michael S. Tsirkin | uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
|
794 | 54c96da7 | Michael S. Tsirkin | uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
|
795 | 54c96da7 | Michael S. Tsirkin | uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
|
796 | 54c96da7 | Michael S. Tsirkin | /* XXX: Ignore redirection hint. */
|
797 | 54c96da7 | Michael S. Tsirkin | apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
|
798 | 54c96da7 | Michael S. Tsirkin | } |
799 | 54c96da7 | Michael S. Tsirkin | |
800 | c227f099 | Anthony Liguori | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
801 | 574bbf7b | bellard | { |
802 | 92a16d7a | Blue Swirl | DeviceState *d; |
803 | 574bbf7b | bellard | APICState *s; |
804 | 54c96da7 | Michael S. Tsirkin | int index = (addr >> 4) & 0xff; |
805 | 54c96da7 | Michael S. Tsirkin | if (addr > 0xfff || !index) { |
806 | 54c96da7 | Michael S. Tsirkin | /* MSI and MMIO APIC are at the same memory location,
|
807 | 54c96da7 | Michael S. Tsirkin | * but actually not on the global bus: MSI is on PCI bus
|
808 | 54c96da7 | Michael S. Tsirkin | * APIC is connected directly to the CPU.
|
809 | 54c96da7 | Michael S. Tsirkin | * Mapping them on the global bus happens to work because
|
810 | 54c96da7 | Michael S. Tsirkin | * MSI registers are reserved in APIC MMIO and vice versa. */
|
811 | 54c96da7 | Michael S. Tsirkin | apic_send_msi(addr, val); |
812 | 54c96da7 | Michael S. Tsirkin | return;
|
813 | 54c96da7 | Michael S. Tsirkin | } |
814 | 574bbf7b | bellard | |
815 | 92a16d7a | Blue Swirl | d = cpu_get_current_apic(); |
816 | 92a16d7a | Blue Swirl | if (!d) {
|
817 | 574bbf7b | bellard | return;
|
818 | 0e26b7b8 | Blue Swirl | } |
819 | 92a16d7a | Blue Swirl | s = DO_UPCAST(APICState, busdev.qdev, d); |
820 | 574bbf7b | bellard | |
821 | d8023f31 | Blue Swirl | trace_apic_mem_writel(addr, val); |
822 | 574bbf7b | bellard | |
823 | 574bbf7b | bellard | switch(index) {
|
824 | 574bbf7b | bellard | case 0x02: |
825 | 574bbf7b | bellard | s->id = (val >> 24);
|
826 | 574bbf7b | bellard | break;
|
827 | e0fd8781 | bellard | case 0x03: |
828 | e0fd8781 | bellard | break;
|
829 | 574bbf7b | bellard | case 0x08: |
830 | 574bbf7b | bellard | s->tpr = val; |
831 | d592d303 | bellard | apic_update_irq(s); |
832 | 574bbf7b | bellard | break;
|
833 | e0fd8781 | bellard | case 0x09: |
834 | e0fd8781 | bellard | case 0x0a: |
835 | e0fd8781 | bellard | break;
|
836 | 574bbf7b | bellard | case 0x0b: /* EOI */ |
837 | 574bbf7b | bellard | apic_eoi(s); |
838 | 574bbf7b | bellard | break;
|
839 | d592d303 | bellard | case 0x0d: |
840 | d592d303 | bellard | s->log_dest = val >> 24;
|
841 | d592d303 | bellard | break;
|
842 | d592d303 | bellard | case 0x0e: |
843 | d592d303 | bellard | s->dest_mode = val >> 28;
|
844 | d592d303 | bellard | break;
|
845 | 574bbf7b | bellard | case 0x0f: |
846 | 574bbf7b | bellard | s->spurious_vec = val & 0x1ff;
|
847 | d592d303 | bellard | apic_update_irq(s); |
848 | 574bbf7b | bellard | break;
|
849 | e0fd8781 | bellard | case 0x10 ... 0x17: |
850 | e0fd8781 | bellard | case 0x18 ... 0x1f: |
851 | e0fd8781 | bellard | case 0x20 ... 0x27: |
852 | e0fd8781 | bellard | case 0x28: |
853 | e0fd8781 | bellard | break;
|
854 | 574bbf7b | bellard | case 0x30: |
855 | d592d303 | bellard | s->icr[0] = val;
|
856 | 92a16d7a | Blue Swirl | apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
857 | d592d303 | bellard | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
858 | d592d303 | bellard | (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); |
859 | d592d303 | bellard | break;
|
860 | 574bbf7b | bellard | case 0x31: |
861 | d592d303 | bellard | s->icr[1] = val;
|
862 | 574bbf7b | bellard | break;
|
863 | 574bbf7b | bellard | case 0x32 ... 0x37: |
864 | 574bbf7b | bellard | { |
865 | 574bbf7b | bellard | int n = index - 0x32; |
866 | 574bbf7b | bellard | s->lvt[n] = val; |
867 | 574bbf7b | bellard | if (n == APIC_LVT_TIMER)
|
868 | 74475455 | Paolo Bonzini | apic_timer_update(s, qemu_get_clock_ns(vm_clock)); |
869 | 574bbf7b | bellard | } |
870 | 574bbf7b | bellard | break;
|
871 | 574bbf7b | bellard | case 0x38: |
872 | 574bbf7b | bellard | s->initial_count = val; |
873 | 74475455 | Paolo Bonzini | s->initial_count_load_time = qemu_get_clock_ns(vm_clock); |
874 | 574bbf7b | bellard | apic_timer_update(s, s->initial_count_load_time); |
875 | 574bbf7b | bellard | break;
|
876 | e0fd8781 | bellard | case 0x39: |
877 | e0fd8781 | bellard | break;
|
878 | 574bbf7b | bellard | case 0x3e: |
879 | 574bbf7b | bellard | { |
880 | 574bbf7b | bellard | int v;
|
881 | 574bbf7b | bellard | s->divide_conf = val & 0xb;
|
882 | 574bbf7b | bellard | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
883 | 574bbf7b | bellard | s->count_shift = (v + 1) & 7; |
884 | 574bbf7b | bellard | } |
885 | 574bbf7b | bellard | break;
|
886 | 574bbf7b | bellard | default:
|
887 | 574bbf7b | bellard | s->esr |= ESR_ILLEGAL_ADDRESS; |
888 | 574bbf7b | bellard | break;
|
889 | 574bbf7b | bellard | } |
890 | 574bbf7b | bellard | } |
891 | 574bbf7b | bellard | |
892 | 695dcf71 | Juan Quintela | /* This function is only used for old state version 1 and 2 */
|
893 | 695dcf71 | Juan Quintela | static int apic_load_old(QEMUFile *f, void *opaque, int version_id) |
894 | d592d303 | bellard | { |
895 | d592d303 | bellard | APICState *s = opaque; |
896 | d592d303 | bellard | int i;
|
897 | d592d303 | bellard | |
898 | e6cf6a8c | bellard | if (version_id > 2) |
899 | d592d303 | bellard | return -EINVAL;
|
900 | d592d303 | bellard | |
901 | d592d303 | bellard | /* XXX: what if the base changes? (registered memory regions) */
|
902 | d592d303 | bellard | qemu_get_be32s(f, &s->apicbase); |
903 | d592d303 | bellard | qemu_get_8s(f, &s->id); |
904 | d592d303 | bellard | qemu_get_8s(f, &s->arb_id); |
905 | d592d303 | bellard | qemu_get_8s(f, &s->tpr); |
906 | d592d303 | bellard | qemu_get_be32s(f, &s->spurious_vec); |
907 | d592d303 | bellard | qemu_get_8s(f, &s->log_dest); |
908 | d592d303 | bellard | qemu_get_8s(f, &s->dest_mode); |
909 | d592d303 | bellard | for (i = 0; i < 8; i++) { |
910 | d592d303 | bellard | qemu_get_be32s(f, &s->isr[i]); |
911 | d592d303 | bellard | qemu_get_be32s(f, &s->tmr[i]); |
912 | d592d303 | bellard | qemu_get_be32s(f, &s->irr[i]); |
913 | d592d303 | bellard | } |
914 | d592d303 | bellard | for (i = 0; i < APIC_LVT_NB; i++) { |
915 | d592d303 | bellard | qemu_get_be32s(f, &s->lvt[i]); |
916 | d592d303 | bellard | } |
917 | d592d303 | bellard | qemu_get_be32s(f, &s->esr); |
918 | d592d303 | bellard | qemu_get_be32s(f, &s->icr[0]);
|
919 | d592d303 | bellard | qemu_get_be32s(f, &s->icr[1]);
|
920 | d592d303 | bellard | qemu_get_be32s(f, &s->divide_conf); |
921 | bee8d684 | ths | s->count_shift=qemu_get_be32(f); |
922 | d592d303 | bellard | qemu_get_be32s(f, &s->initial_count); |
923 | bee8d684 | ths | s->initial_count_load_time=qemu_get_be64(f); |
924 | bee8d684 | ths | s->next_time=qemu_get_be64(f); |
925 | e6cf6a8c | bellard | |
926 | e6cf6a8c | bellard | if (version_id >= 2) |
927 | e6cf6a8c | bellard | qemu_get_timer(f, s->timer); |
928 | d592d303 | bellard | return 0; |
929 | d592d303 | bellard | } |
930 | 574bbf7b | bellard | |
931 | 695dcf71 | Juan Quintela | static const VMStateDescription vmstate_apic = { |
932 | 695dcf71 | Juan Quintela | .name = "apic",
|
933 | 695dcf71 | Juan Quintela | .version_id = 3,
|
934 | 695dcf71 | Juan Quintela | .minimum_version_id = 3,
|
935 | 695dcf71 | Juan Quintela | .minimum_version_id_old = 1,
|
936 | 695dcf71 | Juan Quintela | .load_state_old = apic_load_old, |
937 | 695dcf71 | Juan Quintela | .fields = (VMStateField []) { |
938 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(apicbase, APICState), |
939 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(id, APICState), |
940 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(arb_id, APICState), |
941 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(tpr, APICState), |
942 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(spurious_vec, APICState), |
943 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(log_dest, APICState), |
944 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(dest_mode, APICState), |
945 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(isr, APICState, 8),
|
946 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
|
947 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(irr, APICState, 8),
|
948 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB), |
949 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(esr, APICState), |
950 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(icr, APICState, 2),
|
951 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(divide_conf, APICState), |
952 | 695dcf71 | Juan Quintela | VMSTATE_INT32(count_shift, APICState), |
953 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(initial_count, APICState), |
954 | 695dcf71 | Juan Quintela | VMSTATE_INT64(initial_count_load_time, APICState), |
955 | 695dcf71 | Juan Quintela | VMSTATE_INT64(next_time, APICState), |
956 | 695dcf71 | Juan Quintela | VMSTATE_TIMER(timer, APICState), |
957 | 695dcf71 | Juan Quintela | VMSTATE_END_OF_LIST() |
958 | 695dcf71 | Juan Quintela | } |
959 | 695dcf71 | Juan Quintela | }; |
960 | 695dcf71 | Juan Quintela | |
961 | 8546b099 | Blue Swirl | static void apic_reset(DeviceState *d) |
962 | d592d303 | bellard | { |
963 | 8546b099 | Blue Swirl | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
964 | 4c0960c0 | Avi Kivity | int bsp;
|
965 | fec5fa02 | aurel32 | |
966 | 4c0960c0 | Avi Kivity | bsp = cpu_is_bsp(s->cpu_env); |
967 | fec5fa02 | aurel32 | s->apicbase = 0xfee00000 |
|
968 | 678e12cc | Gleb Natapov | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
|
969 | fec5fa02 | aurel32 | |
970 | 92a16d7a | Blue Swirl | apic_init_reset(d); |
971 | 0e21e12b | ths | |
972 | 678e12cc | Gleb Natapov | if (bsp) {
|
973 | a5b38b51 | aurel32 | /*
|
974 | a5b38b51 | aurel32 | * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
|
975 | a5b38b51 | aurel32 | * time typically by BIOS, so PIC interrupt can be delivered to the
|
976 | a5b38b51 | aurel32 | * processor when local APIC is enabled.
|
977 | a5b38b51 | aurel32 | */
|
978 | a5b38b51 | aurel32 | s->lvt[APIC_LVT_LINT0] = 0x700;
|
979 | a5b38b51 | aurel32 | } |
980 | d592d303 | bellard | } |
981 | 574bbf7b | bellard | |
982 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const apic_mem_read[3] = { |
983 | 574bbf7b | bellard | apic_mem_readb, |
984 | 574bbf7b | bellard | apic_mem_readw, |
985 | 574bbf7b | bellard | apic_mem_readl, |
986 | 574bbf7b | bellard | }; |
987 | 574bbf7b | bellard | |
988 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const apic_mem_write[3] = { |
989 | 574bbf7b | bellard | apic_mem_writeb, |
990 | 574bbf7b | bellard | apic_mem_writew, |
991 | 574bbf7b | bellard | apic_mem_writel, |
992 | 574bbf7b | bellard | }; |
993 | 574bbf7b | bellard | |
994 | 8546b099 | Blue Swirl | static int apic_init1(SysBusDevice *dev) |
995 | 8546b099 | Blue Swirl | { |
996 | 8546b099 | Blue Swirl | APICState *s = FROM_SYSBUS(APICState, dev); |
997 | 8546b099 | Blue Swirl | int apic_io_memory;
|
998 | 8546b099 | Blue Swirl | static int last_apic_idx; |
999 | 8546b099 | Blue Swirl | |
1000 | 8546b099 | Blue Swirl | if (last_apic_idx >= MAX_APICS) {
|
1001 | 8546b099 | Blue Swirl | return -1; |
1002 | 8546b099 | Blue Swirl | } |
1003 | 8546b099 | Blue Swirl | apic_io_memory = cpu_register_io_memory(apic_mem_read, |
1004 | 2507c12a | Alexander Graf | apic_mem_write, NULL,
|
1005 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
1006 | 8546b099 | Blue Swirl | sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory); |
1007 | 8546b099 | Blue Swirl | |
1008 | 74475455 | Paolo Bonzini | s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s); |
1009 | 8546b099 | Blue Swirl | s->idx = last_apic_idx++; |
1010 | 8546b099 | Blue Swirl | local_apics[s->idx] = s; |
1011 | 8546b099 | Blue Swirl | return 0; |
1012 | 8546b099 | Blue Swirl | } |
1013 | 8546b099 | Blue Swirl | |
1014 | 8546b099 | Blue Swirl | static SysBusDeviceInfo apic_info = {
|
1015 | 8546b099 | Blue Swirl | .init = apic_init1, |
1016 | 8546b099 | Blue Swirl | .qdev.name = "apic",
|
1017 | 8546b099 | Blue Swirl | .qdev.size = sizeof(APICState),
|
1018 | 8546b099 | Blue Swirl | .qdev.vmsd = &vmstate_apic, |
1019 | 8546b099 | Blue Swirl | .qdev.reset = apic_reset, |
1020 | 8546b099 | Blue Swirl | .qdev.no_user = 1,
|
1021 | 8546b099 | Blue Swirl | .qdev.props = (Property[]) { |
1022 | 8546b099 | Blue Swirl | DEFINE_PROP_UINT8("id", APICState, id, -1), |
1023 | 8546b099 | Blue Swirl | DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
|
1024 | 8546b099 | Blue Swirl | DEFINE_PROP_END_OF_LIST(), |
1025 | 8546b099 | Blue Swirl | } |
1026 | 8546b099 | Blue Swirl | }; |
1027 | 8546b099 | Blue Swirl | |
1028 | 8546b099 | Blue Swirl | static void apic_register_devices(void) |
1029 | 8546b099 | Blue Swirl | { |
1030 | 8546b099 | Blue Swirl | sysbus_register_withprop(&apic_info); |
1031 | 8546b099 | Blue Swirl | } |
1032 | 8546b099 | Blue Swirl | |
1033 | 8546b099 | Blue Swirl | device_init(apic_register_devices) |