Implement hcall based RTAS for pSeries machines
On pSeries machines, operating systems can instantiate "RTAS" (Run-TimeAbstraction Services), a runtime component of the firmware which implementsa number of low-level, infrequently used operations. On logical partitions...
Clean up slb_lookup() function
The slb_lookup() function, used in the ppc translation path returns anumber of slb entry fields in reference parameters. However, only oneof the two callers of slb_lookup() actually wants this information.
This patch, therefore, makes slb_lookup() return a simple pointer to the...
Parse SDR1 on mtspr instead of at translate time
On ppc machines with hash table MMUs, the special purpose register SDR1contains both the base address of the encoded size (hashed) page tables.
At present, we interpret the SDR1 value within the address translation...
Use "hash" more consistently in ppc mmu code
Currently, get_segment() has a variable called hash. However it doesn't(quite) get the hash value for the ppc hashed page table. Instead itgets the hash shifted - effectively the offset of the hash bucket within...
Better factor the ppc hash translation path
Currently the path handling hash page table translation in get_segment()has a mix of common and 32 or 64 bit specific code. However thedivision is not done terribly well which results in a lot of messy codeflipping between common and divided paths....
Support 1T segments on ppc
Traditionally, the "segments" used for the two-stage translation used onpowerpc MMUs were 256MB in size. This was the only option on all hashpage table based 32-bit powerpc cpus, and on the earlier 64-bit hash pagetable based cpus. However, newer 64-bit cpus also permit 1TB segments...
Add POWER7 support for ppc
This adds emulation support for the recent POWER7 cpu to qemu. It's farfrom perfect - it's missing a number of POWER7 features so far, includingany support for VSX or decimal floating point instructions. However, it'sclose enough to boot a kernel with the POWER7 PVR....
Start implementing pSeries logical partition machine
This patch adds a "pseries" machine to qemu. This aims to emulate alogical partition on an IBM pSeries machine, compliant to the"PowerPC Architecture Platform Requirements" (PAPR) document.
This initial version is quite limited, it implements a basic machine...
Implement the bus structure for PAPR virtual IO
This extends the "pseries" (PAPR) machine to include a virtual IO bussupporting the PAPR defined hypercall based virtual IO mechanisms.
So far only one VIO device is provided, the vty / vterm, providinga full console (polled only, for now)....
Virtual hash page table handling on pSeries machine
On pSeries logical partitions, excepting the old POWER4-style full systempartitions, the guest does not have direct access to the hardware pagetable. Instead, the pagetable exists in hypervisor memory, and the guest...
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