root / target-microblaze / helper.c @ 39bffca2
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1 | 4acb54ba | Edgar E. Iglesias | /*
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2 | 4acb54ba | Edgar E. Iglesias | * MicroBlaze helper routines.
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3 | 4acb54ba | Edgar E. Iglesias | *
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4 | 4acb54ba | Edgar E. Iglesias | * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
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5 | 4acb54ba | Edgar E. Iglesias | *
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6 | 4acb54ba | Edgar E. Iglesias | * This library is free software; you can redistribute it and/or
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7 | 4acb54ba | Edgar E. Iglesias | * modify it under the terms of the GNU Lesser General Public
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8 | 4acb54ba | Edgar E. Iglesias | * License as published by the Free Software Foundation; either
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9 | 4acb54ba | Edgar E. Iglesias | * version 2 of the License, or (at your option) any later version.
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10 | 4acb54ba | Edgar E. Iglesias | *
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11 | 4acb54ba | Edgar E. Iglesias | * This library is distributed in the hope that it will be useful,
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12 | 4acb54ba | Edgar E. Iglesias | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 4acb54ba | Edgar E. Iglesias | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 4acb54ba | Edgar E. Iglesias | * Lesser General Public License for more details.
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15 | 4acb54ba | Edgar E. Iglesias | *
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16 | 4acb54ba | Edgar E. Iglesias | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 4acb54ba | Edgar E. Iglesias | */
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19 | 4acb54ba | Edgar E. Iglesias | |
20 | 4acb54ba | Edgar E. Iglesias | #include <stdio.h> |
21 | 4acb54ba | Edgar E. Iglesias | #include <string.h> |
22 | 4acb54ba | Edgar E. Iglesias | #include <assert.h> |
23 | 4acb54ba | Edgar E. Iglesias | |
24 | 4acb54ba | Edgar E. Iglesias | #include "config.h" |
25 | 4acb54ba | Edgar E. Iglesias | #include "cpu.h" |
26 | 4acb54ba | Edgar E. Iglesias | #include "host-utils.h" |
27 | 4acb54ba | Edgar E. Iglesias | |
28 | 4acb54ba | Edgar E. Iglesias | #define D(x)
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29 | 4acb54ba | Edgar E. Iglesias | #define DMMU(x)
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30 | 4acb54ba | Edgar E. Iglesias | |
31 | 4acb54ba | Edgar E. Iglesias | #if defined(CONFIG_USER_ONLY)
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32 | 4acb54ba | Edgar E. Iglesias | |
33 | 4acb54ba | Edgar E. Iglesias | void do_interrupt (CPUState *env)
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34 | 4acb54ba | Edgar E. Iglesias | { |
35 | 4acb54ba | Edgar E. Iglesias | env->exception_index = -1;
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36 | 4acb54ba | Edgar E. Iglesias | env->regs[14] = env->sregs[SR_PC];
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37 | 4acb54ba | Edgar E. Iglesias | } |
38 | 4acb54ba | Edgar E. Iglesias | |
39 | 4acb54ba | Edgar E. Iglesias | int cpu_mb_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
40 | 97b348e7 | Blue Swirl | int mmu_idx)
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41 | 4acb54ba | Edgar E. Iglesias | { |
42 | 4acb54ba | Edgar E. Iglesias | env->exception_index = 0xaa;
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43 | 4acb54ba | Edgar E. Iglesias | cpu_dump_state(env, stderr, fprintf, 0);
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44 | 4acb54ba | Edgar E. Iglesias | return 1; |
45 | 4acb54ba | Edgar E. Iglesias | } |
46 | 4acb54ba | Edgar E. Iglesias | |
47 | 4acb54ba | Edgar E. Iglesias | #else /* !CONFIG_USER_ONLY */ |
48 | 4acb54ba | Edgar E. Iglesias | |
49 | 4acb54ba | Edgar E. Iglesias | int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
50 | 97b348e7 | Blue Swirl | int mmu_idx)
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51 | 4acb54ba | Edgar E. Iglesias | { |
52 | 4acb54ba | Edgar E. Iglesias | unsigned int hit; |
53 | 4acb54ba | Edgar E. Iglesias | unsigned int mmu_available; |
54 | 4acb54ba | Edgar E. Iglesias | int r = 1; |
55 | 4acb54ba | Edgar E. Iglesias | int prot;
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56 | 4acb54ba | Edgar E. Iglesias | |
57 | 4acb54ba | Edgar E. Iglesias | mmu_available = 0;
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58 | 4acb54ba | Edgar E. Iglesias | if (env->pvr.regs[0] & PVR0_USE_MMU) { |
59 | 4acb54ba | Edgar E. Iglesias | mmu_available = 1;
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60 | 4acb54ba | Edgar E. Iglesias | if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK) |
61 | 4acb54ba | Edgar E. Iglesias | && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
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62 | 4acb54ba | Edgar E. Iglesias | mmu_available = 0;
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63 | 4acb54ba | Edgar E. Iglesias | } |
64 | 4acb54ba | Edgar E. Iglesias | } |
65 | 4acb54ba | Edgar E. Iglesias | |
66 | 4acb54ba | Edgar E. Iglesias | /* Translate if the MMU is available and enabled. */
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67 | 4acb54ba | Edgar E. Iglesias | if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
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68 | 4acb54ba | Edgar E. Iglesias | target_ulong vaddr, paddr; |
69 | 4acb54ba | Edgar E. Iglesias | struct microblaze_mmu_lookup lu;
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70 | 4acb54ba | Edgar E. Iglesias | |
71 | 4acb54ba | Edgar E. Iglesias | hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx); |
72 | 4acb54ba | Edgar E. Iglesias | if (hit) {
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73 | 4acb54ba | Edgar E. Iglesias | vaddr = address & TARGET_PAGE_MASK; |
74 | 4acb54ba | Edgar E. Iglesias | paddr = lu.paddr + vaddr - lu.vaddr; |
75 | 4acb54ba | Edgar E. Iglesias | |
76 | 4acb54ba | Edgar E. Iglesias | DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
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77 | 4acb54ba | Edgar E. Iglesias | mmu_idx, vaddr, paddr, lu.prot)); |
78 | d4c430a8 | Paul Brook | tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); |
79 | d4c430a8 | Paul Brook | r = 0;
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80 | 4acb54ba | Edgar E. Iglesias | } else {
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81 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_EAR] = address; |
82 | 21d20636 | Edgar E. Iglesias | DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address));
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83 | 4acb54ba | Edgar E. Iglesias | |
84 | 4acb54ba | Edgar E. Iglesias | switch (lu.err) {
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85 | 4acb54ba | Edgar E. Iglesias | case ERR_PROT:
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86 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_ESR] = rw == 2 ? 17 : 16; |
87 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_ESR] |= (rw == 1) << 10; |
88 | 4acb54ba | Edgar E. Iglesias | break;
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89 | 4acb54ba | Edgar E. Iglesias | case ERR_MISS:
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90 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_ESR] = rw == 2 ? 19 : 18; |
91 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_ESR] |= (rw == 1) << 10; |
92 | 4acb54ba | Edgar E. Iglesias | break;
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93 | 4acb54ba | Edgar E. Iglesias | default:
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94 | 4acb54ba | Edgar E. Iglesias | abort(); |
95 | 4acb54ba | Edgar E. Iglesias | break;
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96 | 4acb54ba | Edgar E. Iglesias | } |
97 | 4acb54ba | Edgar E. Iglesias | |
98 | 4acb54ba | Edgar E. Iglesias | if (env->exception_index == EXCP_MMU) {
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99 | 4acb54ba | Edgar E. Iglesias | cpu_abort(env, "recursive faults\n");
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100 | 4acb54ba | Edgar E. Iglesias | } |
101 | 4acb54ba | Edgar E. Iglesias | |
102 | 4acb54ba | Edgar E. Iglesias | /* TLB miss. */
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103 | 4acb54ba | Edgar E. Iglesias | env->exception_index = EXCP_MMU; |
104 | 4acb54ba | Edgar E. Iglesias | } |
105 | 4acb54ba | Edgar E. Iglesias | } else {
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106 | 4acb54ba | Edgar E. Iglesias | /* MMU disabled or not available. */
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107 | 4acb54ba | Edgar E. Iglesias | address &= TARGET_PAGE_MASK; |
108 | 4acb54ba | Edgar E. Iglesias | prot = PAGE_BITS; |
109 | d4c430a8 | Paul Brook | tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); |
110 | d4c430a8 | Paul Brook | r = 0;
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111 | 4acb54ba | Edgar E. Iglesias | } |
112 | 4acb54ba | Edgar E. Iglesias | return r;
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113 | 4acb54ba | Edgar E. Iglesias | } |
114 | 4acb54ba | Edgar E. Iglesias | |
115 | 4acb54ba | Edgar E. Iglesias | void do_interrupt(CPUState *env)
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116 | 4acb54ba | Edgar E. Iglesias | { |
117 | 4acb54ba | Edgar E. Iglesias | uint32_t t; |
118 | 4acb54ba | Edgar E. Iglesias | |
119 | 5225d669 | Stefan Weil | /* IMM flag cannot propagate across a branch and into the dslot. */
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120 | 4acb54ba | Edgar E. Iglesias | assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); |
121 | 4acb54ba | Edgar E. Iglesias | assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); |
122 | 4acb54ba | Edgar E. Iglesias | /* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
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123 | 4acb54ba | Edgar E. Iglesias | switch (env->exception_index) {
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124 | cedb936b | Edgar E. Iglesias | case EXCP_HW_EXCP:
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125 | cedb936b | Edgar E. Iglesias | if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { |
126 | cedb936b | Edgar E. Iglesias | qemu_log("Exception raised on system without exceptions!\n");
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127 | cedb936b | Edgar E. Iglesias | return;
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128 | cedb936b | Edgar E. Iglesias | } |
129 | cedb936b | Edgar E. Iglesias | |
130 | cedb936b | Edgar E. Iglesias | env->regs[17] = env->sregs[SR_PC] + 4; |
131 | cedb936b | Edgar E. Iglesias | env->sregs[SR_ESR] &= ~(1 << 12); |
132 | cedb936b | Edgar E. Iglesias | |
133 | cedb936b | Edgar E. Iglesias | /* Exception breaks branch + dslot sequence? */
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134 | cedb936b | Edgar E. Iglesias | if (env->iflags & D_FLAG) {
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135 | cedb936b | Edgar E. Iglesias | env->sregs[SR_ESR] |= 1 << 12 ; |
136 | cedb936b | Edgar E. Iglesias | env->sregs[SR_BTR] = env->btarget; |
137 | cedb936b | Edgar E. Iglesias | } |
138 | cedb936b | Edgar E. Iglesias | |
139 | cedb936b | Edgar E. Iglesias | /* Disable the MMU. */
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140 | cedb936b | Edgar E. Iglesias | t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
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141 | cedb936b | Edgar E. Iglesias | env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); |
142 | cedb936b | Edgar E. Iglesias | env->sregs[SR_MSR] |= t; |
143 | cedb936b | Edgar E. Iglesias | /* Exception in progress. */
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144 | cedb936b | Edgar E. Iglesias | env->sregs[SR_MSR] |= MSR_EIP; |
145 | cedb936b | Edgar E. Iglesias | |
146 | cedb936b | Edgar E. Iglesias | qemu_log_mask(CPU_LOG_INT, |
147 | cedb936b | Edgar E. Iglesias | "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
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148 | cedb936b | Edgar E. Iglesias | env->sregs[SR_PC], env->sregs[SR_EAR], |
149 | cedb936b | Edgar E. Iglesias | env->sregs[SR_ESR], env->iflags); |
150 | cedb936b | Edgar E. Iglesias | log_cpu_state_mask(CPU_LOG_INT, env, 0);
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151 | cedb936b | Edgar E. Iglesias | env->iflags &= ~(IMM_FLAG | D_FLAG); |
152 | cedb936b | Edgar E. Iglesias | env->sregs[SR_PC] = 0x20;
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153 | cedb936b | Edgar E. Iglesias | break;
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154 | cedb936b | Edgar E. Iglesias | |
155 | 4acb54ba | Edgar E. Iglesias | case EXCP_MMU:
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156 | 4acb54ba | Edgar E. Iglesias | env->regs[17] = env->sregs[SR_PC];
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157 | 4acb54ba | Edgar E. Iglesias | |
158 | a75cf0c5 | Edgar E. Iglesias | env->sregs[SR_ESR] &= ~(1 << 12); |
159 | 4acb54ba | Edgar E. Iglesias | /* Exception breaks branch + dslot sequence? */
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160 | 4acb54ba | Edgar E. Iglesias | if (env->iflags & D_FLAG) {
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161 | 4acb54ba | Edgar E. Iglesias | D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
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162 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_ESR] |= 1 << 12 ; |
163 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_BTR] = env->btarget; |
164 | 4acb54ba | Edgar E. Iglesias | |
165 | 4acb54ba | Edgar E. Iglesias | /* Reexecute the branch. */
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166 | 4acb54ba | Edgar E. Iglesias | env->regs[17] -= 4; |
167 | 4acb54ba | Edgar E. Iglesias | /* was the branch immprefixed?. */
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168 | 4acb54ba | Edgar E. Iglesias | if (env->bimm) {
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169 | 4acb54ba | Edgar E. Iglesias | qemu_log_mask(CPU_LOG_INT, |
170 | 4acb54ba | Edgar E. Iglesias | "bimm exception at pc=%x iflags=%x\n",
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171 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_PC], env->iflags); |
172 | 4acb54ba | Edgar E. Iglesias | env->regs[17] -= 4; |
173 | 4acb54ba | Edgar E. Iglesias | log_cpu_state_mask(CPU_LOG_INT, env, 0);
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174 | 4acb54ba | Edgar E. Iglesias | } |
175 | 4acb54ba | Edgar E. Iglesias | } else if (env->iflags & IMM_FLAG) { |
176 | 4acb54ba | Edgar E. Iglesias | D(qemu_log("IMM_FLAG set at exception\n"));
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177 | 4acb54ba | Edgar E. Iglesias | env->regs[17] -= 4; |
178 | 4acb54ba | Edgar E. Iglesias | } |
179 | 4acb54ba | Edgar E. Iglesias | |
180 | 4acb54ba | Edgar E. Iglesias | /* Disable the MMU. */
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181 | 4acb54ba | Edgar E. Iglesias | t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
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182 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); |
183 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_MSR] |= t; |
184 | 4acb54ba | Edgar E. Iglesias | /* Exception in progress. */
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185 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_MSR] |= MSR_EIP; |
186 | 4acb54ba | Edgar E. Iglesias | |
187 | 4acb54ba | Edgar E. Iglesias | qemu_log_mask(CPU_LOG_INT, |
188 | 4acb54ba | Edgar E. Iglesias | "exception at pc=%x ear=%x iflags=%x\n",
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189 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); |
190 | 4acb54ba | Edgar E. Iglesias | log_cpu_state_mask(CPU_LOG_INT, env, 0);
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191 | 4acb54ba | Edgar E. Iglesias | env->iflags &= ~(IMM_FLAG | D_FLAG); |
192 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_PC] = 0x20;
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193 | 4acb54ba | Edgar E. Iglesias | break;
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194 | 4acb54ba | Edgar E. Iglesias | |
195 | 4acb54ba | Edgar E. Iglesias | case EXCP_IRQ:
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196 | 4acb54ba | Edgar E. Iglesias | assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))); |
197 | 4acb54ba | Edgar E. Iglesias | assert(env->sregs[SR_MSR] & MSR_IE); |
198 | 4acb54ba | Edgar E. Iglesias | assert(!(env->iflags & D_FLAG)); |
199 | 4acb54ba | Edgar E. Iglesias | |
200 | 4acb54ba | Edgar E. Iglesias | t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
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201 | 4acb54ba | Edgar E. Iglesias | |
202 | 4acb54ba | Edgar E. Iglesias | #if 0
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203 | 4acb54ba | Edgar E. Iglesias | #include "disas.h"
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204 | 4acb54ba | Edgar E. Iglesias | |
205 | 4acb54ba | Edgar E. Iglesias | /* Useful instrumentation when debugging interrupt issues in either
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206 | 4acb54ba | Edgar E. Iglesias | the models or in sw. */
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207 | 4acb54ba | Edgar E. Iglesias | {
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208 | 4acb54ba | Edgar E. Iglesias | const char *sym;
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209 | 4acb54ba | Edgar E. Iglesias | |
210 | 4acb54ba | Edgar E. Iglesias | sym = lookup_symbol(env->sregs[SR_PC]);
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211 | 4acb54ba | Edgar E. Iglesias | if (sym
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212 | 4acb54ba | Edgar E. Iglesias | && (!strcmp("netif_rx", sym)
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213 | 4acb54ba | Edgar E. Iglesias | || !strcmp("process_backlog", sym))) {
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214 | 4acb54ba | Edgar E. Iglesias | |
215 | 4acb54ba | Edgar E. Iglesias | qemu_log(
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216 | 4acb54ba | Edgar E. Iglesias | "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
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217 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
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218 | 4acb54ba | Edgar E. Iglesias | sym);
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219 | 4acb54ba | Edgar E. Iglesias | |
220 | 4acb54ba | Edgar E. Iglesias | log_cpu_state(env, 0);
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221 | 4acb54ba | Edgar E. Iglesias | }
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222 | 4acb54ba | Edgar E. Iglesias | }
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223 | 4acb54ba | Edgar E. Iglesias | #endif
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224 | 4acb54ba | Edgar E. Iglesias | qemu_log_mask(CPU_LOG_INT, |
225 | 4acb54ba | Edgar E. Iglesias | "interrupt at pc=%x msr=%x %x iflags=%x\n",
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226 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); |
227 | 4acb54ba | Edgar E. Iglesias | |
228 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ |
229 | 4acb54ba | Edgar E. Iglesias | | MSR_UM | MSR_IE); |
230 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_MSR] |= t; |
231 | 4acb54ba | Edgar E. Iglesias | |
232 | 4acb54ba | Edgar E. Iglesias | env->regs[14] = env->sregs[SR_PC];
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233 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_PC] = 0x10;
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234 | 4acb54ba | Edgar E. Iglesias | //log_cpu_state_mask(CPU_LOG_INT, env, 0);
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235 | 4acb54ba | Edgar E. Iglesias | break;
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236 | 4acb54ba | Edgar E. Iglesias | |
237 | 4acb54ba | Edgar E. Iglesias | case EXCP_BREAK:
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238 | 4acb54ba | Edgar E. Iglesias | case EXCP_HW_BREAK:
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239 | 4acb54ba | Edgar E. Iglesias | assert(!(env->iflags & IMM_FLAG)); |
240 | 4acb54ba | Edgar E. Iglesias | assert(!(env->iflags & D_FLAG)); |
241 | 4acb54ba | Edgar E. Iglesias | t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
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242 | 4acb54ba | Edgar E. Iglesias | qemu_log_mask(CPU_LOG_INT, |
243 | 4acb54ba | Edgar E. Iglesias | "break at pc=%x msr=%x %x iflags=%x\n",
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244 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); |
245 | 4acb54ba | Edgar E. Iglesias | log_cpu_state_mask(CPU_LOG_INT, env, 0);
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246 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); |
247 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_MSR] |= t; |
248 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_MSR] |= MSR_BIP; |
249 | 4acb54ba | Edgar E. Iglesias | if (env->exception_index == EXCP_HW_BREAK) {
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250 | 4acb54ba | Edgar E. Iglesias | env->regs[16] = env->sregs[SR_PC];
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251 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_MSR] |= MSR_BIP; |
252 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_PC] = 0x18;
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253 | 4acb54ba | Edgar E. Iglesias | } else
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254 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_PC] = env->btarget; |
255 | 4acb54ba | Edgar E. Iglesias | break;
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256 | 4acb54ba | Edgar E. Iglesias | default:
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257 | 4acb54ba | Edgar E. Iglesias | cpu_abort(env, "unhandled exception type=%d\n",
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258 | 4acb54ba | Edgar E. Iglesias | env->exception_index); |
259 | 4acb54ba | Edgar E. Iglesias | break;
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260 | 4acb54ba | Edgar E. Iglesias | } |
261 | 4acb54ba | Edgar E. Iglesias | } |
262 | 4acb54ba | Edgar E. Iglesias | |
263 | c227f099 | Anthony Liguori | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
264 | 4acb54ba | Edgar E. Iglesias | { |
265 | 4acb54ba | Edgar E. Iglesias | target_ulong vaddr, paddr = 0;
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266 | 4acb54ba | Edgar E. Iglesias | struct microblaze_mmu_lookup lu;
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267 | 4acb54ba | Edgar E. Iglesias | unsigned int hit; |
268 | 4acb54ba | Edgar E. Iglesias | |
269 | 4acb54ba | Edgar E. Iglesias | if (env->sregs[SR_MSR] & MSR_VM) {
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270 | 4acb54ba | Edgar E. Iglesias | hit = mmu_translate(&env->mmu, &lu, addr, 0, 0); |
271 | 4acb54ba | Edgar E. Iglesias | if (hit) {
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272 | 4acb54ba | Edgar E. Iglesias | vaddr = addr & TARGET_PAGE_MASK; |
273 | 4acb54ba | Edgar E. Iglesias | paddr = lu.paddr + vaddr - lu.vaddr; |
274 | 4acb54ba | Edgar E. Iglesias | } else
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275 | 4acb54ba | Edgar E. Iglesias | paddr = 0; /* ???. */ |
276 | 4acb54ba | Edgar E. Iglesias | } else
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277 | 4acb54ba | Edgar E. Iglesias | paddr = addr & TARGET_PAGE_MASK; |
278 | 4acb54ba | Edgar E. Iglesias | |
279 | 4acb54ba | Edgar E. Iglesias | return paddr;
|
280 | 4acb54ba | Edgar E. Iglesias | } |
281 | 4acb54ba | Edgar E. Iglesias | #endif |