target-arm: convert gen_lookup_tb not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCG
The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16helpers used fixed registers to return values. This patch replaces that withTCG code, so T0/T1 is no longer directly used by the helper functions....
target-arm: fix TANDC and TORC instructions
Uninitialized register was used instead of proper TCG variable.
target-arm: replace thumb usage of cpu_T registers by proper register allocations
The goal is eventually to get rid of all cpu_T register usage and to usejust short-lived tmp/tmp2 registers. This patch converts all the places wherecpu_T was used in the Thumb code and replaces it with explicit TCG register...
target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_T
target-arm: convert disas_neon_data_insn and helpers not to use cpu_T
target-arm: convert disas_neon_ls_insn not to use cpu_T
target-arm: convert disas_dsp_insn not use cpu_T
target-arm: use tcg_global_mem_new_i32 to allocate registers
Currently each read/write of ARM register involves a LD/ST TCG operation. Thispatch uses TCG memory-backed registers to represent the ARM register set. Withmemory-backed registers the LD/ST operations are transparently generated by TCG...
target-arm: get rid of temporary variable cache
The temporary variable cache in no longer need since tcg_temp_free was introduced.
target-arm: remove useless line that sets register that is never used again
target-arm: remove unused gen_movl_T2_reg function
target-arm: fix SRS/RFE instructions
The encoding of 'IA' and 'DB' conditions was swapped.SRS instruction must store banked SPSR instead of CPSR at the specific address.Missing 'return' statement at the end of RFE handling.Fixed write-back code to reference correct registers....
target-arm: get rid of gen_set_psr_T0 and replace it by gen_set_psr/gen_set_psr_im
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with afew minor variations. This patch sets up appropriate defaults for ageneric handle_cpu_signal and provides overrides for particular targets...
Save/restore ARMv6 MMU state
Correctly save/restore ARMV6 MMU state.
Signed-off-by: Paul Brook <paul@codesourcery.com>
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Remove unused gen_bx_T0 function.
Signed-off-by: Filip Navara <filip.navara@gmail.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Convert machine registration to use module init functions
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
fix ARMv7 data processing instructions
ARMv7 defines a new behavior for ARM data processing instructionscompared to earlier architecture revisions; when the destinationregister is R15, a Branch and Exchange operation is executed ratherthan a simple Branch to the target address. This patch corrects the...
Modernize parts of target-arm/translate.c in preparation for themodifications in the subsequent patch in this patch set. This is donein order to avoid writing new code to target-arm/translate.c thatwould use deprecated methods and/or variables....
Syborg (Symbian Virtual Platform) board
A virtual reference platform for SymbianOS development/debugging.
Fixe ARM NEON vrshl.
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
qemu: per-arch cpu_has_work (Marcelo Tosatti)
Blue Swirl: fix Sparc32 breakage
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
target-arm: don't use T[x] in helper
(Torbjörn Andersson)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7034 c046a42c-6fe2-441c-8c8c-71466251a162
Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and addsthis feature to targets which did not have a compile time option.
Add monitor command to enable or disable single step mode.
Modify monitor command "info status" to display single step mode....
Fix ARM quadword VDUP (core register).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6857 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
Fix correct reset value for ARM CP15 c1 auxiliary control register
According to ARM Cortex A8 Technical Reference Manual, the reset value for CP15 c1 auxiliary controlregister is 2, not zero (page 3.12).
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
clean build: Fix arm build warnings
Fix remaining arm warnings - except for the mess in the NetWinder FPemulator.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6766 c046a42c-6fe2-441c-8c8c-71466251a162
The _exit syscall is used for both thread termination in NPTL applications,and process termination in legacy applications. Try to guess which we wantbased on the presence of multiple threads.
Also implement locking when modifying the CPU list.
Signed-off-by: Paul Brook <paul@codesourcery.com>...
Fix cpu_arm_handle_mmu_fault warning
This patch fixes:
/scratch/froydnj/qemu.git/target-arm/helper.c:451: warning: no previous prototype for 'cpu_arm_handle_mmu_fault'
by moving the declaration of the function to cpu.h from exec.h. cpu.hseems to be the place most other ports declare the corresponding...
targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added morearchs.
This patch introduces a flag to log CPU resets. Useful for tracingunexpected resets (such as those triggered by x86 triple faults).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Implement flush-to-zero mode (denormal results are replaced with zero).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6107 c046a42c-6fe2-441c-8c8c-71466251a162
Implement default-NaN mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6106 c046a42c-6fe2-441c-8c8c-71466251a162
Implement ARMv7 cp15 cache ID registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6105 c046a42c-6fe2-441c-8c8c-71466251a162
Implement (very) basic Thumb2-EE support. This doesn't actually implementEE state, just the associated system coprocessor registers. It is sufficientto keep OS setup and context switching code happy.
Fix VFP fixed point conversion routines.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6103 c046a42c-6fe2-441c-8c8c-71466251a162
Implement ARMv7 MMU access permissions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6099 c046a42c-6fe2-441c-8c8c-71466251a162
ARM: basic SX1-cellphone sysemu support (Jean-Christophe PLAGNIOL-VILLARD).
The TSC2102 chip is not included in documentation because a patch ispending.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6038 c046a42c-6fe2-441c-8c8c-71466251a162
Remove unnecessary trailing newlines
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
Remove FORCE_RET() and RETURN
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
ARM: fix smmul and smmla/smmls usage of registers (Mans Rullgard).
This fixes the destination and accumulator registers for the smmuland smmla instructions.
Signed-off-by: Mans Rullgard <mans@mansr.com>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
ARM: fix usad8 and usada8 usage of registers (Mans Rullgard).
This fixes the destination and accumulator registers for the usad8and usada8 instructions.
Signed-off-by: Mans Rullgard <mans@mansr.com>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>...
Patch holes in ARM translation (Laurent Desnogues).
- gen_set_CF_bit31: use the right value to set carry flag - shifter_out_im: remove a spurious semi-colon - add a break for VSHRN, VRSHRN, VQSHRN, VQRSHRN size 2 case - sbfx, ubfx are v6t2 instructions...
ARM: cosmetics (Laurent Desnogues).
- remove macros that are not used - remove disass structure is_mem field which value is never used - correct a typo in a comment.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>...
Common cpu_loop_exit prototype
All archs use the same cpu_loop_exit, so move the prototype in a commonheader. i386 was carrying a __hidden attribute, but that was empty forthis arch anyway.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying thecode and also fixing a use after release issue incpu_break/watchpoint_remove_all.
Remove premature memop TB terminations (Jan Kiszka)
Now that we can properly restore the pc on watchpoint hits, there is nomore need for prematurely terminating TBs if watchpoints are present.Remove all related bits.
Refactor and enhance break/watchpoint API (Jan Kiszka)
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow thesucceeding enhancements this series comes with.
First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switchingto dynamically allocated data structures that are kept in linked lists....
Refactor translation block CPU state handling (Jan Kiszka)
This patch refactors the way the CPU state is handled that is associatedwith a TB. The basic motivation is to move more arch specific code outof generic files. Specifically the long #ifdef clutter in tb_find_fast()...
Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
as macros should be avoided when possible.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
TCG variable type checking.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
VFP fnmsc negative zero fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5610 c046a42c-6fe2-441c-8c8c-71466251a162
Fix undeclared symbol warnings from sparse
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
Additional exclusive load/store instruction are v6K, not v6T2.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5518 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARMv6t2 strex instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5517 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARMv6 translation table base address calculation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5514 c046a42c-6fe2-441c-8c8c-71466251a162
Optimize redundant cp15 coprocessor access control register writes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5512 c046a42c-6fe2-441c-8c8c-71466251a162
Add GDB XML register description support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5459 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARM NEON vdup and vtbl bugs.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5286 c046a42c-6fe2-441c-8c8c-71466251a162
Fix neon encoding comment.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5285 c046a42c-6fe2-441c-8c8c-71466251a162
Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
Fix QADD / QSUB decoding on ARM (Torbjörn Andersson).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5273 c046a42c-6fe2-441c-8c8c-71466251a162
Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
ARMv6: fix SIMD add/sub carry flags (Vincent Palatin).
After a quick code review, it seems to be a bad cut-n-paste between16-bit and 8-bit UADD/USUB, indeed UADD8/USUB8 tries to set GE bits bypair instead of one at a time.Besides, the addition operations (UADD8/UADD16) set GE bits to "NOT...
ARM: fix CPS masks (Vincent Palatin).
According to ARM Reference Manual (DDI0100 A4.1.16),bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction maskshould be 0x0ff10020 not 0x0ff10010.Besides, mmod flag is bit 17 (b14 is SBZ)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4899 c046a42c-6fe2-441c-8c8c-71466251a162
Fix smlald, smlsld, pkhtp, pkhbt, ssat, usat, umul, smul... (Laurent Desnogues).
helper.c - copy reference c0_c2 to runtime c0_c2 and not c0_c1
op_helper.c - remove old code (PARAM1, probably some left over from old dyngen) that broke do_[us]sat
translate.c...
Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
Terminate TB immediately after v7-M exception return.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4868 c046a42c-6fe2-441c-8c8c-71466251a162
Convert remaining __builtin_expect to likely/unlikely, by Jan Kiszka.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4840 c046a42c-6fe2-441c-8c8c-71466251a162
Silence compiler warning.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4839 c046a42c-6fe2-441c-8c8c-71466251a162
ARMv7-M interrupt stack alignment fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4823 c046a42c-6fe2-441c-8c8c-71466251a162
Move interrupt_request and user_mode_only to common cpu state.Save and restore env->interrupt_request and env->halted.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
Spelling fixes, spotted by Stuart Brady.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4809 c046a42c-6fe2-441c-8c8c-71466251a162
Move CPU save/load registration to common code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
Suppress bogus compiler warnings.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4803 c046a42c-6fe2-441c-8c8c-71466251a162
Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
Mark a dead_tmp as such in ARM msr.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4648 c046a42c-6fe2-441c-8c8c-71466251a162
Provide basic emulation for Sharp SL-6000 PDA (Tosa), Dmitry Baryshkov.
This adds basic support for emulating Sharp Zaurus SL-6000 PDA (tosa).Currently it provides only basic support: no kbd/lcd, sound, ts, etc.But it's able at least to boot Linux from CF....
Fix typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
Move clone() register setup to target specific code. Handle fork-like clone.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
Push common interrupt variables to cpu-defs.h (Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
Implement ARM magic kernel page and TLS register.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4610 c046a42c-6fe2-441c-8c8c-71466251a162
moved halted field to CPU_COMMON
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
Fix off-by-one unwinding error.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARM conditional branch bug.Add tcg_gen_brcondi.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4552 c046a42c-6fe2-441c-8c8c-71466251a162
Add N810 to allowed -M values, add documentation part for N8x0.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4490 c046a42c-6fe2-441c-8c8c-71466251a162
Remove arm's local not_i32 tcg op now that there's one in tcg.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4475 c046a42c-6fe2-441c-8c8c-71466251a162
Add TCG native negation op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4426 c046a42c-6fe2-441c-8c8c-71466251a162
Add zero extension (pseudo-)ops.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4424 c046a42c-6fe2-441c-8c8c-71466251a162