root / hw / slavio_timer.c @ 3b4aa426
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1 | e80cfcfc | bellard | /*
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2 | e80cfcfc | bellard | * QEMU Sparc SLAVIO timer controller emulation
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3 | e80cfcfc | bellard | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | e80cfcfc | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | e80cfcfc | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | e80cfcfc | bellard | * in the Software without restriction, including without limitation the rights
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9 | e80cfcfc | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | e80cfcfc | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | e80cfcfc | bellard | * furnished to do so, subject to the following conditions:
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12 | e80cfcfc | bellard | *
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13 | e80cfcfc | bellard | * The above copyright notice and this permission notice shall be included in
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14 | e80cfcfc | bellard | * all copies or substantial portions of the Software.
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15 | e80cfcfc | bellard | *
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16 | e80cfcfc | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | e80cfcfc | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | e80cfcfc | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | e80cfcfc | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | e80cfcfc | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | e80cfcfc | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | e80cfcfc | bellard | * THE SOFTWARE.
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23 | e80cfcfc | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | e80cfcfc | bellard | |
28 | e80cfcfc | bellard | //#define DEBUG_TIMER
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29 | e80cfcfc | bellard | |
30 | 66321a11 | bellard | #ifdef DEBUG_TIMER
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31 | 66321a11 | bellard | #define DPRINTF(fmt, args...) \
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32 | 66321a11 | bellard | do { printf("TIMER: " fmt , ##args); } while (0) |
33 | 66321a11 | bellard | #else
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34 | 66321a11 | bellard | #define DPRINTF(fmt, args...)
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35 | 66321a11 | bellard | #endif
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36 | 66321a11 | bellard | |
37 | e80cfcfc | bellard | /*
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38 | e80cfcfc | bellard | * Registers of hardware timer in sun4m.
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39 | e80cfcfc | bellard | *
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40 | e80cfcfc | bellard | * This is the timer/counter part of chip STP2001 (Slave I/O), also
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41 | e80cfcfc | bellard | * produced as NCR89C105. See
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42 | e80cfcfc | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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43 | 5fafdf24 | ths | *
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44 | e80cfcfc | bellard | * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
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45 | e80cfcfc | bellard | * are zero. Bit 31 is 1 when count has been reached.
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46 | e80cfcfc | bellard | *
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47 | ba3c64fb | bellard | * Per-CPU timers interrupt local CPU, system timer uses normal
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48 | ba3c64fb | bellard | * interrupt routing.
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49 | ba3c64fb | bellard | *
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50 | e80cfcfc | bellard | */
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51 | e80cfcfc | bellard | |
52 | 81732d19 | blueswir1 | #define MAX_CPUS 16 |
53 | 81732d19 | blueswir1 | |
54 | e80cfcfc | bellard | typedef struct SLAVIO_TIMERState { |
55 | d7edfd27 | blueswir1 | qemu_irq irq; |
56 | 8d05ea8a | blueswir1 | ptimer_state *timer; |
57 | 8d05ea8a | blueswir1 | uint32_t count, counthigh, reached; |
58 | 8d05ea8a | blueswir1 | uint64_t limit; |
59 | 115646b6 | blueswir1 | // processor only
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60 | 115646b6 | blueswir1 | int running;
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61 | 115646b6 | blueswir1 | struct SLAVIO_TIMERState *master;
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62 | 115646b6 | blueswir1 | int slave_index;
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63 | 115646b6 | blueswir1 | // system only
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64 | 19f8e5dd | blueswir1 | unsigned int num_slaves; |
65 | 81732d19 | blueswir1 | struct SLAVIO_TIMERState *slave[MAX_CPUS];
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66 | 81732d19 | blueswir1 | uint32_t slave_mode; |
67 | e80cfcfc | bellard | } SLAVIO_TIMERState; |
68 | e80cfcfc | bellard | |
69 | e80cfcfc | bellard | #define TIMER_MAXADDR 0x1f |
70 | 115646b6 | blueswir1 | #define SYS_TIMER_SIZE 0x14 |
71 | 81732d19 | blueswir1 | #define CPU_TIMER_SIZE 0x10 |
72 | e80cfcfc | bellard | |
73 | d2c38b24 | blueswir1 | #define SYS_TIMER_OFFSET 0x10000ULL |
74 | d2c38b24 | blueswir1 | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
75 | d2c38b24 | blueswir1 | |
76 | d2c38b24 | blueswir1 | #define TIMER_LIMIT 0 |
77 | d2c38b24 | blueswir1 | #define TIMER_COUNTER 1 |
78 | d2c38b24 | blueswir1 | #define TIMER_COUNTER_NORST 2 |
79 | d2c38b24 | blueswir1 | #define TIMER_STATUS 3 |
80 | d2c38b24 | blueswir1 | #define TIMER_MODE 4 |
81 | d2c38b24 | blueswir1 | |
82 | d2c38b24 | blueswir1 | #define TIMER_COUNT_MASK32 0xfffffe00 |
83 | d2c38b24 | blueswir1 | #define TIMER_LIMIT_MASK32 0x7fffffff |
84 | d2c38b24 | blueswir1 | #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL |
85 | d2c38b24 | blueswir1 | #define TIMER_MAX_COUNT32 0x7ffffe00ULL |
86 | d2c38b24 | blueswir1 | #define TIMER_REACHED 0x80000000 |
87 | d2c38b24 | blueswir1 | #define TIMER_PERIOD 500ULL // 500ns |
88 | d2c38b24 | blueswir1 | #define LIMIT_TO_PERIODS(l) ((l) >> 9) |
89 | d2c38b24 | blueswir1 | #define PERIODS_TO_LIMIT(l) ((l) << 9) |
90 | d2c38b24 | blueswir1 | |
91 | 115646b6 | blueswir1 | static int slavio_timer_is_user(SLAVIO_TIMERState *s) |
92 | 115646b6 | blueswir1 | { |
93 | 115646b6 | blueswir1 | return s->master && (s->master->slave_mode & (1 << s->slave_index)); |
94 | 115646b6 | blueswir1 | } |
95 | 115646b6 | blueswir1 | |
96 | e80cfcfc | bellard | // Update count, set irq, update expire_time
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97 | 8d05ea8a | blueswir1 | // Convert from ptimer countdown units
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98 | e80cfcfc | bellard | static void slavio_timer_get_out(SLAVIO_TIMERState *s) |
99 | e80cfcfc | bellard | { |
100 | bd7e2875 | blueswir1 | uint64_t count, limit; |
101 | e80cfcfc | bellard | |
102 | bd7e2875 | blueswir1 | if (s->limit == 0) /* free-run processor or system counter */ |
103 | bd7e2875 | blueswir1 | limit = TIMER_MAX_COUNT32; |
104 | bd7e2875 | blueswir1 | else
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105 | bd7e2875 | blueswir1 | limit = s->limit; |
106 | bd7e2875 | blueswir1 | |
107 | bd7e2875 | blueswir1 | count = limit - PERIODS_TO_LIMIT(ptimer_get_count(s->timer)); |
108 | d2c38b24 | blueswir1 | DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, |
109 | d2c38b24 | blueswir1 | s->counthigh, s->count); |
110 | d2c38b24 | blueswir1 | s->count = count & TIMER_COUNT_MASK32; |
111 | 8d05ea8a | blueswir1 | s->counthigh = count >> 32;
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112 | e80cfcfc | bellard | } |
113 | e80cfcfc | bellard | |
114 | e80cfcfc | bellard | // timer callback
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115 | e80cfcfc | bellard | static void slavio_timer_irq(void *opaque) |
116 | e80cfcfc | bellard | { |
117 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
118 | e80cfcfc | bellard | |
119 | e80cfcfc | bellard | slavio_timer_get_out(s); |
120 | 8d05ea8a | blueswir1 | DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
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121 | 115646b6 | blueswir1 | if (!slavio_timer_is_user(s)) {
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122 | d2c38b24 | blueswir1 | s->reached = TIMER_REACHED; |
123 | f930d07e | blueswir1 | qemu_irq_raise(s->irq); |
124 | 115646b6 | blueswir1 | } |
125 | e80cfcfc | bellard | } |
126 | e80cfcfc | bellard | |
127 | e80cfcfc | bellard | static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
128 | e80cfcfc | bellard | { |
129 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
130 | 8d05ea8a | blueswir1 | uint32_t saddr, ret; |
131 | e80cfcfc | bellard | |
132 | e80cfcfc | bellard | saddr = (addr & TIMER_MAXADDR) >> 2;
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133 | e80cfcfc | bellard | switch (saddr) {
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134 | d2c38b24 | blueswir1 | case TIMER_LIMIT:
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135 | f930d07e | blueswir1 | // read limit (system counter mode) or read most signifying
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136 | f930d07e | blueswir1 | // part of counter (user mode)
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137 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
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138 | 115646b6 | blueswir1 | // read user timer MSW
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139 | 115646b6 | blueswir1 | slavio_timer_get_out(s); |
140 | 115646b6 | blueswir1 | ret = s->counthigh; |
141 | 115646b6 | blueswir1 | } else {
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142 | 115646b6 | blueswir1 | // read limit
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143 | f930d07e | blueswir1 | // clear irq
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144 | d7edfd27 | blueswir1 | qemu_irq_lower(s->irq); |
145 | f930d07e | blueswir1 | s->reached = 0;
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146 | d2c38b24 | blueswir1 | ret = s->limit & TIMER_LIMIT_MASK32; |
147 | f930d07e | blueswir1 | } |
148 | 8d05ea8a | blueswir1 | break;
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149 | d2c38b24 | blueswir1 | case TIMER_COUNTER:
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150 | f930d07e | blueswir1 | // read counter and reached bit (system mode) or read lsbits
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151 | f930d07e | blueswir1 | // of counter (user mode)
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152 | f930d07e | blueswir1 | slavio_timer_get_out(s); |
153 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) // read user timer LSW |
154 | d2c38b24 | blueswir1 | ret = s->count & TIMER_COUNT_MASK32; |
155 | 115646b6 | blueswir1 | else // read limit |
156 | d2c38b24 | blueswir1 | ret = (s->count & TIMER_MAX_COUNT32) | s->reached; |
157 | 8d05ea8a | blueswir1 | break;
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158 | d2c38b24 | blueswir1 | case TIMER_STATUS:
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159 | 115646b6 | blueswir1 | // only available in processor counter/timer
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160 | f930d07e | blueswir1 | // read start/stop status
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161 | 115646b6 | blueswir1 | ret = s->running; |
162 | 8d05ea8a | blueswir1 | break;
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163 | d2c38b24 | blueswir1 | case TIMER_MODE:
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164 | 115646b6 | blueswir1 | // only available in system counter
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165 | f930d07e | blueswir1 | // read user/system mode
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166 | 81732d19 | blueswir1 | ret = s->slave_mode; |
167 | 8d05ea8a | blueswir1 | break;
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168 | e80cfcfc | bellard | default:
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169 | 115646b6 | blueswir1 | DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr); |
170 | 8d05ea8a | blueswir1 | ret = 0;
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171 | 8d05ea8a | blueswir1 | break;
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172 | e80cfcfc | bellard | } |
173 | 8d05ea8a | blueswir1 | DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret); |
174 | 8d05ea8a | blueswir1 | |
175 | 8d05ea8a | blueswir1 | return ret;
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176 | e80cfcfc | bellard | } |
177 | e80cfcfc | bellard | |
178 | d2c38b24 | blueswir1 | static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, |
179 | d2c38b24 | blueswir1 | uint32_t val) |
180 | e80cfcfc | bellard | { |
181 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
182 | e80cfcfc | bellard | uint32_t saddr; |
183 | e80cfcfc | bellard | |
184 | 8d05ea8a | blueswir1 | DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val); |
185 | e80cfcfc | bellard | saddr = (addr & TIMER_MAXADDR) >> 2;
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186 | e80cfcfc | bellard | switch (saddr) {
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187 | d2c38b24 | blueswir1 | case TIMER_LIMIT:
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188 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
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189 | 115646b6 | blueswir1 | // set user counter MSW, reset counter
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190 | 81732d19 | blueswir1 | qemu_irq_lower(s->irq); |
191 | d2c38b24 | blueswir1 | s->limit = TIMER_MAX_COUNT64; |
192 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer reset\n", s->slave_index);
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193 | d2c38b24 | blueswir1 | ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
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194 | 115646b6 | blueswir1 | } else {
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195 | 115646b6 | blueswir1 | // set limit, reset counter
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196 | 115646b6 | blueswir1 | qemu_irq_lower(s->irq); |
197 | d2c38b24 | blueswir1 | s->limit = val & TIMER_MAX_COUNT32; |
198 | 6240d646 | blueswir1 | if (s->limit == 0) /* free-run */ |
199 | 6240d646 | blueswir1 | ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
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200 | 6240d646 | blueswir1 | else
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201 | 6240d646 | blueswir1 | ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
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202 | 81732d19 | blueswir1 | } |
203 | 115646b6 | blueswir1 | break;
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204 | d2c38b24 | blueswir1 | case TIMER_COUNTER:
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205 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
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206 | 115646b6 | blueswir1 | // set user counter LSW, reset counter
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207 | 115646b6 | blueswir1 | qemu_irq_lower(s->irq); |
208 | d2c38b24 | blueswir1 | s->limit = TIMER_MAX_COUNT64; |
209 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer reset\n", s->slave_index);
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210 | d2c38b24 | blueswir1 | ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
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211 | 115646b6 | blueswir1 | } else
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212 | 115646b6 | blueswir1 | DPRINTF("not user timer\n");
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213 | 115646b6 | blueswir1 | break;
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214 | d2c38b24 | blueswir1 | case TIMER_COUNTER_NORST:
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215 | f930d07e | blueswir1 | // set limit without resetting counter
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216 | d2c38b24 | blueswir1 | s->limit = val & TIMER_MAX_COUNT32; |
217 | 6240d646 | blueswir1 | if (s->limit == 0) /* free-run */ |
218 | 6240d646 | blueswir1 | ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
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219 | 6240d646 | blueswir1 | else
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220 | 6240d646 | blueswir1 | ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 0);
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221 | f930d07e | blueswir1 | break;
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222 | d2c38b24 | blueswir1 | case TIMER_STATUS:
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223 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
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224 | 115646b6 | blueswir1 | // start/stop user counter
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225 | 115646b6 | blueswir1 | if ((val & 1) && !s->running) { |
226 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer started\n", s->slave_index);
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227 | 8d05ea8a | blueswir1 | ptimer_run(s->timer, 0);
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228 | 115646b6 | blueswir1 | s->running = 1;
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229 | 115646b6 | blueswir1 | } else if (!(val & 1) && s->running) { |
230 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer stopped\n", s->slave_index);
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231 | 115646b6 | blueswir1 | ptimer_stop(s->timer); |
232 | 115646b6 | blueswir1 | s->running = 0;
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233 | f930d07e | blueswir1 | } |
234 | f930d07e | blueswir1 | } |
235 | f930d07e | blueswir1 | break;
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236 | d2c38b24 | blueswir1 | case TIMER_MODE:
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237 | 115646b6 | blueswir1 | if (s->master == NULL) { |
238 | 81732d19 | blueswir1 | unsigned int i; |
239 | 81732d19 | blueswir1 | |
240 | 19f8e5dd | blueswir1 | for (i = 0; i < s->num_slaves; i++) { |
241 | 81732d19 | blueswir1 | if (val & (1 << i)) { |
242 | 81732d19 | blueswir1 | qemu_irq_lower(s->slave[i]->irq); |
243 | 81732d19 | blueswir1 | s->slave[i]->limit = -1ULL;
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244 | 81732d19 | blueswir1 | } |
245 | 115646b6 | blueswir1 | if ((val & (1 << i)) != (s->slave_mode & (1 << i))) { |
246 | 115646b6 | blueswir1 | ptimer_stop(s->slave[i]->timer); |
247 | d2c38b24 | blueswir1 | ptimer_set_limit(s->slave[i]->timer, |
248 | d2c38b24 | blueswir1 | LIMIT_TO_PERIODS(s->slave[i]->limit), 1);
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249 | d2c38b24 | blueswir1 | DPRINTF("processor %d timer changed\n",
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250 | d2c38b24 | blueswir1 | s->slave[i]->slave_index); |
251 | 115646b6 | blueswir1 | ptimer_run(s->slave[i]->timer, 0);
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252 | 115646b6 | blueswir1 | } |
253 | 81732d19 | blueswir1 | } |
254 | 19f8e5dd | blueswir1 | s->slave_mode = val & ((1 << s->num_slaves) - 1); |
255 | 115646b6 | blueswir1 | } else
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256 | 115646b6 | blueswir1 | DPRINTF("not system timer\n");
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257 | f930d07e | blueswir1 | break;
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258 | e80cfcfc | bellard | default:
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259 | 115646b6 | blueswir1 | DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr); |
260 | f930d07e | blueswir1 | break;
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261 | e80cfcfc | bellard | } |
262 | e80cfcfc | bellard | } |
263 | e80cfcfc | bellard | |
264 | e80cfcfc | bellard | static CPUReadMemoryFunc *slavio_timer_mem_read[3] = { |
265 | e80cfcfc | bellard | slavio_timer_mem_readl, |
266 | e80cfcfc | bellard | slavio_timer_mem_readl, |
267 | e80cfcfc | bellard | slavio_timer_mem_readl, |
268 | e80cfcfc | bellard | }; |
269 | e80cfcfc | bellard | |
270 | e80cfcfc | bellard | static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = { |
271 | e80cfcfc | bellard | slavio_timer_mem_writel, |
272 | e80cfcfc | bellard | slavio_timer_mem_writel, |
273 | e80cfcfc | bellard | slavio_timer_mem_writel, |
274 | e80cfcfc | bellard | }; |
275 | e80cfcfc | bellard | |
276 | e80cfcfc | bellard | static void slavio_timer_save(QEMUFile *f, void *opaque) |
277 | e80cfcfc | bellard | { |
278 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
279 | e80cfcfc | bellard | |
280 | 8d05ea8a | blueswir1 | qemu_put_be64s(f, &s->limit); |
281 | e80cfcfc | bellard | qemu_put_be32s(f, &s->count); |
282 | e80cfcfc | bellard | qemu_put_be32s(f, &s->counthigh); |
283 | d7edfd27 | blueswir1 | qemu_put_be32(f, 0); // Was irq |
284 | e80cfcfc | bellard | qemu_put_be32s(f, &s->reached); |
285 | 115646b6 | blueswir1 | qemu_put_be32s(f, &s->running); |
286 | 115646b6 | blueswir1 | qemu_put_be32s(f, 0); // Was mode |
287 | 8d05ea8a | blueswir1 | qemu_put_ptimer(f, s->timer); |
288 | e80cfcfc | bellard | } |
289 | e80cfcfc | bellard | |
290 | e80cfcfc | bellard | static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id) |
291 | e80cfcfc | bellard | { |
292 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
293 | d7edfd27 | blueswir1 | uint32_t tmp; |
294 | 3b46e624 | ths | |
295 | 8d05ea8a | blueswir1 | if (version_id != 2) |
296 | e80cfcfc | bellard | return -EINVAL;
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297 | e80cfcfc | bellard | |
298 | 8d05ea8a | blueswir1 | qemu_get_be64s(f, &s->limit); |
299 | e80cfcfc | bellard | qemu_get_be32s(f, &s->count); |
300 | e80cfcfc | bellard | qemu_get_be32s(f, &s->counthigh); |
301 | d7edfd27 | blueswir1 | qemu_get_be32s(f, &tmp); // Was irq
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302 | e80cfcfc | bellard | qemu_get_be32s(f, &s->reached); |
303 | 115646b6 | blueswir1 | qemu_get_be32s(f, &s->running); |
304 | 115646b6 | blueswir1 | qemu_get_be32s(f, &tmp); // Was mode
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305 | 8d05ea8a | blueswir1 | qemu_get_ptimer(f, s->timer); |
306 | 8d05ea8a | blueswir1 | |
307 | e80cfcfc | bellard | return 0; |
308 | e80cfcfc | bellard | } |
309 | e80cfcfc | bellard | |
310 | e80cfcfc | bellard | static void slavio_timer_reset(void *opaque) |
311 | e80cfcfc | bellard | { |
312 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
313 | e80cfcfc | bellard | |
314 | 3b4aa426 | blueswir1 | s->limit = 0;
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315 | e80cfcfc | bellard | s->count = 0;
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316 | e80cfcfc | bellard | s->reached = 0;
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317 | 3b4aa426 | blueswir1 | s->slave_mode = 0;
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318 | 3b4aa426 | blueswir1 | ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
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319 | 8d05ea8a | blueswir1 | ptimer_run(s->timer, 0);
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320 | 115646b6 | blueswir1 | s->running = 1;
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321 | d7edfd27 | blueswir1 | qemu_irq_lower(s->irq); |
322 | e80cfcfc | bellard | } |
323 | e80cfcfc | bellard | |
324 | 81732d19 | blueswir1 | static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
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325 | 115646b6 | blueswir1 | qemu_irq irq, |
326 | 115646b6 | blueswir1 | SLAVIO_TIMERState *master, |
327 | 115646b6 | blueswir1 | int slave_index)
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328 | e80cfcfc | bellard | { |
329 | e80cfcfc | bellard | int slavio_timer_io_memory;
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330 | e80cfcfc | bellard | SLAVIO_TIMERState *s; |
331 | 8d05ea8a | blueswir1 | QEMUBH *bh; |
332 | e80cfcfc | bellard | |
333 | e80cfcfc | bellard | s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
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334 | e80cfcfc | bellard | if (!s)
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335 | 81732d19 | blueswir1 | return s;
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336 | e80cfcfc | bellard | s->irq = irq; |
337 | 115646b6 | blueswir1 | s->master = master; |
338 | 115646b6 | blueswir1 | s->slave_index = slave_index; |
339 | 8d05ea8a | blueswir1 | bh = qemu_bh_new(slavio_timer_irq, s); |
340 | 8d05ea8a | blueswir1 | s->timer = ptimer_init(bh); |
341 | d2c38b24 | blueswir1 | ptimer_set_period(s->timer, TIMER_PERIOD); |
342 | e80cfcfc | bellard | |
343 | e80cfcfc | bellard | slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
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344 | f930d07e | blueswir1 | slavio_timer_mem_write, s); |
345 | 115646b6 | blueswir1 | if (master)
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346 | d2c38b24 | blueswir1 | cpu_register_physical_memory(addr, CPU_TIMER_SIZE, |
347 | d2c38b24 | blueswir1 | slavio_timer_io_memory); |
348 | 81732d19 | blueswir1 | else
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349 | d2c38b24 | blueswir1 | cpu_register_physical_memory(addr, SYS_TIMER_SIZE, |
350 | d2c38b24 | blueswir1 | slavio_timer_io_memory); |
351 | d2c38b24 | blueswir1 | register_savevm("slavio_timer", addr, 2, slavio_timer_save, |
352 | d2c38b24 | blueswir1 | slavio_timer_load, s); |
353 | e80cfcfc | bellard | qemu_register_reset(slavio_timer_reset, s); |
354 | e80cfcfc | bellard | slavio_timer_reset(s); |
355 | 81732d19 | blueswir1 | |
356 | 81732d19 | blueswir1 | return s;
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357 | 81732d19 | blueswir1 | } |
358 | 81732d19 | blueswir1 | |
359 | 81732d19 | blueswir1 | void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
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360 | 19f8e5dd | blueswir1 | qemu_irq *cpu_irqs, unsigned int num_cpus) |
361 | 81732d19 | blueswir1 | { |
362 | 81732d19 | blueswir1 | SLAVIO_TIMERState *master; |
363 | 81732d19 | blueswir1 | unsigned int i; |
364 | 81732d19 | blueswir1 | |
365 | d2c38b24 | blueswir1 | master = slavio_timer_init(base + SYS_TIMER_OFFSET, master_irq, NULL, 0); |
366 | 81732d19 | blueswir1 | |
367 | 19f8e5dd | blueswir1 | master->num_slaves = num_cpus; |
368 | 19f8e5dd | blueswir1 | |
369 | 81732d19 | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
370 | 81732d19 | blueswir1 | master->slave[i] = slavio_timer_init(base + (target_phys_addr_t) |
371 | d2c38b24 | blueswir1 | CPU_TIMER_OFFSET(i), |
372 | 115646b6 | blueswir1 | cpu_irqs[i], master, i); |
373 | 81732d19 | blueswir1 | } |
374 | e80cfcfc | bellard | } |