root / hw / timer / tusb6010.c @ 3bd88451
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1 | 942ac052 | balrog | /*
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2 | 942ac052 | balrog | * Texas Instruments TUSB6010 emulation.
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3 | 942ac052 | balrog | * Based on reverse-engineering of a linux driver.
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4 | 942ac052 | balrog | *
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5 | 942ac052 | balrog | * Copyright (C) 2008 Nokia Corporation
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6 | 942ac052 | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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7 | 942ac052 | balrog | *
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8 | 942ac052 | balrog | * This program is free software; you can redistribute it and/or
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9 | 942ac052 | balrog | * modify it under the terms of the GNU General Public License as
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10 | 942ac052 | balrog | * published by the Free Software Foundation; either version 2 or
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11 | 942ac052 | balrog | * (at your option) version 3 of the License.
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12 | 942ac052 | balrog | *
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13 | 942ac052 | balrog | * This program is distributed in the hope that it will be useful,
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14 | 942ac052 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 | 942ac052 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 | 942ac052 | balrog | * GNU General Public License for more details.
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17 | 942ac052 | balrog | *
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18 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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19 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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20 | 942ac052 | balrog | */
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21 | 942ac052 | balrog | #include "qemu-common.h" |
22 | 1de7afc9 | Paolo Bonzini | #include "qemu/timer.h" |
23 | 83c9f4ca | Paolo Bonzini | #include "hw/usb.h" |
24 | 0d09e41a | Paolo Bonzini | #include "hw/arm/omap.h" |
25 | 83c9f4ca | Paolo Bonzini | #include "hw/irq.h" |
26 | 0d09e41a | Paolo Bonzini | #include "hw/arm/devices.h" |
27 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
28 | 942ac052 | balrog | |
29 | bdc76462 | Peter Maydell | typedef struct TUSBState { |
30 | bdc76462 | Peter Maydell | SysBusDevice busdev; |
31 | 64066a8f | Avi Kivity | MemoryRegion iomem[2];
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32 | 942ac052 | balrog | qemu_irq irq; |
33 | bc24a225 | Paul Brook | MUSBState *musb; |
34 | 942ac052 | balrog | QEMUTimer *otg_timer; |
35 | 942ac052 | balrog | QEMUTimer *pwr_timer; |
36 | 942ac052 | balrog | |
37 | 942ac052 | balrog | int power;
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38 | 942ac052 | balrog | uint32_t scratch; |
39 | 942ac052 | balrog | uint16_t test_reset; |
40 | 942ac052 | balrog | uint32_t prcm_config; |
41 | 942ac052 | balrog | uint32_t prcm_mngmt; |
42 | 942ac052 | balrog | uint16_t otg_status; |
43 | 942ac052 | balrog | uint32_t dev_config; |
44 | 942ac052 | balrog | int host_mode;
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45 | 942ac052 | balrog | uint32_t intr; |
46 | 942ac052 | balrog | uint32_t intr_ok; |
47 | 942ac052 | balrog | uint32_t mask; |
48 | 942ac052 | balrog | uint32_t usbip_intr; |
49 | 942ac052 | balrog | uint32_t usbip_mask; |
50 | 942ac052 | balrog | uint32_t gpio_intr; |
51 | 942ac052 | balrog | uint32_t gpio_mask; |
52 | 942ac052 | balrog | uint32_t gpio_config; |
53 | 942ac052 | balrog | uint32_t dma_intr; |
54 | 942ac052 | balrog | uint32_t dma_mask; |
55 | 942ac052 | balrog | uint32_t dma_map; |
56 | 942ac052 | balrog | uint32_t dma_config; |
57 | 942ac052 | balrog | uint32_t ep0_config; |
58 | 942ac052 | balrog | uint32_t rx_config[15];
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59 | 942ac052 | balrog | uint32_t tx_config[15];
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60 | 942ac052 | balrog | uint32_t wkup_mask; |
61 | 942ac052 | balrog | uint32_t pullup[2];
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62 | 942ac052 | balrog | uint32_t control_config; |
63 | 942ac052 | balrog | uint32_t otg_timer_val; |
64 | bdc76462 | Peter Maydell | } TUSBState; |
65 | 942ac052 | balrog | |
66 | 942ac052 | balrog | #define TUSB_DEVCLOCK 60000000 /* 60 MHz */ |
67 | 942ac052 | balrog | |
68 | 942ac052 | balrog | #define TUSB_VLYNQ_CTRL 0x004 |
69 | 942ac052 | balrog | |
70 | 942ac052 | balrog | /* Mentor Graphics OTG core registers. */
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71 | 942ac052 | balrog | #define TUSB_BASE_OFFSET 0x400 |
72 | 942ac052 | balrog | |
73 | 942ac052 | balrog | /* FIFO registers, 32-bit. */
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74 | 942ac052 | balrog | #define TUSB_FIFO_BASE 0x600 |
75 | 942ac052 | balrog | |
76 | 942ac052 | balrog | /* Device System & Control registers, 32-bit. */
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77 | 942ac052 | balrog | #define TUSB_SYS_REG_BASE 0x800 |
78 | 942ac052 | balrog | |
79 | 942ac052 | balrog | #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000) |
80 | 942ac052 | balrog | #define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16) |
81 | 942ac052 | balrog | #define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15) |
82 | 942ac052 | balrog | #define TUSB_DEV_CONF_SOFT_ID (1 << 1) |
83 | 942ac052 | balrog | #define TUSB_DEV_CONF_ID_SEL (1 << 0) |
84 | 942ac052 | balrog | |
85 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004) |
86 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008) |
87 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24) |
88 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_O_ID_PULLUP (1 << 23) |
89 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19) |
90 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18) |
91 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17) |
92 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16) |
93 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15) |
94 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14) |
95 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13) |
96 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12) |
97 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11) |
98 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10) |
99 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9) |
100 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7) |
101 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_PD (1 << 6) |
102 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5) |
103 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4) |
104 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3) |
105 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_RESET (1 << 2) |
106 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1) |
107 | 942ac052 | balrog | #define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0) |
108 | 942ac052 | balrog | |
109 | 942ac052 | balrog | /* OTG status register */
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110 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c) |
111 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8) |
112 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_SESS_END (1 << 7) |
113 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6) |
114 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5) |
115 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4) |
116 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3) |
117 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2) |
118 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0) |
119 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1) |
120 | 942ac052 | balrog | #define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0) |
121 | 942ac052 | balrog | |
122 | 942ac052 | balrog | #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010) |
123 | 942ac052 | balrog | #define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31) |
124 | 942ac052 | balrog | #define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) |
125 | 942ac052 | balrog | #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014) |
126 | 942ac052 | balrog | |
127 | 942ac052 | balrog | /* PRCM configuration register */
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128 | 942ac052 | balrog | #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018) |
129 | 942ac052 | balrog | #define TUSB_PRCM_CONF_SFW_CPEN (1 << 24) |
130 | 942ac052 | balrog | #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) |
131 | 942ac052 | balrog | |
132 | 942ac052 | balrog | /* PRCM management register */
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133 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c) |
134 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v) (((v) & 0xf) << 25) |
135 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24) |
136 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20) |
137 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19) |
138 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18) |
139 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17) |
140 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10) |
141 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9) |
142 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8) |
143 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4) |
144 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3) |
145 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2) |
146 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1) |
147 | 942ac052 | balrog | #define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0) |
148 | 942ac052 | balrog | |
149 | 942ac052 | balrog | /* Wake-up source clear and mask registers */
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150 | 942ac052 | balrog | #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020) |
151 | 942ac052 | balrog | #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028) |
152 | 942ac052 | balrog | #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c) |
153 | 942ac052 | balrog | #define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13) |
154 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_7 (1 << 12) |
155 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_6 (1 << 11) |
156 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_5 (1 << 10) |
157 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_4 (1 << 9) |
158 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_3 (1 << 8) |
159 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_2 (1 << 7) |
160 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_1 (1 << 6) |
161 | 942ac052 | balrog | #define TUSB_PRCM_WGPIO_0 (1 << 5) |
162 | 942ac052 | balrog | #define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */ |
163 | 942ac052 | balrog | #define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */ |
164 | 942ac052 | balrog | #define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */ |
165 | 942ac052 | balrog | #define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */ |
166 | 942ac052 | balrog | #define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */ |
167 | 942ac052 | balrog | |
168 | 942ac052 | balrog | #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030) |
169 | 942ac052 | balrog | #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034) |
170 | 942ac052 | balrog | #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038) |
171 | 942ac052 | balrog | #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c) |
172 | 942ac052 | balrog | #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040) |
173 | 942ac052 | balrog | #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044) |
174 | 942ac052 | balrog | #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048) |
175 | 942ac052 | balrog | #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c) |
176 | 942ac052 | balrog | #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050) |
177 | 942ac052 | balrog | #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054) |
178 | 942ac052 | balrog | #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058) |
179 | 942ac052 | balrog | #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c) |
180 | 942ac052 | balrog | #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060) |
181 | 942ac052 | balrog | #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064) |
182 | 942ac052 | balrog | #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068) |
183 | 942ac052 | balrog | #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c) |
184 | 942ac052 | balrog | |
185 | 942ac052 | balrog | /* NOR flash interrupt source registers */
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186 | 942ac052 | balrog | #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070) |
187 | 942ac052 | balrog | #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074) |
188 | 942ac052 | balrog | #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078) |
189 | 942ac052 | balrog | #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c) |
190 | 942ac052 | balrog | #define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24) |
191 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_CORE (1 << 17) |
192 | 942ac052 | balrog | #define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16) |
193 | 942ac052 | balrog | #define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15) |
194 | 942ac052 | balrog | #define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14) |
195 | 942ac052 | balrog | #define TUSB_INT_SRC_DEV_WAKEUP (1 << 13) |
196 | 942ac052 | balrog | #define TUSB_INT_SRC_DEV_READY (1 << 12) |
197 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_TX (1 << 9) |
198 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_RX (1 << 8) |
199 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7) |
200 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6) |
201 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_DISCON (1 << 5) |
202 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_CONN (1 << 4) |
203 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_SOF (1 << 3) |
204 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2) |
205 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_RESUME (1 << 1) |
206 | 942ac052 | balrog | #define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0) |
207 | 942ac052 | balrog | |
208 | 942ac052 | balrog | #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080) |
209 | 942ac052 | balrog | #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084) |
210 | 942ac052 | balrog | #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100) |
211 | 942ac052 | balrog | #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104) |
212 | 942ac052 | balrog | #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108) |
213 | 942ac052 | balrog | #define TUSB_EP_IN_SIZE (TUSB_SYS_REG_BASE + 0x10c) |
214 | 942ac052 | balrog | #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148) |
215 | 942ac052 | balrog | #define TUSB_EP_OUT_SIZE (TUSB_SYS_REG_BASE + 0x14c) |
216 | 942ac052 | balrog | #define TUSB_EP_MAX_PACKET_SIZE_OFFSET (TUSB_SYS_REG_BASE + 0x188) |
217 | 942ac052 | balrog | #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4) |
218 | 942ac052 | balrog | #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8) |
219 | 942ac052 | balrog | #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8) |
220 | 942ac052 | balrog | |
221 | 942ac052 | balrog | #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8) |
222 | 942ac052 | balrog | #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc) |
223 | 942ac052 | balrog | |
224 | 942ac052 | balrog | /* Device System & Control register bitfields */
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225 | 942ac052 | balrog | #define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18) |
226 | 942ac052 | balrog | #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17) |
227 | 942ac052 | balrog | #define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16) |
228 | 942ac052 | balrog | #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24) |
229 | 942ac052 | balrog | #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26) |
230 | 942ac052 | balrog | #define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v) (((v) & 0x3f) << 20) |
231 | 942ac052 | balrog | #define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16) |
232 | 942ac052 | balrog | #define TUSB_EP0_CONFIG_SW_EN (1 << 8) |
233 | 942ac052 | balrog | #define TUSB_EP0_CONFIG_DIR_TX (1 << 7) |
234 | 942ac052 | balrog | #define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f) |
235 | 942ac052 | balrog | #define TUSB_EP_CONFIG_SW_EN (1 << 31) |
236 | 942ac052 | balrog | #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) |
237 | 942ac052 | balrog | #define TUSB_PROD_TEST_RESET_VAL 0xa596 |
238 | 942ac052 | balrog | |
239 | bc24a225 | Paul Brook | static void tusb_intr_update(TUSBState *s) |
240 | 942ac052 | balrog | { |
241 | 942ac052 | balrog | if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
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242 | 942ac052 | balrog | qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok); |
243 | 942ac052 | balrog | else
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244 | 942ac052 | balrog | qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok); |
245 | 942ac052 | balrog | } |
246 | 942ac052 | balrog | |
247 | bc24a225 | Paul Brook | static void tusb_usbip_intr_update(TUSBState *s) |
248 | 942ac052 | balrog | { |
249 | 942ac052 | balrog | /* TX interrupt in the MUSB */
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250 | 942ac052 | balrog | if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask) |
251 | 942ac052 | balrog | s->intr |= TUSB_INT_SRC_USB_IP_TX; |
252 | 942ac052 | balrog | else
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253 | 942ac052 | balrog | s->intr &= ~TUSB_INT_SRC_USB_IP_TX; |
254 | 942ac052 | balrog | |
255 | 942ac052 | balrog | /* RX interrupt in the MUSB */
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256 | 942ac052 | balrog | if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask) |
257 | 942ac052 | balrog | s->intr |= TUSB_INT_SRC_USB_IP_RX; |
258 | 942ac052 | balrog | else
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259 | 942ac052 | balrog | s->intr &= ~TUSB_INT_SRC_USB_IP_RX; |
260 | 942ac052 | balrog | |
261 | 942ac052 | balrog | /* XXX: What about TUSB_INT_SRC_USB_IP_CORE? */
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262 | 942ac052 | balrog | |
263 | 942ac052 | balrog | tusb_intr_update(s); |
264 | 942ac052 | balrog | } |
265 | 942ac052 | balrog | |
266 | bc24a225 | Paul Brook | static void tusb_dma_intr_update(TUSBState *s) |
267 | 942ac052 | balrog | { |
268 | 942ac052 | balrog | if (s->dma_intr & ~s->dma_mask)
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269 | 942ac052 | balrog | s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE; |
270 | 942ac052 | balrog | else
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271 | 942ac052 | balrog | s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE; |
272 | 942ac052 | balrog | |
273 | 942ac052 | balrog | tusb_intr_update(s); |
274 | 942ac052 | balrog | } |
275 | 942ac052 | balrog | |
276 | bc24a225 | Paul Brook | static void tusb_gpio_intr_update(TUSBState *s) |
277 | 942ac052 | balrog | { |
278 | 942ac052 | balrog | /* TODO: How is this signalled? */
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279 | 942ac052 | balrog | } |
280 | 942ac052 | balrog | |
281 | d60efc6b | Blue Swirl | extern CPUReadMemoryFunc * const musb_read[]; |
282 | d60efc6b | Blue Swirl | extern CPUWriteMemoryFunc * const musb_write[]; |
283 | 942ac052 | balrog | |
284 | a8170e5e | Avi Kivity | static uint32_t tusb_async_readb(void *opaque, hwaddr addr) |
285 | 942ac052 | balrog | { |
286 | bc24a225 | Paul Brook | TUSBState *s = (TUSBState *) opaque; |
287 | 942ac052 | balrog | |
288 | 942ac052 | balrog | switch (addr & 0xfff) { |
289 | 942ac052 | balrog | case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
290 | 942ac052 | balrog | return musb_read[0](s->musb, addr & 0x1ff); |
291 | 942ac052 | balrog | |
292 | 942ac052 | balrog | case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
293 | 942ac052 | balrog | return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
294 | 942ac052 | balrog | } |
295 | 942ac052 | balrog | |
296 | 942ac052 | balrog | printf("%s: unknown register at %03x\n",
|
297 | 942ac052 | balrog | __FUNCTION__, (int) (addr & 0xfff)); |
298 | 942ac052 | balrog | return 0; |
299 | 942ac052 | balrog | } |
300 | 942ac052 | balrog | |
301 | a8170e5e | Avi Kivity | static uint32_t tusb_async_readh(void *opaque, hwaddr addr) |
302 | 942ac052 | balrog | { |
303 | bc24a225 | Paul Brook | TUSBState *s = (TUSBState *) opaque; |
304 | 942ac052 | balrog | |
305 | 942ac052 | balrog | switch (addr & 0xfff) { |
306 | 942ac052 | balrog | case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
307 | 942ac052 | balrog | return musb_read[1](s->musb, addr & 0x1ff); |
308 | 942ac052 | balrog | |
309 | 942ac052 | balrog | case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
310 | 942ac052 | balrog | return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
311 | 942ac052 | balrog | } |
312 | 942ac052 | balrog | |
313 | 942ac052 | balrog | printf("%s: unknown register at %03x\n",
|
314 | 942ac052 | balrog | __FUNCTION__, (int) (addr & 0xfff)); |
315 | 942ac052 | balrog | return 0; |
316 | 942ac052 | balrog | } |
317 | 942ac052 | balrog | |
318 | a8170e5e | Avi Kivity | static uint32_t tusb_async_readw(void *opaque, hwaddr addr) |
319 | 942ac052 | balrog | { |
320 | bc24a225 | Paul Brook | TUSBState *s = (TUSBState *) opaque; |
321 | 942ac052 | balrog | int offset = addr & 0xfff; |
322 | 942ac052 | balrog | int epnum;
|
323 | 942ac052 | balrog | uint32_t ret; |
324 | 942ac052 | balrog | |
325 | 942ac052 | balrog | switch (offset) {
|
326 | 942ac052 | balrog | case TUSB_DEV_CONF:
|
327 | 942ac052 | balrog | return s->dev_config;
|
328 | 942ac052 | balrog | |
329 | 942ac052 | balrog | case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
330 | 942ac052 | balrog | return musb_read[2](s->musb, offset & 0x1ff); |
331 | 942ac052 | balrog | |
332 | 942ac052 | balrog | case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
333 | 942ac052 | balrog | return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
334 | 942ac052 | balrog | |
335 | 942ac052 | balrog | case TUSB_PHY_OTG_CTRL_ENABLE:
|
336 | 942ac052 | balrog | case TUSB_PHY_OTG_CTRL:
|
337 | 942ac052 | balrog | return 0x00; /* TODO */ |
338 | 942ac052 | balrog | |
339 | 942ac052 | balrog | case TUSB_DEV_OTG_STAT:
|
340 | 942ac052 | balrog | ret = s->otg_status; |
341 | 942ac052 | balrog | #if 0
|
342 | 942ac052 | balrog | if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN))
|
343 | 942ac052 | balrog | ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
|
344 | 942ac052 | balrog | #endif
|
345 | 942ac052 | balrog | return ret;
|
346 | 942ac052 | balrog | case TUSB_DEV_OTG_TIMER:
|
347 | 942ac052 | balrog | return s->otg_timer_val;
|
348 | 942ac052 | balrog | |
349 | 942ac052 | balrog | case TUSB_PRCM_REV:
|
350 | 942ac052 | balrog | return 0x20; |
351 | 942ac052 | balrog | case TUSB_PRCM_CONF:
|
352 | 942ac052 | balrog | return s->prcm_config;
|
353 | 942ac052 | balrog | case TUSB_PRCM_MNGMT:
|
354 | 942ac052 | balrog | return s->prcm_mngmt;
|
355 | 942ac052 | balrog | case TUSB_PRCM_WAKEUP_SOURCE:
|
356 | 942ac052 | balrog | case TUSB_PRCM_WAKEUP_CLEAR: /* TODO: What does this one return? */ |
357 | 942ac052 | balrog | return 0x00000000; |
358 | 942ac052 | balrog | case TUSB_PRCM_WAKEUP_MASK:
|
359 | 942ac052 | balrog | return s->wkup_mask;
|
360 | 942ac052 | balrog | |
361 | 942ac052 | balrog | case TUSB_PULLUP_1_CTRL:
|
362 | 942ac052 | balrog | return s->pullup[0]; |
363 | 942ac052 | balrog | case TUSB_PULLUP_2_CTRL:
|
364 | 942ac052 | balrog | return s->pullup[1]; |
365 | 942ac052 | balrog | |
366 | 942ac052 | balrog | case TUSB_INT_CTRL_REV:
|
367 | 942ac052 | balrog | return 0x20; |
368 | 942ac052 | balrog | case TUSB_INT_CTRL_CONF:
|
369 | 942ac052 | balrog | return s->control_config;
|
370 | 942ac052 | balrog | |
371 | 942ac052 | balrog | case TUSB_USBIP_INT_SRC:
|
372 | 942ac052 | balrog | case TUSB_USBIP_INT_SET: /* TODO: What do these two return? */ |
373 | 942ac052 | balrog | case TUSB_USBIP_INT_CLEAR:
|
374 | 942ac052 | balrog | return s->usbip_intr;
|
375 | 942ac052 | balrog | case TUSB_USBIP_INT_MASK:
|
376 | 942ac052 | balrog | return s->usbip_mask;
|
377 | 942ac052 | balrog | |
378 | 942ac052 | balrog | case TUSB_DMA_INT_SRC:
|
379 | 942ac052 | balrog | case TUSB_DMA_INT_SET: /* TODO: What do these two return? */ |
380 | 942ac052 | balrog | case TUSB_DMA_INT_CLEAR:
|
381 | 942ac052 | balrog | return s->dma_intr;
|
382 | 942ac052 | balrog | case TUSB_DMA_INT_MASK:
|
383 | 942ac052 | balrog | return s->dma_mask;
|
384 | 942ac052 | balrog | |
385 | 942ac052 | balrog | case TUSB_GPIO_INT_SRC: /* TODO: What do these two return? */ |
386 | 942ac052 | balrog | case TUSB_GPIO_INT_SET:
|
387 | 942ac052 | balrog | case TUSB_GPIO_INT_CLEAR:
|
388 | 942ac052 | balrog | return s->gpio_intr;
|
389 | 942ac052 | balrog | case TUSB_GPIO_INT_MASK:
|
390 | 942ac052 | balrog | return s->gpio_mask;
|
391 | 942ac052 | balrog | |
392 | 942ac052 | balrog | case TUSB_INT_SRC:
|
393 | 942ac052 | balrog | case TUSB_INT_SRC_SET: /* TODO: What do these two return? */ |
394 | 942ac052 | balrog | case TUSB_INT_SRC_CLEAR:
|
395 | 942ac052 | balrog | return s->intr;
|
396 | 942ac052 | balrog | case TUSB_INT_MASK:
|
397 | 942ac052 | balrog | return s->mask;
|
398 | 942ac052 | balrog | |
399 | 942ac052 | balrog | case TUSB_GPIO_REV:
|
400 | 942ac052 | balrog | return 0x30; |
401 | 942ac052 | balrog | case TUSB_GPIO_CONF:
|
402 | 942ac052 | balrog | return s->gpio_config;
|
403 | 942ac052 | balrog | |
404 | 942ac052 | balrog | case TUSB_DMA_CTRL_REV:
|
405 | 942ac052 | balrog | return 0x30; |
406 | 942ac052 | balrog | case TUSB_DMA_REQ_CONF:
|
407 | 942ac052 | balrog | return s->dma_config;
|
408 | 942ac052 | balrog | case TUSB_EP0_CONF:
|
409 | 942ac052 | balrog | return s->ep0_config;
|
410 | 942ac052 | balrog | case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): |
411 | 942ac052 | balrog | epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
|
412 | 942ac052 | balrog | return s->tx_config[epnum];
|
413 | 942ac052 | balrog | case TUSB_DMA_EP_MAP:
|
414 | 942ac052 | balrog | return s->dma_map;
|
415 | 942ac052 | balrog | case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): |
416 | 942ac052 | balrog | epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
|
417 | 942ac052 | balrog | return s->rx_config[epnum];
|
418 | 942ac052 | balrog | case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
|
419 | 942ac052 | balrog | (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
|
420 | 942ac052 | balrog | return 0x00000000; /* TODO */ |
421 | 942ac052 | balrog | case TUSB_WAIT_COUNT:
|
422 | 942ac052 | balrog | return 0x00; /* TODO */ |
423 | 942ac052 | balrog | |
424 | 942ac052 | balrog | case TUSB_SCRATCH_PAD:
|
425 | 942ac052 | balrog | return s->scratch;
|
426 | 942ac052 | balrog | |
427 | 942ac052 | balrog | case TUSB_PROD_TEST_RESET:
|
428 | 942ac052 | balrog | return s->test_reset;
|
429 | 942ac052 | balrog | |
430 | 942ac052 | balrog | /* DIE IDs */
|
431 | 942ac052 | balrog | case TUSB_DIDR1_LO:
|
432 | 942ac052 | balrog | return 0xa9453c59; |
433 | 942ac052 | balrog | case TUSB_DIDR1_HI:
|
434 | 942ac052 | balrog | return 0x54059adf; |
435 | 942ac052 | balrog | } |
436 | 942ac052 | balrog | |
437 | 942ac052 | balrog | printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
|
438 | 942ac052 | balrog | return 0; |
439 | 942ac052 | balrog | } |
440 | 942ac052 | balrog | |
441 | a8170e5e | Avi Kivity | static void tusb_async_writeb(void *opaque, hwaddr addr, |
442 | 942ac052 | balrog | uint32_t value) |
443 | 942ac052 | balrog | { |
444 | bc24a225 | Paul Brook | TUSBState *s = (TUSBState *) opaque; |
445 | 942ac052 | balrog | |
446 | 942ac052 | balrog | switch (addr & 0xfff) { |
447 | 942ac052 | balrog | case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
448 | 942ac052 | balrog | musb_write[0](s->musb, addr & 0x1ff, value); |
449 | 942ac052 | balrog | break;
|
450 | 942ac052 | balrog | |
451 | 942ac052 | balrog | case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
452 | 942ac052 | balrog | musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
453 | 942ac052 | balrog | break;
|
454 | 942ac052 | balrog | |
455 | 942ac052 | balrog | default:
|
456 | 942ac052 | balrog | printf("%s: unknown register at %03x\n",
|
457 | 942ac052 | balrog | __FUNCTION__, (int) (addr & 0xfff)); |
458 | 942ac052 | balrog | return;
|
459 | 942ac052 | balrog | } |
460 | 942ac052 | balrog | } |
461 | 942ac052 | balrog | |
462 | a8170e5e | Avi Kivity | static void tusb_async_writeh(void *opaque, hwaddr addr, |
463 | 942ac052 | balrog | uint32_t value) |
464 | 942ac052 | balrog | { |
465 | bc24a225 | Paul Brook | TUSBState *s = (TUSBState *) opaque; |
466 | 942ac052 | balrog | |
467 | 942ac052 | balrog | switch (addr & 0xfff) { |
468 | 942ac052 | balrog | case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
469 | 942ac052 | balrog | musb_write[1](s->musb, addr & 0x1ff, value); |
470 | 942ac052 | balrog | break;
|
471 | 942ac052 | balrog | |
472 | 942ac052 | balrog | case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
473 | 942ac052 | balrog | musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
474 | 942ac052 | balrog | break;
|
475 | 942ac052 | balrog | |
476 | 942ac052 | balrog | default:
|
477 | 942ac052 | balrog | printf("%s: unknown register at %03x\n",
|
478 | 942ac052 | balrog | __FUNCTION__, (int) (addr & 0xfff)); |
479 | 942ac052 | balrog | return;
|
480 | 942ac052 | balrog | } |
481 | 942ac052 | balrog | } |
482 | 942ac052 | balrog | |
483 | a8170e5e | Avi Kivity | static void tusb_async_writew(void *opaque, hwaddr addr, |
484 | 942ac052 | balrog | uint32_t value) |
485 | 942ac052 | balrog | { |
486 | bc24a225 | Paul Brook | TUSBState *s = (TUSBState *) opaque; |
487 | 942ac052 | balrog | int offset = addr & 0xfff; |
488 | 942ac052 | balrog | int epnum;
|
489 | 942ac052 | balrog | |
490 | 942ac052 | balrog | switch (offset) {
|
491 | 942ac052 | balrog | case TUSB_VLYNQ_CTRL:
|
492 | 942ac052 | balrog | break;
|
493 | 942ac052 | balrog | |
494 | 942ac052 | balrog | case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
495 | 942ac052 | balrog | musb_write[2](s->musb, offset & 0x1ff, value); |
496 | 942ac052 | balrog | break;
|
497 | 942ac052 | balrog | |
498 | 942ac052 | balrog | case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
499 | 942ac052 | balrog | musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
500 | 942ac052 | balrog | break;
|
501 | 942ac052 | balrog | |
502 | 942ac052 | balrog | case TUSB_DEV_CONF:
|
503 | 942ac052 | balrog | s->dev_config = value; |
504 | 942ac052 | balrog | s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE); |
505 | 942ac052 | balrog | if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
|
506 | 2ac71179 | Paul Brook | hw_error("%s: Product Test mode not allowed\n", __FUNCTION__);
|
507 | 942ac052 | balrog | break;
|
508 | 942ac052 | balrog | |
509 | 942ac052 | balrog | case TUSB_PHY_OTG_CTRL_ENABLE:
|
510 | 942ac052 | balrog | case TUSB_PHY_OTG_CTRL:
|
511 | 942ac052 | balrog | return; /* TODO */ |
512 | 942ac052 | balrog | case TUSB_DEV_OTG_TIMER:
|
513 | 942ac052 | balrog | s->otg_timer_val = value; |
514 | 942ac052 | balrog | if (value & TUSB_DEV_OTG_TIMER_ENABLE)
|
515 | 74475455 | Paolo Bonzini | qemu_mod_timer(s->otg_timer, qemu_get_clock_ns(vm_clock) + |
516 | 942ac052 | balrog | muldiv64(TUSB_DEV_OTG_TIMER_VAL(value), |
517 | 6ee093c9 | Juan Quintela | get_ticks_per_sec(), TUSB_DEVCLOCK)); |
518 | 942ac052 | balrog | else
|
519 | 942ac052 | balrog | qemu_del_timer(s->otg_timer); |
520 | 942ac052 | balrog | break;
|
521 | 942ac052 | balrog | |
522 | 942ac052 | balrog | case TUSB_PRCM_CONF:
|
523 | 942ac052 | balrog | s->prcm_config = value; |
524 | 942ac052 | balrog | break;
|
525 | 942ac052 | balrog | case TUSB_PRCM_MNGMT:
|
526 | 942ac052 | balrog | s->prcm_mngmt = value; |
527 | 942ac052 | balrog | break;
|
528 | 942ac052 | balrog | case TUSB_PRCM_WAKEUP_CLEAR:
|
529 | 942ac052 | balrog | break;
|
530 | 942ac052 | balrog | case TUSB_PRCM_WAKEUP_MASK:
|
531 | 942ac052 | balrog | s->wkup_mask = value; |
532 | 942ac052 | balrog | break;
|
533 | 942ac052 | balrog | |
534 | 942ac052 | balrog | case TUSB_PULLUP_1_CTRL:
|
535 | 942ac052 | balrog | s->pullup[0] = value;
|
536 | 942ac052 | balrog | break;
|
537 | 942ac052 | balrog | case TUSB_PULLUP_2_CTRL:
|
538 | 942ac052 | balrog | s->pullup[1] = value;
|
539 | 942ac052 | balrog | break;
|
540 | 942ac052 | balrog | case TUSB_INT_CTRL_CONF:
|
541 | 942ac052 | balrog | s->control_config = value; |
542 | 942ac052 | balrog | tusb_intr_update(s); |
543 | 942ac052 | balrog | break;
|
544 | 942ac052 | balrog | |
545 | 942ac052 | balrog | case TUSB_USBIP_INT_SET:
|
546 | 942ac052 | balrog | s->usbip_intr |= value; |
547 | 942ac052 | balrog | tusb_usbip_intr_update(s); |
548 | 942ac052 | balrog | break;
|
549 | 942ac052 | balrog | case TUSB_USBIP_INT_CLEAR:
|
550 | 942ac052 | balrog | s->usbip_intr &= ~value; |
551 | 942ac052 | balrog | tusb_usbip_intr_update(s); |
552 | 942ac052 | balrog | musb_core_intr_clear(s->musb, ~value); |
553 | 942ac052 | balrog | break;
|
554 | 942ac052 | balrog | case TUSB_USBIP_INT_MASK:
|
555 | 942ac052 | balrog | s->usbip_mask = value; |
556 | 942ac052 | balrog | tusb_usbip_intr_update(s); |
557 | 942ac052 | balrog | break;
|
558 | 942ac052 | balrog | |
559 | 942ac052 | balrog | case TUSB_DMA_INT_SET:
|
560 | 942ac052 | balrog | s->dma_intr |= value; |
561 | 942ac052 | balrog | tusb_dma_intr_update(s); |
562 | 942ac052 | balrog | break;
|
563 | 942ac052 | balrog | case TUSB_DMA_INT_CLEAR:
|
564 | 942ac052 | balrog | s->dma_intr &= ~value; |
565 | 942ac052 | balrog | tusb_dma_intr_update(s); |
566 | 942ac052 | balrog | break;
|
567 | 942ac052 | balrog | case TUSB_DMA_INT_MASK:
|
568 | 942ac052 | balrog | s->dma_mask = value; |
569 | 942ac052 | balrog | tusb_dma_intr_update(s); |
570 | 942ac052 | balrog | break;
|
571 | 942ac052 | balrog | |
572 | 942ac052 | balrog | case TUSB_GPIO_INT_SET:
|
573 | 942ac052 | balrog | s->gpio_intr |= value; |
574 | 942ac052 | balrog | tusb_gpio_intr_update(s); |
575 | 942ac052 | balrog | break;
|
576 | 942ac052 | balrog | case TUSB_GPIO_INT_CLEAR:
|
577 | 942ac052 | balrog | s->gpio_intr &= ~value; |
578 | 942ac052 | balrog | tusb_gpio_intr_update(s); |
579 | 942ac052 | balrog | break;
|
580 | 942ac052 | balrog | case TUSB_GPIO_INT_MASK:
|
581 | 942ac052 | balrog | s->gpio_mask = value; |
582 | 942ac052 | balrog | tusb_gpio_intr_update(s); |
583 | 942ac052 | balrog | break;
|
584 | 942ac052 | balrog | |
585 | 942ac052 | balrog | case TUSB_INT_SRC_SET:
|
586 | 942ac052 | balrog | s->intr |= value; |
587 | 942ac052 | balrog | tusb_intr_update(s); |
588 | 942ac052 | balrog | break;
|
589 | 942ac052 | balrog | case TUSB_INT_SRC_CLEAR:
|
590 | 942ac052 | balrog | s->intr &= ~value; |
591 | 942ac052 | balrog | tusb_intr_update(s); |
592 | 942ac052 | balrog | break;
|
593 | 942ac052 | balrog | case TUSB_INT_MASK:
|
594 | 942ac052 | balrog | s->mask = value; |
595 | 942ac052 | balrog | tusb_intr_update(s); |
596 | 942ac052 | balrog | break;
|
597 | 942ac052 | balrog | |
598 | 942ac052 | balrog | case TUSB_GPIO_CONF:
|
599 | 942ac052 | balrog | s->gpio_config = value; |
600 | 942ac052 | balrog | break;
|
601 | 942ac052 | balrog | case TUSB_DMA_REQ_CONF:
|
602 | 942ac052 | balrog | s->dma_config = value; |
603 | 942ac052 | balrog | break;
|
604 | 942ac052 | balrog | case TUSB_EP0_CONF:
|
605 | 942ac052 | balrog | s->ep0_config = value & 0x1ff;
|
606 | 942ac052 | balrog | musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value),
|
607 | 942ac052 | balrog | value & TUSB_EP0_CONFIG_DIR_TX); |
608 | 942ac052 | balrog | break;
|
609 | 942ac052 | balrog | case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): |
610 | 942ac052 | balrog | epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
|
611 | 942ac052 | balrog | s->tx_config[epnum] = value; |
612 | 942ac052 | balrog | musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1); |
613 | 942ac052 | balrog | break;
|
614 | 942ac052 | balrog | case TUSB_DMA_EP_MAP:
|
615 | 942ac052 | balrog | s->dma_map = value; |
616 | 942ac052 | balrog | break;
|
617 | 942ac052 | balrog | case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): |
618 | 942ac052 | balrog | epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
|
619 | 942ac052 | balrog | s->rx_config[epnum] = value; |
620 | 942ac052 | balrog | musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0); |
621 | 942ac052 | balrog | break;
|
622 | 942ac052 | balrog | case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
|
623 | 942ac052 | balrog | (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
|
624 | 942ac052 | balrog | return; /* TODO */ |
625 | 942ac052 | balrog | case TUSB_WAIT_COUNT:
|
626 | 942ac052 | balrog | return; /* TODO */ |
627 | 942ac052 | balrog | |
628 | 942ac052 | balrog | case TUSB_SCRATCH_PAD:
|
629 | 942ac052 | balrog | s->scratch = value; |
630 | 942ac052 | balrog | break;
|
631 | 942ac052 | balrog | |
632 | 942ac052 | balrog | case TUSB_PROD_TEST_RESET:
|
633 | 942ac052 | balrog | s->test_reset = value; |
634 | 942ac052 | balrog | break;
|
635 | 942ac052 | balrog | |
636 | 942ac052 | balrog | default:
|
637 | 942ac052 | balrog | printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
|
638 | 942ac052 | balrog | return;
|
639 | 942ac052 | balrog | } |
640 | 942ac052 | balrog | } |
641 | 942ac052 | balrog | |
642 | 64066a8f | Avi Kivity | static const MemoryRegionOps tusb_async_ops = { |
643 | 64066a8f | Avi Kivity | .old_mmio = { |
644 | 64066a8f | Avi Kivity | .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, }, |
645 | 64066a8f | Avi Kivity | .write = { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, }, |
646 | 64066a8f | Avi Kivity | }, |
647 | 64066a8f | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
648 | 942ac052 | balrog | }; |
649 | 942ac052 | balrog | |
650 | 942ac052 | balrog | static void tusb_otg_tick(void *opaque) |
651 | 942ac052 | balrog | { |
652 | bc24a225 | Paul Brook | TUSBState *s = (TUSBState *) opaque; |
653 | 942ac052 | balrog | |
654 | 942ac052 | balrog | s->otg_timer_val = 0;
|
655 | 942ac052 | balrog | s->intr |= TUSB_INT_SRC_OTG_TIMEOUT; |
656 | 942ac052 | balrog | tusb_intr_update(s); |
657 | 942ac052 | balrog | } |
658 | 942ac052 | balrog | |
659 | 942ac052 | balrog | static void tusb_power_tick(void *opaque) |
660 | 942ac052 | balrog | { |
661 | bc24a225 | Paul Brook | TUSBState *s = (TUSBState *) opaque; |
662 | 942ac052 | balrog | |
663 | 942ac052 | balrog | if (s->power) {
|
664 | 942ac052 | balrog | s->intr_ok = ~0;
|
665 | 942ac052 | balrog | tusb_intr_update(s); |
666 | 942ac052 | balrog | } |
667 | 942ac052 | balrog | } |
668 | 942ac052 | balrog | |
669 | 942ac052 | balrog | static void tusb_musb_core_intr(void *opaque, int source, int level) |
670 | 942ac052 | balrog | { |
671 | bc24a225 | Paul Brook | TUSBState *s = (TUSBState *) opaque; |
672 | 942ac052 | balrog | uint16_t otg_status = s->otg_status; |
673 | 942ac052 | balrog | |
674 | 942ac052 | balrog | switch (source) {
|
675 | 942ac052 | balrog | case musb_set_vbus:
|
676 | 942ac052 | balrog | if (level)
|
677 | 942ac052 | balrog | otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID; |
678 | 942ac052 | balrog | else
|
679 | 942ac052 | balrog | otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID; |
680 | 942ac052 | balrog | |
681 | 942ac052 | balrog | /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set? */
|
682 | 942ac052 | balrog | /* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set? */
|
683 | 942ac052 | balrog | if (s->otg_status != otg_status) {
|
684 | 942ac052 | balrog | s->otg_status = otg_status; |
685 | 942ac052 | balrog | s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG; |
686 | 942ac052 | balrog | tusb_intr_update(s); |
687 | 942ac052 | balrog | } |
688 | 942ac052 | balrog | break;
|
689 | 942ac052 | balrog | |
690 | 942ac052 | balrog | case musb_set_session:
|
691 | 942ac052 | balrog | /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set? */
|
692 | 942ac052 | balrog | /* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set? */
|
693 | 942ac052 | balrog | if (level) {
|
694 | 942ac052 | balrog | s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID; |
695 | 942ac052 | balrog | s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END; |
696 | 942ac052 | balrog | } else {
|
697 | 942ac052 | balrog | s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID; |
698 | 942ac052 | balrog | s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END; |
699 | 942ac052 | balrog | } |
700 | 942ac052 | balrog | |
701 | 942ac052 | balrog | /* XXX: some IRQ or anything? */
|
702 | 942ac052 | balrog | break;
|
703 | 942ac052 | balrog | |
704 | 942ac052 | balrog | case musb_irq_tx:
|
705 | 942ac052 | balrog | case musb_irq_rx:
|
706 | 942ac052 | balrog | s->usbip_intr = musb_core_intr_get(s->musb); |
707 | 942ac052 | balrog | /* Fall through. */
|
708 | 942ac052 | balrog | default:
|
709 | 942ac052 | balrog | if (level)
|
710 | 942ac052 | balrog | s->intr |= 1 << source;
|
711 | 942ac052 | balrog | else
|
712 | 942ac052 | balrog | s->intr &= ~(1 << source);
|
713 | 942ac052 | balrog | tusb_intr_update(s); |
714 | 942ac052 | balrog | break;
|
715 | 942ac052 | balrog | } |
716 | 942ac052 | balrog | } |
717 | 942ac052 | balrog | |
718 | bdc76462 | Peter Maydell | static void tusb6010_power(TUSBState *s, int on) |
719 | 942ac052 | balrog | { |
720 | bdc76462 | Peter Maydell | if (!on) {
|
721 | bdc76462 | Peter Maydell | s->power = 0;
|
722 | bdc76462 | Peter Maydell | } else if (!s->power && on) { |
723 | bdc76462 | Peter Maydell | s->power = 1;
|
724 | bdc76462 | Peter Maydell | /* Pull the interrupt down after TUSB6010 comes up. */
|
725 | bdc76462 | Peter Maydell | s->intr_ok = 0;
|
726 | bdc76462 | Peter Maydell | tusb_intr_update(s); |
727 | bdc76462 | Peter Maydell | qemu_mod_timer(s->pwr_timer, |
728 | bdc76462 | Peter Maydell | qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 2);
|
729 | bdc76462 | Peter Maydell | } |
730 | bdc76462 | Peter Maydell | } |
731 | bdc76462 | Peter Maydell | |
732 | bdc76462 | Peter Maydell | static void tusb6010_irq(void *opaque, int source, int level) |
733 | bdc76462 | Peter Maydell | { |
734 | bdc76462 | Peter Maydell | if (source) {
|
735 | bdc76462 | Peter Maydell | tusb_musb_core_intr(opaque, source - 1, level);
|
736 | bdc76462 | Peter Maydell | } else {
|
737 | bdc76462 | Peter Maydell | tusb6010_power(opaque, level); |
738 | bdc76462 | Peter Maydell | } |
739 | bdc76462 | Peter Maydell | } |
740 | bdc76462 | Peter Maydell | |
741 | bdc76462 | Peter Maydell | static void tusb6010_reset(DeviceState *dev) |
742 | bdc76462 | Peter Maydell | { |
743 | 1356b98d | Andreas Färber | TUSBState *s = FROM_SYSBUS(TUSBState, SYS_BUS_DEVICE(dev)); |
744 | bdc76462 | Peter Maydell | int i;
|
745 | 942ac052 | balrog | |
746 | 942ac052 | balrog | s->test_reset = TUSB_PROD_TEST_RESET_VAL; |
747 | 942ac052 | balrog | s->host_mode = 0;
|
748 | 942ac052 | balrog | s->dev_config = 0;
|
749 | 942ac052 | balrog | s->otg_status = 0; /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */ |
750 | 942ac052 | balrog | s->power = 0;
|
751 | 942ac052 | balrog | s->mask = 0xffffffff;
|
752 | 942ac052 | balrog | s->intr = 0x00000000;
|
753 | 942ac052 | balrog | s->otg_timer_val = 0;
|
754 | bdc76462 | Peter Maydell | s->scratch = 0;
|
755 | bdc76462 | Peter Maydell | s->prcm_config = 0;
|
756 | bdc76462 | Peter Maydell | s->prcm_mngmt = 0;
|
757 | bdc76462 | Peter Maydell | s->intr_ok = 0;
|
758 | bdc76462 | Peter Maydell | s->usbip_intr = 0;
|
759 | bdc76462 | Peter Maydell | s->usbip_mask = 0;
|
760 | bdc76462 | Peter Maydell | s->gpio_intr = 0;
|
761 | bdc76462 | Peter Maydell | s->gpio_mask = 0;
|
762 | bdc76462 | Peter Maydell | s->gpio_config = 0;
|
763 | bdc76462 | Peter Maydell | s->dma_intr = 0;
|
764 | bdc76462 | Peter Maydell | s->dma_mask = 0;
|
765 | bdc76462 | Peter Maydell | s->dma_map = 0;
|
766 | bdc76462 | Peter Maydell | s->dma_config = 0;
|
767 | bdc76462 | Peter Maydell | s->ep0_config = 0;
|
768 | bdc76462 | Peter Maydell | s->wkup_mask = 0;
|
769 | bdc76462 | Peter Maydell | s->pullup[0] = s->pullup[1] = 0; |
770 | bdc76462 | Peter Maydell | s->control_config = 0;
|
771 | bdc76462 | Peter Maydell | for (i = 0; i < 15; i++) { |
772 | bdc76462 | Peter Maydell | s->rx_config[i] = s->tx_config[i] = 0;
|
773 | bdc76462 | Peter Maydell | } |
774 | 5b1cdb4e | Juha Riihimäki | musb_reset(s->musb); |
775 | bdc76462 | Peter Maydell | } |
776 | bdc76462 | Peter Maydell | |
777 | bdc76462 | Peter Maydell | static int tusb6010_init(SysBusDevice *dev) |
778 | bdc76462 | Peter Maydell | { |
779 | bdc76462 | Peter Maydell | TUSBState *s = FROM_SYSBUS(TUSBState, dev); |
780 | 74475455 | Paolo Bonzini | s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s); |
781 | 74475455 | Paolo Bonzini | s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s); |
782 | bdc76462 | Peter Maydell | memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async", |
783 | bdc76462 | Peter Maydell | UINT32_MAX); |
784 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->iomem[0]);
|
785 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->iomem[1]);
|
786 | bdc76462 | Peter Maydell | sysbus_init_irq(dev, &s->irq); |
787 | 9147b752 | Peter Maydell | qdev_init_gpio_in(&dev->qdev, tusb6010_irq, musb_irq_max + 1);
|
788 | 406c2075 | Peter Maydell | s->musb = musb_init(&dev->qdev, 1);
|
789 | bdc76462 | Peter Maydell | return 0; |
790 | 942ac052 | balrog | } |
791 | 942ac052 | balrog | |
792 | 999e12bb | Anthony Liguori | static void tusb6010_class_init(ObjectClass *klass, void *data) |
793 | 999e12bb | Anthony Liguori | { |
794 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
795 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
796 | 999e12bb | Anthony Liguori | |
797 | 999e12bb | Anthony Liguori | k->init = tusb6010_init; |
798 | 39bffca2 | Anthony Liguori | dc->reset = tusb6010_reset; |
799 | 999e12bb | Anthony Liguori | } |
800 | 999e12bb | Anthony Liguori | |
801 | 8c43a6f0 | Andreas Färber | static const TypeInfo tusb6010_info = { |
802 | 39bffca2 | Anthony Liguori | .name = "tusb6010",
|
803 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
804 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(TUSBState),
|
805 | 39bffca2 | Anthony Liguori | .class_init = tusb6010_class_init, |
806 | bdc76462 | Peter Maydell | }; |
807 | 942ac052 | balrog | |
808 | 83f7d43a | Andreas Färber | static void tusb6010_register_types(void) |
809 | bdc76462 | Peter Maydell | { |
810 | 39bffca2 | Anthony Liguori | type_register_static(&tusb6010_info); |
811 | 942ac052 | balrog | } |
812 | bdc76462 | Peter Maydell | |
813 | 83f7d43a | Andreas Färber | type_init(tusb6010_register_types) |