Archipelago » qemu

#include "exec.h"

#include "host-utils.h"

#include "helper.h"

#if !defined(CONFIG_USER_ONLY)

#include "softmmu_exec.h"

#endif /* !defined(CONFIG_USER_ONLY) */

//#define DEBUG_MMU

//#define DEBUG_MXCC

//#define DEBUG_UNALIGNED

//#define DEBUG_UNASSIGNED

//#define DEBUG_ASI

//#define DEBUG_PCALL

//#define DEBUG_PSTATE

#ifdef DEBUG_MMU

#define DPRINTF_MMU(fmt, ...)                                   \

    do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)

#else

#define DPRINTF_MMU(fmt, ...) do {} while (0)

#endif

#ifdef DEBUG_MXCC

#define DPRINTF_MXCC(fmt, ...)                                  \

    do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)

#else

#define DPRINTF_MXCC(fmt, ...) do {} while (0)

#endif

#ifdef DEBUG_ASI

#define DPRINTF_ASI(fmt, ...)                                   \

    do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)

#endif

#ifdef DEBUG_PSTATE

#define DPRINTF_PSTATE(fmt, ...)                                   \

    do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)

#else

#define DPRINTF_PSTATE(fmt, ...) do {} while (0)

#endif

#ifdef TARGET_SPARC64

#ifndef TARGET_ABI32

#define AM_CHECK(env1) ((env1)->pstate & PS_AM)

#else

#define AM_CHECK(env1) (1)

#endif

#endif

#if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)

static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,

                          int is_asi, int size);

#endif

#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)

// Calculates TSB pointer value for fault page size 8k or 64k

static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,

                                       uint64_t tag_access_register,

                                       int page_size)

{

    uint64_t tsb_base = tsb_register & ~0x1fffULL;

    int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;

    int tsb_size  = tsb_register & 0xf;

    // discard lower 13 bits which hold tag access context

    uint64_t tag_access_va = tag_access_register & ~0x1fffULL;

    // now reorder bits

    uint64_t tsb_base_mask = ~0x1fffULL;

    uint64_t va = tag_access_va;

    // move va bits to correct position

    if (page_size == 8*1024) {

        va >>= 9;

    } else if (page_size == 64*1024) {

        va >>= 12;

    }

    if (tsb_size) {

        tsb_base_mask <<= tsb_size;

    }

    // calculate tsb_base mask and adjust va if split is in use

    if (tsb_split) {

        if (page_size == 8*1024) {

            va &= ~(1ULL << (13 + tsb_size));

        } else if (page_size == 64*1024) {

            va |= (1ULL << (13 + tsb_size));

        }

        tsb_base_mask <<= 1;

    }

    return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;

}

// Calculates tag target register value by reordering bits

// in tag access register

static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)

{

    return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);

}

static void replace_tlb_entry(SparcTLBEntry *tlb,

                              uint64_t tlb_tag, uint64_t tlb_tte,

                              CPUState *env1)

{

    target_ulong mask, size, va, offset;

    // flush page range if translation is valid

    if (TTE_IS_VALID(tlb->tte)) {

        mask = 0xffffffffffffe000ULL;

        mask <<= 3 * ((tlb->tte >> 61) & 3);

        size = ~mask + 1;

        va = tlb->tag & mask;

        for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {

            tlb_flush_page(env1, va + offset);

        }

    }

    tlb->tag = tlb_tag;

    tlb->tte = tlb_tte;

}

static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,

                      const char* strmmu, CPUState *env1)

{

    unsigned int i;

    target_ulong mask;

    for (i = 0; i < 64; i++) {

        if (TTE_IS_VALID(tlb[i].tte)) {

            mask = 0xffffffffffffe000ULL;

            mask <<= 3 * ((tlb[i].tte >> 61) & 3);

            if ((demap_addr & mask) == (tlb[i].tag & mask)) {

                replace_tlb_entry(&tlb[i], 0, 0, env1);

#ifdef DEBUG_MMU

                DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);

                dump_mmu(env1);

#endif

            }

            //return;

        }

    }

}

static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,

                                 uint64_t tlb_tag, uint64_t tlb_tte,

                                 const char* strmmu, CPUState *env1)

{

    unsigned int i, replace_used;

    // Try replacing invalid entry

    for (i = 0; i < 64; i++) {

        if (!TTE_IS_VALID(tlb[i].tte)) {

            replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);

#ifdef DEBUG_MMU

            DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);

            dump_mmu(env1);

#endif

            return;

        }

    }

    // All entries are valid, try replacing unlocked entry

    for (replace_used = 0; replace_used < 2; ++replace_used) {

        // Used entries are not replaced on first pass

        for (i = 0; i < 64; i++) {

            if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {

                replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);

#ifdef DEBUG_MMU

                DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",

                            strmmu, (replace_used?"used":"unused"), i);

                dump_mmu(env1);

#endif

                return;

            }

        }

        // Now reset used bit and search for unused entries again

        for (i = 0; i < 64; i++) {

            TTE_SET_UNUSED(tlb[i].tte);

        }

    }

#ifdef DEBUG_MMU

    DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);

#endif

    // error state?

}

#endif

static inline void address_mask(CPUState *env1, target_ulong *addr)

{

#ifdef TARGET_SPARC64

    if (AM_CHECK(env1))

        *addr &= 0xffffffffULL;

#endif

}

static void raise_exception(int tt)

{

    env->exception_index = tt;

    cpu_loop_exit();

}

void HELPER(raise_exception)(int tt)

{

    raise_exception(tt);

}

static inline void set_cwp(int new_cwp)

{

    cpu_set_cwp(env, new_cwp);

}

void helper_check_align(target_ulong addr, uint32_t align)

{

    if (addr & align) {

#ifdef DEBUG_UNALIGNED

    printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx

           "\n", addr, env->pc);

#endif

        raise_exception(TT_UNALIGNED);

    }

}

#define F_HELPER(name, p) void helper_f##name##p(void)

#define F_BINOP(name)                                           \

    float32 helper_f ## name ## s (float32 src1, float32 src2)  \

    {                                                           \

        return float32_ ## name (src1, src2, &env->fp_status);  \

    }                                                           \

    F_HELPER(name, d)                                           \

    {                                                           \

        DT0 = float64_ ## name (DT0, DT1, &env->fp_status);     \

    }                                                           \

    F_HELPER(name, q)                                           \

    {                                                           \

        QT0 = float128_ ## name (QT0, QT1, &env->fp_status);    \

    }

F_BINOP(add);

F_BINOP(sub);

F_BINOP(mul);

F_BINOP(div);

#undef F_BINOP

void helper_fsmuld(float32 src1, float32 src2)

{

    DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),

                      float32_to_float64(src2, &env->fp_status),

                      &env->fp_status);

}

void helper_fdmulq(void)

{

    QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),

                       float64_to_float128(DT1, &env->fp_status),

                       &env->fp_status);

}

float32 helper_fnegs(float32 src)

{

    return float32_chs(src);

}

#ifdef TARGET_SPARC64

F_HELPER(neg, d)

{

    DT0 = float64_chs(DT1);

}

F_HELPER(neg, q)

{

    QT0 = float128_chs(QT1);

}

#endif

/* Integer to float conversion.  */

float32 helper_fitos(int32_t src)

{

    return int32_to_float32(src, &env->fp_status);

}

void helper_fitod(int32_t src)

{

    DT0 = int32_to_float64(src, &env->fp_status);

}

void helper_fitoq(int32_t src)

{

    QT0 = int32_to_float128(src, &env->fp_status);

}

#ifdef TARGET_SPARC64

float32 helper_fxtos(void)

{

    return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);

}

F_HELPER(xto, d)

{

    DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);

}

F_HELPER(xto, q)

{

    QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);

}

#endif

#undef F_HELPER

/* floating point conversion */

float32 helper_fdtos(void)

{

    return float64_to_float32(DT1, &env->fp_status);

}

void helper_fstod(float32 src)

{

    DT0 = float32_to_float64(src, &env->fp_status);

}

float32 helper_fqtos(void)

{

    return float128_to_float32(QT1, &env->fp_status);

}

void helper_fstoq(float32 src)

{

    QT0 = float32_to_float128(src, &env->fp_status);

}

void helper_fqtod(void)

{

    DT0 = float128_to_float64(QT1, &env->fp_status);

}

void helper_fdtoq(void)

{

    QT0 = float64_to_float128(DT1, &env->fp_status);

}

/* Float to integer conversion.  */

int32_t helper_fstoi(float32 src)

{

    return float32_to_int32_round_to_zero(src, &env->fp_status);

}

int32_t helper_fdtoi(void)

{

    return float64_to_int32_round_to_zero(DT1, &env->fp_status);

}

int32_t helper_fqtoi(void)

{

    return float128_to_int32_round_to_zero(QT1, &env->fp_status);

}

#ifdef TARGET_SPARC64

void helper_fstox(float32 src)

{

    *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);

}

void helper_fdtox(void)

{

    *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);

}

void helper_fqtox(void)

{

    *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);

}

void helper_faligndata(void)

{

    uint64_t tmp;

    tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);

    /* on many architectures a shift of 64 does nothing */

    if ((env->gsr & 7) != 0) {

        tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);

    }

    *((uint64_t *)&DT0) = tmp;

}

#ifdef HOST_WORDS_BIGENDIAN

#define VIS_B64(n) b[7 - (n)]

#define VIS_W64(n) w[3 - (n)]

#define VIS_SW64(n) sw[3 - (n)]

#define VIS_L64(n) l[1 - (n)]

#define VIS_B32(n) b[3 - (n)]

#define VIS_W32(n) w[1 - (n)]

#else

#define VIS_B64(n) b[n]

#define VIS_W64(n) w[n]

#define VIS_SW64(n) sw[n]

#define VIS_L64(n) l[n]

#define VIS_B32(n) b[n]

#define VIS_W32(n) w[n]

#endif

typedef union {

    uint8_t b[8];

    uint16_t w[4];

    int16_t sw[4];

    uint32_t l[2];

    float64 d;

} vis64;

typedef union {

    uint8_t b[4];

    uint16_t w[2];

    uint32_t l;

    float32 f;

} vis32;

void helper_fpmerge(void)

{

    vis64 s, d;

    s.d = DT0;

    d.d = DT1;

    // Reverse calculation order to handle overlap

    d.VIS_B64(7) = s.VIS_B64(3);

    d.VIS_B64(6) = d.VIS_B64(3);

    d.VIS_B64(5) = s.VIS_B64(2);

    d.VIS_B64(4) = d.VIS_B64(2);

    d.VIS_B64(3) = s.VIS_B64(1);

    d.VIS_B64(2) = d.VIS_B64(1);

    d.VIS_B64(1) = s.VIS_B64(0);

    //d.VIS_B64(0) = d.VIS_B64(0);

    DT0 = d.d;

}

void helper_fmul8x16(void)

{

    vis64 s, d;

    uint32_t tmp;

    s.d = DT0;

    d.d = DT1;

#define PMUL(r)                                                 \

    tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r);       \

    if ((tmp & 0xff) > 0x7f)                                    \

        tmp += 0x100;                                           \

    d.VIS_W64(r) = tmp >> 8;

    PMUL(0);

    PMUL(1);

    PMUL(2);

    PMUL(3);

#undef PMUL

    DT0 = d.d;

}

void helper_fmul8x16al(void)

{

    vis64 s, d;

    uint32_t tmp;

    s.d = DT0;

    d.d = DT1;

#define PMUL(r)                                                 \

    tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r);       \

    if ((tmp & 0xff) > 0x7f)                                    \

        tmp += 0x100;                                           \

    d.VIS_W64(r) = tmp >> 8;

    PMUL(0);

    PMUL(1);

    PMUL(2);

    PMUL(3);

#undef PMUL

    DT0 = d.d;

}

void helper_fmul8x16au(void)

{

    vis64 s, d;

    uint32_t tmp;

    s.d = DT0;

    d.d = DT1;

#define PMUL(r)                                                 \

    tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r);       \

    if ((tmp & 0xff) > 0x7f)                                    \

        tmp += 0x100;                                           \

    d.VIS_W64(r) = tmp >> 8;

    PMUL(0);

    PMUL(1);

    PMUL(2);

    PMUL(3);

#undef PMUL

    DT0 = d.d;

}

void helper_fmul8sux16(void)

{

    vis64 s, d;

    uint32_t tmp;

    s.d = DT0;

    d.d = DT1;

#define PMUL(r)                                                         \

    tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8);       \

    if ((tmp & 0xff) > 0x7f)                                            \

        tmp += 0x100;                                                   \

    d.VIS_W64(r) = tmp >> 8;

    PMUL(0);

    PMUL(1);

    PMUL(2);

    PMUL(3);

#undef PMUL

    DT0 = d.d;

}

void helper_fmul8ulx16(void)

{

    vis64 s, d;

    uint32_t tmp;

    s.d = DT0;

    d.d = DT1;

#define PMUL(r)                                                         \

    tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2));        \

    if ((tmp & 0xff) > 0x7f)                                            \

        tmp += 0x100;                                                   \

    d.VIS_W64(r) = tmp >> 8;

    PMUL(0);

    PMUL(1);

    PMUL(2);

    PMUL(3);

#undef PMUL

    DT0 = d.d;

}

void helper_fmuld8sux16(void)

{

    vis64 s, d;

    uint32_t tmp;

    s.d = DT0;

    d.d = DT1;

#define PMUL(r)                                                         \

    tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8);       \

    if ((tmp & 0xff) > 0x7f)                                            \

        tmp += 0x100;                                                   \

    d.VIS_L64(r) = tmp;

    // Reverse calculation order to handle overlap

    PMUL(1);

    PMUL(0);

#undef PMUL

    DT0 = d.d;

}

void helper_fmuld8ulx16(void)

{

    vis64 s, d;

    uint32_t tmp;

    s.d = DT0;

    d.d = DT1;

#define PMUL(r)                                                         \

    tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2));        \

    if ((tmp & 0xff) > 0x7f)                                            \

        tmp += 0x100;                                                   \

    d.VIS_L64(r) = tmp;

    // Reverse calculation order to handle overlap

    PMUL(1);

    PMUL(0);

#undef PMUL

    DT0 = d.d;

}

void helper_fexpand(void)

{

    vis32 s;

    vis64 d;

    s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);

    d.d = DT1;

    d.VIS_W64(0) = s.VIS_B32(0) << 4;

    d.VIS_W64(1) = s.VIS_B32(1) << 4;

    d.VIS_W64(2) = s.VIS_B32(2) << 4;

    d.VIS_W64(3) = s.VIS_B32(3) << 4;

    DT0 = d.d;

}

#define VIS_HELPER(name, F)                             \

    void name##16(void)                                 \

    {                                                   \

        vis64 s, d;                                     \

                                                        \

        s.d = DT0;                                      \

        d.d = DT1;                                      \

                                                        \

        d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0));   \

        d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1));   \

        d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2));   \

        d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3));   \

                                                        \

        DT0 = d.d;                                      \

    }                                                   \

                                                        \

    uint32_t name##16s(uint32_t src1, uint32_t src2)    \

    {                                                   \

        vis32 s, d;                                     \

                                                        \

        s.l = src1;                                     \

        d.l = src2;                                     \

                                                        \

        d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0));   \

        d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1));   \

                                                        \

        return d.l;                                     \

    }                                                   \

                                                        \

    void name##32(void)                                 \

    {                                                   \

        vis64 s, d;                                     \

                                                        \

        s.d = DT0;                                      \

        d.d = DT1;                                      \

                                                        \

        d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0));   \

        d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1));   \

                                                        \

        DT0 = d.d;                                      \

    }                                                   \

                                                        \

    uint32_t name##32s(uint32_t src1, uint32_t src2)    \

    {                                                   \

        vis32 s, d;                                     \

                                                        \

        s.l = src1;                                     \

        d.l = src2;                                     \

                                                        \

        d.l = F(d.l, s.l);                              \

                                                        \

        return d.l;                                     \

    }

#define FADD(a, b) ((a) + (b))

#define FSUB(a, b) ((a) - (b))

VIS_HELPER(helper_fpadd, FADD)

VIS_HELPER(helper_fpsub, FSUB)

#define VIS_CMPHELPER(name, F)                                        \

    void name##16(void)                                           \

    {                                                             \

        vis64 s, d;                                               \

                                                                  \

        s.d = DT0;                                                \

        d.d = DT1;                                                \

                                                                  \

        d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0;       \

        d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0;      \

        d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0;      \

        d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0;      \

                                                                  \

        DT0 = d.d;                                                \

    }                                                             \

                                                                  \

    void name##32(void)                                           \

    {                                                             \

        vis64 s, d;                                               \

                                                                  \

        s.d = DT0;                                                \

        d.d = DT1;                                                \

                                                                  \

        d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0;       \

        d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0;      \

                                                                  \

        DT0 = d.d;                                                \

    }

#define FCMPGT(a, b) ((a) > (b))

#define FCMPEQ(a, b) ((a) == (b))

#define FCMPLE(a, b) ((a) <= (b))

#define FCMPNE(a, b) ((a) != (b))

VIS_CMPHELPER(helper_fcmpgt, FCMPGT)

VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)

VIS_CMPHELPER(helper_fcmple, FCMPLE)

VIS_CMPHELPER(helper_fcmpne, FCMPNE)

#endif

void helper_check_ieee_exceptions(void)

{

    target_ulong status;

    status = get_float_exception_flags(&env->fp_status);

    if (status) {

        /* Copy IEEE 754 flags into FSR */

        if (status & float_flag_invalid)

            env->fsr |= FSR_NVC;

        if (status & float_flag_overflow)

            env->fsr |= FSR_OFC;

        if (status & float_flag_underflow)

            env->fsr |= FSR_UFC;

        if (status & float_flag_divbyzero)

            env->fsr |= FSR_DZC;

        if (status & float_flag_inexact)

            env->fsr |= FSR_NXC;

        if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {

            /* Unmasked exception, generate a trap */

            env->fsr |= FSR_FTT_IEEE_EXCP;

            raise_exception(TT_FP_EXCP);

        } else {

            /* Accumulate exceptions */

            env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;

        }

    }

}

void helper_clear_float_exceptions(void)

{

    set_float_exception_flags(0, &env->fp_status);

}

float32 helper_fabss(float32 src)

{

    return float32_abs(src);

}

#ifdef TARGET_SPARC64

void helper_fabsd(void)

{

    DT0 = float64_abs(DT1);

}

void helper_fabsq(void)

{

    QT0 = float128_abs(QT1);

}

#endif

float32 helper_fsqrts(float32 src)

{

    return float32_sqrt(src, &env->fp_status);

}

void helper_fsqrtd(void)

{

    DT0 = float64_sqrt(DT1, &env->fp_status);

}

void helper_fsqrtq(void)

{

    QT0 = float128_sqrt(QT1, &env->fp_status);

}

#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP)                      \

    void glue(helper_, name) (void)                                     \

    {                                                                   \

        target_ulong new_fsr;                                           \

                                                                        \

        env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                     \

        switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \

        case float_relation_unordered:                                  \

            new_fsr = (FSR_FCC1 | FSR_FCC0) << FS;                      \

            if ((env->fsr & FSR_NVM) || TRAP) {                         \

                env->fsr |= new_fsr;                                    \

                env->fsr |= FSR_NVC;                                    \

                env->fsr |= FSR_FTT_IEEE_EXCP;                          \

                raise_exception(TT_FP_EXCP);                            \

            } else {                                                    \

                env->fsr |= FSR_NVA;                                    \

            }                                                           \

            break;                                                      \

        case float_relation_less:                                       \

            new_fsr = FSR_FCC0 << FS;                                   \

            break;                                                      \

        case float_relation_greater:                                    \

            new_fsr = FSR_FCC1 << FS;                                   \

            break;                                                      \

        default:                                                        \

            new_fsr = 0;                                                \

            break;                                                      \

        }                                                               \

        env->fsr |= new_fsr;                                            \

    }

#define GEN_FCMPS(name, size, FS, TRAP)                                 \

    void glue(helper_, name)(float32 src1, float32 src2)                \

    {                                                                   \

        target_ulong new_fsr;                                           \

                                                                        \

        env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                     \

        switch (glue(size, _compare) (src1, src2, &env->fp_status)) {   \

        case float_relation_unordered:                                  \

            new_fsr = (FSR_FCC1 | FSR_FCC0) << FS;                      \

            if ((env->fsr & FSR_NVM) || TRAP) {                         \

                env->fsr |= new_fsr;                                    \

                env->fsr |= FSR_NVC;                                    \

                env->fsr |= FSR_FTT_IEEE_EXCP;                          \

                raise_exception(TT_FP_EXCP);                            \

            } else {                                                    \

                env->fsr |= FSR_NVA;                                    \

            }                                                           \

            break;                                                      \

        case float_relation_less:                                       \

            new_fsr = FSR_FCC0 << FS;                                   \

            break;                                                      \

        case float_relation_greater:                                    \

            new_fsr = FSR_FCC1 << FS;                                   \

            break;                                                      \

        default:                                                        \

            new_fsr = 0;                                                \

            break;                                                      \

        }                                                               \

        env->fsr |= new_fsr;                                            \

    }

GEN_FCMPS(fcmps, float32, 0, 0);

GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);

GEN_FCMPS(fcmpes, float32, 0, 1);

GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);

GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);

GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);

static uint32_t compute_all_flags(void)

{

    return env->psr & PSR_ICC;

}

static uint32_t compute_C_flags(void)

{

    return env->psr & PSR_CARRY;

}

static inline uint32_t get_NZ_icc(target_ulong dst)

{

    uint32_t ret = 0;

    if (!(dst & 0xffffffffULL))

        ret |= PSR_ZERO;

    if ((int32_t) (dst & 0xffffffffULL) < 0)

        ret |= PSR_NEG;

    return ret;

}

#ifdef TARGET_SPARC64

static uint32_t compute_all_flags_xcc(void)

{

    return env->xcc & PSR_ICC;

}

static uint32_t compute_C_flags_xcc(void)

{

    return env->xcc & PSR_CARRY;

}

static inline uint32_t get_NZ_xcc(target_ulong dst)

{

    uint32_t ret = 0;

    if (!dst)

        ret |= PSR_ZERO;

    if ((int64_t)dst < 0)

        ret |= PSR_NEG;

    return ret;

}

#endif

static inline uint32_t get_V_div_icc(target_ulong src2)