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1 | 3475187d | bellard | /*
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2 | c7ba218d | blueswir1 | * QEMU Sun4u/Sun4v System Emulator
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 18e08a55 | Michael S. Tsirkin | #include "apb_pci.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 87ecb68b | pbrook | #include "nvram.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "net.h" |
31 | 87ecb68b | pbrook | #include "qemu-timer.h" |
32 | 87ecb68b | pbrook | #include "sysemu.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
35 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
36 | 1baffa46 | Blue Swirl | #include "sysbus.h" |
37 | 977e1244 | Gerd Hoffmann | #include "ide.h" |
38 | ca20cf32 | Blue Swirl | #include "loader.h" |
39 | ca20cf32 | Blue Swirl | #include "elf.h" |
40 | 3475187d | bellard | |
41 | 9d926598 | blueswir1 | //#define DEBUG_IRQ
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42 | b430a225 | Blue Swirl | //#define DEBUG_EBUS
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43 | 8f4efc55 | Igor V. Kovalenko | //#define DEBUG_TIMER
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44 | 9d926598 | blueswir1 | |
45 | 9d926598 | blueswir1 | #ifdef DEBUG_IRQ
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46 | b430a225 | Blue Swirl | #define CPUIRQ_DPRINTF(fmt, ...) \
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47 | 001faf32 | Blue Swirl | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
48 | 9d926598 | blueswir1 | #else
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49 | b430a225 | Blue Swirl | #define CPUIRQ_DPRINTF(fmt, ...)
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50 | b430a225 | Blue Swirl | #endif
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51 | b430a225 | Blue Swirl | |
52 | b430a225 | Blue Swirl | #ifdef DEBUG_EBUS
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53 | b430a225 | Blue Swirl | #define EBUS_DPRINTF(fmt, ...) \
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54 | b430a225 | Blue Swirl | do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) |
55 | b430a225 | Blue Swirl | #else
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56 | b430a225 | Blue Swirl | #define EBUS_DPRINTF(fmt, ...)
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57 | 9d926598 | blueswir1 | #endif
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58 | 9d926598 | blueswir1 | |
59 | 8f4efc55 | Igor V. Kovalenko | #ifdef DEBUG_TIMER
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60 | 8f4efc55 | Igor V. Kovalenko | #define TIMER_DPRINTF(fmt, ...) \
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61 | 8f4efc55 | Igor V. Kovalenko | do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) |
62 | 8f4efc55 | Igor V. Kovalenko | #else
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63 | 8f4efc55 | Igor V. Kovalenko | #define TIMER_DPRINTF(fmt, ...)
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64 | 8f4efc55 | Igor V. Kovalenko | #endif
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65 | 8f4efc55 | Igor V. Kovalenko | |
66 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
67 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
68 | 83469015 | bellard | #define INITRD_LOAD_ADDR 0x00300000 |
69 | ac2e9d66 | blueswir1 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
70 | f930d07e | blueswir1 | #define PROM_VADDR 0x000ffd00000ULL |
71 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
72 | f930d07e | blueswir1 | #define APB_MEM_BASE 0x1ff00000000ULL |
73 | f930d07e | blueswir1 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) |
74 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc64" |
75 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
76 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
77 | 3cce6243 | blueswir1 | #define BIOS_CFG_IOPORT 0x510 |
78 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
79 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
80 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
81 | 3475187d | bellard | |
82 | 9d926598 | blueswir1 | #define MAX_PILS 16 |
83 | 9d926598 | blueswir1 | |
84 | 8fa211e8 | blueswir1 | #define TICK_MAX 0x7fffffffffffffffULL |
85 | 8fa211e8 | blueswir1 | |
86 | c7ba218d | blueswir1 | struct hwdef {
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87 | c7ba218d | blueswir1 | const char * const default_cpu_model; |
88 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
89 | e87231d4 | blueswir1 | uint64_t prom_addr; |
90 | e87231d4 | blueswir1 | uint64_t console_serial_base; |
91 | c7ba218d | blueswir1 | }; |
92 | c7ba218d | blueswir1 | |
93 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
94 | 3475187d | bellard | { |
95 | 3475187d | bellard | return 0; |
96 | 3475187d | bellard | } |
97 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
98 | 3475187d | bellard | { |
99 | 3475187d | bellard | return 0; |
100 | 3475187d | bellard | } |
101 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
102 | 3475187d | bellard | { |
103 | 3475187d | bellard | return 0; |
104 | 3475187d | bellard | } |
105 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
106 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
107 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
108 | 3475187d | bellard | void DMA_init (int high_page_enable) {} |
109 | 3475187d | bellard | void DMA_register_channel (int nchan, |
110 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
111 | 3475187d | bellard | void *opaque)
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112 | 3475187d | bellard | { |
113 | 3475187d | bellard | } |
114 | 3475187d | bellard | |
115 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
116 | 81864572 | blueswir1 | { |
117 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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118 | 81864572 | blueswir1 | return 0; |
119 | 81864572 | blueswir1 | } |
120 | 81864572 | blueswir1 | |
121 | 43a34704 | Blue Swirl | static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size, |
122 | 43a34704 | Blue Swirl | const char *arch, ram_addr_t RAM_size, |
123 | 43a34704 | Blue Swirl | const char *boot_devices, |
124 | 43a34704 | Blue Swirl | uint32_t kernel_image, uint32_t kernel_size, |
125 | 43a34704 | Blue Swirl | const char *cmdline, |
126 | 43a34704 | Blue Swirl | uint32_t initrd_image, uint32_t initrd_size, |
127 | 43a34704 | Blue Swirl | uint32_t NVRAM_image, |
128 | 43a34704 | Blue Swirl | int width, int height, int depth, |
129 | 43a34704 | Blue Swirl | const uint8_t *macaddr)
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130 | 83469015 | bellard | { |
131 | 66508601 | blueswir1 | unsigned int i; |
132 | 66508601 | blueswir1 | uint32_t start, end; |
133 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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134 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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135 | d2c63fc1 | blueswir1 | |
136 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
137 | d2c63fc1 | blueswir1 | |
138 | 513f789f | blueswir1 | start = 0;
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139 | 83469015 | bellard | |
140 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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141 | 66508601 | blueswir1 | // Variable partition
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142 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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143 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
144 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
145 | 66508601 | blueswir1 | |
146 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
147 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
148 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
149 | d2c63fc1 | blueswir1 | |
150 | d2c63fc1 | blueswir1 | // End marker
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151 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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152 | 66508601 | blueswir1 | |
153 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
154 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
155 | 66508601 | blueswir1 | |
156 | 66508601 | blueswir1 | // free partition
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157 | 66508601 | blueswir1 | start = end; |
158 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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159 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
160 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
161 | 66508601 | blueswir1 | |
162 | 66508601 | blueswir1 | end = 0x1fd0;
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163 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
164 | d2c63fc1 | blueswir1 | |
165 | 0d31cb99 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
166 | 0d31cb99 | blueswir1 | |
167 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
168 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
169 | 66508601 | blueswir1 | |
170 | 83469015 | bellard | return 0; |
171 | 3475187d | bellard | } |
172 | 636aa70a | Blue Swirl | static unsigned long sun4u_load_kernel(const char *kernel_filename, |
173 | 636aa70a | Blue Swirl | const char *initrd_filename, |
174 | c227f099 | Anthony Liguori | ram_addr_t RAM_size, long *initrd_size)
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175 | 636aa70a | Blue Swirl | { |
176 | 636aa70a | Blue Swirl | int linux_boot;
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177 | 636aa70a | Blue Swirl | unsigned int i; |
178 | 636aa70a | Blue Swirl | long kernel_size;
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179 | 6908d9ce | Blue Swirl | uint8_t *ptr; |
180 | 636aa70a | Blue Swirl | |
181 | 636aa70a | Blue Swirl | linux_boot = (kernel_filename != NULL);
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182 | 636aa70a | Blue Swirl | |
183 | 636aa70a | Blue Swirl | kernel_size = 0;
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184 | 636aa70a | Blue Swirl | if (linux_boot) {
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185 | ca20cf32 | Blue Swirl | int bswap_needed;
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186 | ca20cf32 | Blue Swirl | |
187 | ca20cf32 | Blue Swirl | #ifdef BSWAP_NEEDED
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188 | ca20cf32 | Blue Swirl | bswap_needed = 1;
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189 | ca20cf32 | Blue Swirl | #else
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190 | ca20cf32 | Blue Swirl | bswap_needed = 0;
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191 | ca20cf32 | Blue Swirl | #endif
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192 | ca20cf32 | Blue Swirl | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL, |
193 | ca20cf32 | Blue Swirl | 1, ELF_MACHINE, 0); |
194 | 636aa70a | Blue Swirl | if (kernel_size < 0) |
195 | 636aa70a | Blue Swirl | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
196 | ca20cf32 | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
197 | ca20cf32 | Blue Swirl | TARGET_PAGE_SIZE); |
198 | 636aa70a | Blue Swirl | if (kernel_size < 0) |
199 | 636aa70a | Blue Swirl | kernel_size = load_image_targphys(kernel_filename, |
200 | 636aa70a | Blue Swirl | KERNEL_LOAD_ADDR, |
201 | 636aa70a | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR); |
202 | 636aa70a | Blue Swirl | if (kernel_size < 0) { |
203 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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204 | 636aa70a | Blue Swirl | kernel_filename); |
205 | 636aa70a | Blue Swirl | exit(1);
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206 | 636aa70a | Blue Swirl | } |
207 | 636aa70a | Blue Swirl | |
208 | 636aa70a | Blue Swirl | /* load initrd */
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209 | 636aa70a | Blue Swirl | *initrd_size = 0;
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210 | 636aa70a | Blue Swirl | if (initrd_filename) {
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211 | 636aa70a | Blue Swirl | *initrd_size = load_image_targphys(initrd_filename, |
212 | 636aa70a | Blue Swirl | INITRD_LOAD_ADDR, |
213 | 636aa70a | Blue Swirl | RAM_size - INITRD_LOAD_ADDR); |
214 | 636aa70a | Blue Swirl | if (*initrd_size < 0) { |
215 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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216 | 636aa70a | Blue Swirl | initrd_filename); |
217 | 636aa70a | Blue Swirl | exit(1);
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218 | 636aa70a | Blue Swirl | } |
219 | 636aa70a | Blue Swirl | } |
220 | 636aa70a | Blue Swirl | if (*initrd_size > 0) { |
221 | 636aa70a | Blue Swirl | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
222 | 6908d9ce | Blue Swirl | ptr = rom_ptr(KERNEL_LOAD_ADDR + i); |
223 | 6908d9ce | Blue Swirl | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
224 | 6908d9ce | Blue Swirl | stl_p(ptr + 24, INITRD_LOAD_ADDR + KERNEL_LOAD_ADDR - 0x4000); |
225 | 6908d9ce | Blue Swirl | stl_p(ptr + 28, *initrd_size);
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226 | 636aa70a | Blue Swirl | break;
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227 | 636aa70a | Blue Swirl | } |
228 | 636aa70a | Blue Swirl | } |
229 | 636aa70a | Blue Swirl | } |
230 | 636aa70a | Blue Swirl | } |
231 | 636aa70a | Blue Swirl | return kernel_size;
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232 | 636aa70a | Blue Swirl | } |
233 | 3475187d | bellard | |
234 | b4950060 | blueswir1 | void pic_info(Monitor *mon)
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235 | 3475187d | bellard | { |
236 | 3475187d | bellard | } |
237 | 3475187d | bellard | |
238 | b4950060 | blueswir1 | void irq_info(Monitor *mon)
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239 | 3475187d | bellard | { |
240 | 3475187d | bellard | } |
241 | 3475187d | bellard | |
242 | 9d926598 | blueswir1 | void cpu_check_irqs(CPUState *env)
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243 | 9d926598 | blueswir1 | { |
244 | d532b26c | Igor V. Kovalenko | uint32_t pil = env->pil_in | |
245 | d532b26c | Igor V. Kovalenko | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); |
246 | d532b26c | Igor V. Kovalenko | |
247 | d532b26c | Igor V. Kovalenko | /* check if TM or SM in SOFTINT are set
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248 | d532b26c | Igor V. Kovalenko | setting these also causes interrupt 14 */
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249 | d532b26c | Igor V. Kovalenko | if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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250 | d532b26c | Igor V. Kovalenko | pil |= 1 << 14; |
251 | d532b26c | Igor V. Kovalenko | } |
252 | d532b26c | Igor V. Kovalenko | |
253 | d532b26c | Igor V. Kovalenko | if (!pil) {
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254 | d532b26c | Igor V. Kovalenko | if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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255 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
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256 | d532b26c | Igor V. Kovalenko | env->interrupt_index); |
257 | d532b26c | Igor V. Kovalenko | env->interrupt_index = 0;
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258 | d532b26c | Igor V. Kovalenko | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
259 | d532b26c | Igor V. Kovalenko | } |
260 | d532b26c | Igor V. Kovalenko | return;
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261 | d532b26c | Igor V. Kovalenko | } |
262 | d532b26c | Igor V. Kovalenko | |
263 | d532b26c | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
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264 | 9d926598 | blueswir1 | |
265 | 9d926598 | blueswir1 | unsigned int i; |
266 | 9d926598 | blueswir1 | |
267 | d532b26c | Igor V. Kovalenko | for (i = 15; i > env->psrpil; i--) { |
268 | 9d926598 | blueswir1 | if (pil & (1 << i)) { |
269 | 9d926598 | blueswir1 | int old_interrupt = env->interrupt_index;
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270 | d532b26c | Igor V. Kovalenko | int new_interrupt = TT_EXTINT | i;
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271 | d532b26c | Igor V. Kovalenko | |
272 | d532b26c | Igor V. Kovalenko | if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) { |
273 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
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274 | d532b26c | Igor V. Kovalenko | "current %x >= pending %x\n",
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275 | d532b26c | Igor V. Kovalenko | env->tl, cpu_tsptr(env)->tt, new_interrupt); |
276 | d532b26c | Igor V. Kovalenko | } else if (old_interrupt != new_interrupt) { |
277 | d532b26c | Igor V. Kovalenko | env->interrupt_index = new_interrupt; |
278 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
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279 | d532b26c | Igor V. Kovalenko | old_interrupt, new_interrupt); |
280 | 9d926598 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
281 | 9d926598 | blueswir1 | } |
282 | 9d926598 | blueswir1 | break;
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283 | 9d926598 | blueswir1 | } |
284 | 9d926598 | blueswir1 | } |
285 | d532b26c | Igor V. Kovalenko | } else {
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286 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
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287 | d532b26c | Igor V. Kovalenko | "current interrupt %x\n",
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288 | d532b26c | Igor V. Kovalenko | pil, env->pil_in, env->softint, env->interrupt_index); |
289 | 9d926598 | blueswir1 | } |
290 | 9d926598 | blueswir1 | } |
291 | 9d926598 | blueswir1 | |
292 | 8f4efc55 | Igor V. Kovalenko | static void cpu_kick_irq(CPUState *env) |
293 | 8f4efc55 | Igor V. Kovalenko | { |
294 | 8f4efc55 | Igor V. Kovalenko | env->halted = 0;
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295 | 8f4efc55 | Igor V. Kovalenko | cpu_check_irqs(env); |
296 | 8f4efc55 | Igor V. Kovalenko | } |
297 | 8f4efc55 | Igor V. Kovalenko | |
298 | 9d926598 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
299 | 9d926598 | blueswir1 | { |
300 | 9d926598 | blueswir1 | CPUState *env = opaque; |
301 | 9d926598 | blueswir1 | |
302 | 9d926598 | blueswir1 | if (level) {
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303 | b430a225 | Blue Swirl | CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
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304 | 9d926598 | blueswir1 | env->halted = 0;
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305 | 9d926598 | blueswir1 | env->pil_in |= 1 << irq;
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306 | 9d926598 | blueswir1 | cpu_check_irqs(env); |
307 | 9d926598 | blueswir1 | } else {
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308 | b430a225 | Blue Swirl | CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
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309 | 9d926598 | blueswir1 | env->pil_in &= ~(1 << irq);
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310 | 9d926598 | blueswir1 | cpu_check_irqs(env); |
311 | 9d926598 | blueswir1 | } |
312 | 9d926598 | blueswir1 | } |
313 | 9d926598 | blueswir1 | |
314 | e87231d4 | blueswir1 | typedef struct ResetData { |
315 | e87231d4 | blueswir1 | CPUState *env; |
316 | 44a99354 | Blue Swirl | uint64_t prom_addr; |
317 | e87231d4 | blueswir1 | } ResetData; |
318 | e87231d4 | blueswir1 | |
319 | 8f4efc55 | Igor V. Kovalenko | void cpu_put_timer(QEMUFile *f, CPUTimer *s)
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320 | 8f4efc55 | Igor V. Kovalenko | { |
321 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be32s(f, &s->frequency); |
322 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be32s(f, &s->disabled); |
323 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be64s(f, &s->disabled_mask); |
324 | 8f4efc55 | Igor V. Kovalenko | qemu_put_sbe64s(f, &s->clock_offset); |
325 | 8f4efc55 | Igor V. Kovalenko | |
326 | 8f4efc55 | Igor V. Kovalenko | qemu_put_timer(f, s->qtimer); |
327 | 8f4efc55 | Igor V. Kovalenko | } |
328 | 8f4efc55 | Igor V. Kovalenko | |
329 | 8f4efc55 | Igor V. Kovalenko | void cpu_get_timer(QEMUFile *f, CPUTimer *s)
|
330 | 8f4efc55 | Igor V. Kovalenko | { |
331 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be32s(f, &s->frequency); |
332 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be32s(f, &s->disabled); |
333 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be64s(f, &s->disabled_mask); |
334 | 8f4efc55 | Igor V. Kovalenko | qemu_get_sbe64s(f, &s->clock_offset); |
335 | 8f4efc55 | Igor V. Kovalenko | |
336 | 8f4efc55 | Igor V. Kovalenko | qemu_get_timer(f, s->qtimer); |
337 | 8f4efc55 | Igor V. Kovalenko | } |
338 | 8f4efc55 | Igor V. Kovalenko | |
339 | 8f4efc55 | Igor V. Kovalenko | static CPUTimer* cpu_timer_create(const char* name, CPUState *env, |
340 | 8f4efc55 | Igor V. Kovalenko | QEMUBHFunc *cb, uint32_t frequency, |
341 | 8f4efc55 | Igor V. Kovalenko | uint64_t disabled_mask) |
342 | 8f4efc55 | Igor V. Kovalenko | { |
343 | 8f4efc55 | Igor V. Kovalenko | CPUTimer *timer = qemu_mallocz(sizeof (CPUTimer));
|
344 | 8f4efc55 | Igor V. Kovalenko | |
345 | 8f4efc55 | Igor V. Kovalenko | timer->name = name; |
346 | 8f4efc55 | Igor V. Kovalenko | timer->frequency = frequency; |
347 | 8f4efc55 | Igor V. Kovalenko | timer->disabled_mask = disabled_mask; |
348 | 8f4efc55 | Igor V. Kovalenko | |
349 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = 1;
|
350 | 8f4efc55 | Igor V. Kovalenko | timer->clock_offset = qemu_get_clock(vm_clock); |
351 | 8f4efc55 | Igor V. Kovalenko | |
352 | 8f4efc55 | Igor V. Kovalenko | timer->qtimer = qemu_new_timer(vm_clock, cb, env); |
353 | 8f4efc55 | Igor V. Kovalenko | |
354 | 8f4efc55 | Igor V. Kovalenko | return timer;
|
355 | 8f4efc55 | Igor V. Kovalenko | } |
356 | 8f4efc55 | Igor V. Kovalenko | |
357 | 8f4efc55 | Igor V. Kovalenko | static void cpu_timer_reset(CPUTimer *timer) |
358 | 8f4efc55 | Igor V. Kovalenko | { |
359 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = 1;
|
360 | 8f4efc55 | Igor V. Kovalenko | timer->clock_offset = qemu_get_clock(vm_clock); |
361 | 8f4efc55 | Igor V. Kovalenko | |
362 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
363 | 8f4efc55 | Igor V. Kovalenko | } |
364 | 8f4efc55 | Igor V. Kovalenko | |
365 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
366 | c68ea704 | bellard | { |
367 | e87231d4 | blueswir1 | ResetData *s = (ResetData *)opaque; |
368 | e87231d4 | blueswir1 | CPUState *env = s->env; |
369 | 44a99354 | Blue Swirl | static unsigned int nr_resets; |
370 | 20c9f095 | blueswir1 | |
371 | c68ea704 | bellard | cpu_reset(env); |
372 | 8f4efc55 | Igor V. Kovalenko | |
373 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->tick); |
374 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->stick); |
375 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->hstick); |
376 | 8f4efc55 | Igor V. Kovalenko | |
377 | e87231d4 | blueswir1 | env->gregs[1] = 0; // Memory start |
378 | e87231d4 | blueswir1 | env->gregs[2] = ram_size; // Memory size |
379 | e87231d4 | blueswir1 | env->gregs[3] = 0; // Machine description XXX |
380 | 44a99354 | Blue Swirl | if (nr_resets++ == 0) { |
381 | 44a99354 | Blue Swirl | /* Power on reset */
|
382 | 44a99354 | Blue Swirl | env->pc = s->prom_addr + 0x20ULL;
|
383 | 44a99354 | Blue Swirl | } else {
|
384 | 44a99354 | Blue Swirl | env->pc = s->prom_addr + 0x40ULL;
|
385 | 44a99354 | Blue Swirl | } |
386 | e87231d4 | blueswir1 | env->npc = env->pc + 4;
|
387 | 20c9f095 | blueswir1 | } |
388 | 20c9f095 | blueswir1 | |
389 | 22548760 | blueswir1 | static void tick_irq(void *opaque) |
390 | 20c9f095 | blueswir1 | { |
391 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
392 | 20c9f095 | blueswir1 | |
393 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->tick; |
394 | 8f4efc55 | Igor V. Kovalenko | |
395 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
396 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
|
397 | 8f4efc55 | Igor V. Kovalenko | return;
|
398 | 8f4efc55 | Igor V. Kovalenko | } else {
|
399 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("tick: fire\n");
|
400 | 8fa211e8 | blueswir1 | } |
401 | 8f4efc55 | Igor V. Kovalenko | |
402 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_TIMER; |
403 | 8f4efc55 | Igor V. Kovalenko | cpu_kick_irq(env); |
404 | 20c9f095 | blueswir1 | } |
405 | 20c9f095 | blueswir1 | |
406 | 22548760 | blueswir1 | static void stick_irq(void *opaque) |
407 | 20c9f095 | blueswir1 | { |
408 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
409 | 20c9f095 | blueswir1 | |
410 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->stick; |
411 | 8f4efc55 | Igor V. Kovalenko | |
412 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
413 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
|
414 | 8f4efc55 | Igor V. Kovalenko | return;
|
415 | 8f4efc55 | Igor V. Kovalenko | } else {
|
416 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("stick: fire\n");
|
417 | 8fa211e8 | blueswir1 | } |
418 | 8f4efc55 | Igor V. Kovalenko | |
419 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_STIMER; |
420 | 8f4efc55 | Igor V. Kovalenko | cpu_kick_irq(env); |
421 | 20c9f095 | blueswir1 | } |
422 | 20c9f095 | blueswir1 | |
423 | 22548760 | blueswir1 | static void hstick_irq(void *opaque) |
424 | 20c9f095 | blueswir1 | { |
425 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
426 | 20c9f095 | blueswir1 | |
427 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->hstick; |
428 | 8f4efc55 | Igor V. Kovalenko | |
429 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
430 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
|
431 | 8f4efc55 | Igor V. Kovalenko | return;
|
432 | 8f4efc55 | Igor V. Kovalenko | } else {
|
433 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("hstick: fire\n");
|
434 | 8fa211e8 | blueswir1 | } |
435 | 8f4efc55 | Igor V. Kovalenko | |
436 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_STIMER; |
437 | 8f4efc55 | Igor V. Kovalenko | cpu_kick_irq(env); |
438 | 8f4efc55 | Igor V. Kovalenko | } |
439 | 8f4efc55 | Igor V. Kovalenko | |
440 | 8f4efc55 | Igor V. Kovalenko | static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
|
441 | 8f4efc55 | Igor V. Kovalenko | { |
442 | 8f4efc55 | Igor V. Kovalenko | return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
|
443 | 8f4efc55 | Igor V. Kovalenko | } |
444 | 8f4efc55 | Igor V. Kovalenko | |
445 | 8f4efc55 | Igor V. Kovalenko | static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
|
446 | 8f4efc55 | Igor V. Kovalenko | { |
447 | 8f4efc55 | Igor V. Kovalenko | return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
|
448 | c68ea704 | bellard | } |
449 | c68ea704 | bellard | |
450 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
|
451 | f4b1a842 | blueswir1 | { |
452 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_count = count & ~timer->disabled_mask; |
453 | 8f4efc55 | Igor V. Kovalenko | uint64_t disabled_bit = count & timer->disabled_mask; |
454 | 8f4efc55 | Igor V. Kovalenko | |
455 | 8f4efc55 | Igor V. Kovalenko | int64_t vm_clock_offset = qemu_get_clock(vm_clock) - |
456 | 8f4efc55 | Igor V. Kovalenko | cpu_to_timer_ticks(real_count, timer->frequency); |
457 | 8f4efc55 | Igor V. Kovalenko | |
458 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
|
459 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_count, |
460 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", timer); |
461 | 8f4efc55 | Igor V. Kovalenko | |
462 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = disabled_bit ? 1 : 0; |
463 | 8f4efc55 | Igor V. Kovalenko | timer->clock_offset = vm_clock_offset; |
464 | f4b1a842 | blueswir1 | } |
465 | f4b1a842 | blueswir1 | |
466 | 8f4efc55 | Igor V. Kovalenko | uint64_t cpu_tick_get_count(CPUTimer *timer) |
467 | f4b1a842 | blueswir1 | { |
468 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_count = timer_to_cpu_ticks( |
469 | 8f4efc55 | Igor V. Kovalenko | qemu_get_clock(vm_clock) - timer->clock_offset, |
470 | 8f4efc55 | Igor V. Kovalenko | timer->frequency); |
471 | 8f4efc55 | Igor V. Kovalenko | |
472 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
|
473 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_count, |
474 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", timer); |
475 | 8f4efc55 | Igor V. Kovalenko | |
476 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled)
|
477 | 8f4efc55 | Igor V. Kovalenko | real_count |= timer->disabled_mask; |
478 | 8f4efc55 | Igor V. Kovalenko | |
479 | 8f4efc55 | Igor V. Kovalenko | return real_count;
|
480 | f4b1a842 | blueswir1 | } |
481 | f4b1a842 | blueswir1 | |
482 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
|
483 | f4b1a842 | blueswir1 | { |
484 | 8f4efc55 | Igor V. Kovalenko | int64_t now = qemu_get_clock(vm_clock); |
485 | 8f4efc55 | Igor V. Kovalenko | |
486 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_limit = limit & ~timer->disabled_mask; |
487 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; |
488 | 8f4efc55 | Igor V. Kovalenko | |
489 | 8f4efc55 | Igor V. Kovalenko | int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + |
490 | 8f4efc55 | Igor V. Kovalenko | timer->clock_offset; |
491 | 8f4efc55 | Igor V. Kovalenko | |
492 | 8f4efc55 | Igor V. Kovalenko | if (expires < now) {
|
493 | 8f4efc55 | Igor V. Kovalenko | expires = now + 1;
|
494 | 8f4efc55 | Igor V. Kovalenko | } |
495 | 8f4efc55 | Igor V. Kovalenko | |
496 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
|
497 | 8f4efc55 | Igor V. Kovalenko | "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
|
498 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_limit, |
499 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", |
500 | 8f4efc55 | Igor V. Kovalenko | timer, limit, |
501 | 8f4efc55 | Igor V. Kovalenko | timer_to_cpu_ticks(now - timer->clock_offset, |
502 | 8f4efc55 | Igor V. Kovalenko | timer->frequency), |
503 | 8f4efc55 | Igor V. Kovalenko | timer_to_cpu_ticks(expires - now, timer->frequency)); |
504 | 8f4efc55 | Igor V. Kovalenko | |
505 | 8f4efc55 | Igor V. Kovalenko | if (!real_limit) {
|
506 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
|
507 | 8f4efc55 | Igor V. Kovalenko | timer->name); |
508 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
509 | 8f4efc55 | Igor V. Kovalenko | } else if (timer->disabled) { |
510 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
511 | 8f4efc55 | Igor V. Kovalenko | } else {
|
512 | 8f4efc55 | Igor V. Kovalenko | qemu_mod_timer(timer->qtimer, expires); |
513 | 8f4efc55 | Igor V. Kovalenko | } |
514 | f4b1a842 | blueswir1 | } |
515 | f4b1a842 | blueswir1 | |
516 | c190ea07 | blueswir1 | static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
517 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
518 | c190ea07 | blueswir1 | { |
519 | b430a225 | Blue Swirl | EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n", |
520 | b430a225 | Blue Swirl | region_num, addr); |
521 | c190ea07 | blueswir1 | switch (region_num) {
|
522 | c190ea07 | blueswir1 | case 0: |
523 | c190ea07 | blueswir1 | isa_mmio_init(addr, 0x1000000);
|
524 | c190ea07 | blueswir1 | break;
|
525 | c190ea07 | blueswir1 | case 1: |
526 | c190ea07 | blueswir1 | isa_mmio_init(addr, 0x800000);
|
527 | c190ea07 | blueswir1 | break;
|
528 | c190ea07 | blueswir1 | } |
529 | c190ea07 | blueswir1 | } |
530 | c190ea07 | blueswir1 | |
531 | 1387fe4a | Blue Swirl | static void dummy_isa_irq_handler(void *opaque, int n, int level) |
532 | 1387fe4a | Blue Swirl | { |
533 | 1387fe4a | Blue Swirl | } |
534 | 1387fe4a | Blue Swirl | |
535 | c190ea07 | blueswir1 | /* EBUS (Eight bit bus) bridge */
|
536 | c190ea07 | blueswir1 | static void |
537 | c190ea07 | blueswir1 | pci_ebus_init(PCIBus *bus, int devfn)
|
538 | c190ea07 | blueswir1 | { |
539 | 1387fe4a | Blue Swirl | qemu_irq *isa_irq; |
540 | 1387fe4a | Blue Swirl | |
541 | 53e3c4f9 | Blue Swirl | pci_create_simple(bus, devfn, "ebus");
|
542 | 1387fe4a | Blue Swirl | isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16); |
543 | 1387fe4a | Blue Swirl | isa_bus_irqs(isa_irq); |
544 | 53e3c4f9 | Blue Swirl | } |
545 | c190ea07 | blueswir1 | |
546 | 81a322d4 | Gerd Hoffmann | static int |
547 | 53e3c4f9 | Blue Swirl | pci_ebus_init1(PCIDevice *s) |
548 | 53e3c4f9 | Blue Swirl | { |
549 | 0c5b8d83 | Blue Swirl | isa_bus_new(&s->qdev); |
550 | 0c5b8d83 | Blue Swirl | |
551 | deb54399 | aliguori | pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); |
552 | deb54399 | aliguori | pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS); |
553 | c190ea07 | blueswir1 | s->config[0x04] = 0x06; // command = bus master, pci mem |
554 | c190ea07 | blueswir1 | s->config[0x05] = 0x00; |
555 | c190ea07 | blueswir1 | s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
556 | c190ea07 | blueswir1 | s->config[0x07] = 0x03; // status = medium devsel |
557 | c190ea07 | blueswir1 | s->config[0x08] = 0x01; // revision |
558 | c190ea07 | blueswir1 | s->config[0x09] = 0x00; // programming i/f |
559 | 173a543b | blueswir1 | pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); |
560 | c190ea07 | blueswir1 | s->config[0x0D] = 0x0a; // latency_timer |
561 | 6407f373 | Isaku Yamahata | s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
562 | c190ea07 | blueswir1 | |
563 | 0392a017 | Isaku Yamahata | pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY, |
564 | c190ea07 | blueswir1 | ebus_mmio_mapfunc); |
565 | 0392a017 | Isaku Yamahata | pci_register_bar(s, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_MEMORY, |
566 | c190ea07 | blueswir1 | ebus_mmio_mapfunc); |
567 | 81a322d4 | Gerd Hoffmann | return 0; |
568 | c190ea07 | blueswir1 | } |
569 | c190ea07 | blueswir1 | |
570 | 53e3c4f9 | Blue Swirl | static PCIDeviceInfo ebus_info = {
|
571 | 53e3c4f9 | Blue Swirl | .qdev.name = "ebus",
|
572 | 53e3c4f9 | Blue Swirl | .qdev.size = sizeof(PCIDevice),
|
573 | 53e3c4f9 | Blue Swirl | .init = pci_ebus_init1, |
574 | 53e3c4f9 | Blue Swirl | }; |
575 | 53e3c4f9 | Blue Swirl | |
576 | 53e3c4f9 | Blue Swirl | static void pci_ebus_register(void) |
577 | 53e3c4f9 | Blue Swirl | { |
578 | 53e3c4f9 | Blue Swirl | pci_qdev_register(&ebus_info); |
579 | 53e3c4f9 | Blue Swirl | } |
580 | 53e3c4f9 | Blue Swirl | |
581 | 53e3c4f9 | Blue Swirl | device_init(pci_ebus_register); |
582 | 53e3c4f9 | Blue Swirl | |
583 | 1baffa46 | Blue Swirl | /* Boot PROM (OpenBIOS) */
|
584 | c227f099 | Anthony Liguori | static void prom_init(target_phys_addr_t addr, const char *bios_name) |
585 | 1baffa46 | Blue Swirl | { |
586 | 1baffa46 | Blue Swirl | DeviceState *dev; |
587 | 1baffa46 | Blue Swirl | SysBusDevice *s; |
588 | 1baffa46 | Blue Swirl | char *filename;
|
589 | 1baffa46 | Blue Swirl | int ret;
|
590 | 1baffa46 | Blue Swirl | |
591 | 1baffa46 | Blue Swirl | dev = qdev_create(NULL, "openprom"); |
592 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
593 | 1baffa46 | Blue Swirl | s = sysbus_from_qdev(dev); |
594 | 1baffa46 | Blue Swirl | |
595 | 1baffa46 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
596 | 1baffa46 | Blue Swirl | |
597 | 1baffa46 | Blue Swirl | /* load boot prom */
|
598 | 1baffa46 | Blue Swirl | if (bios_name == NULL) { |
599 | 1baffa46 | Blue Swirl | bios_name = PROM_FILENAME; |
600 | 1baffa46 | Blue Swirl | } |
601 | 1baffa46 | Blue Swirl | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
602 | 1baffa46 | Blue Swirl | if (filename) {
|
603 | ca20cf32 | Blue Swirl | ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL, |
604 | ca20cf32 | Blue Swirl | 1, ELF_MACHINE, 0); |
605 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
606 | 1baffa46 | Blue Swirl | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
607 | 1baffa46 | Blue Swirl | } |
608 | 1baffa46 | Blue Swirl | qemu_free(filename); |
609 | 1baffa46 | Blue Swirl | } else {
|
610 | 1baffa46 | Blue Swirl | ret = -1;
|
611 | 1baffa46 | Blue Swirl | } |
612 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
613 | 1baffa46 | Blue Swirl | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
614 | 1baffa46 | Blue Swirl | exit(1);
|
615 | 1baffa46 | Blue Swirl | } |
616 | 1baffa46 | Blue Swirl | } |
617 | 1baffa46 | Blue Swirl | |
618 | 81a322d4 | Gerd Hoffmann | static int prom_init1(SysBusDevice *dev) |
619 | 1baffa46 | Blue Swirl | { |
620 | c227f099 | Anthony Liguori | ram_addr_t prom_offset; |
621 | 1baffa46 | Blue Swirl | |
622 | 1baffa46 | Blue Swirl | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
623 | 1baffa46 | Blue Swirl | sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); |
624 | 81a322d4 | Gerd Hoffmann | return 0; |
625 | 1baffa46 | Blue Swirl | } |
626 | 1baffa46 | Blue Swirl | |
627 | 1baffa46 | Blue Swirl | static SysBusDeviceInfo prom_info = {
|
628 | 1baffa46 | Blue Swirl | .init = prom_init1, |
629 | 1baffa46 | Blue Swirl | .qdev.name = "openprom",
|
630 | 1baffa46 | Blue Swirl | .qdev.size = sizeof(SysBusDevice),
|
631 | 1baffa46 | Blue Swirl | .qdev.props = (Property[]) { |
632 | 1baffa46 | Blue Swirl | {/* end of property list */}
|
633 | 1baffa46 | Blue Swirl | } |
634 | 1baffa46 | Blue Swirl | }; |
635 | 1baffa46 | Blue Swirl | |
636 | 1baffa46 | Blue Swirl | static void prom_register_devices(void) |
637 | 1baffa46 | Blue Swirl | { |
638 | 1baffa46 | Blue Swirl | sysbus_register_withprop(&prom_info); |
639 | 1baffa46 | Blue Swirl | } |
640 | 1baffa46 | Blue Swirl | |
641 | 1baffa46 | Blue Swirl | device_init(prom_register_devices); |
642 | 1baffa46 | Blue Swirl | |
643 | bda42033 | Blue Swirl | |
644 | bda42033 | Blue Swirl | typedef struct RamDevice |
645 | bda42033 | Blue Swirl | { |
646 | bda42033 | Blue Swirl | SysBusDevice busdev; |
647 | 04843626 | Blue Swirl | uint64_t size; |
648 | bda42033 | Blue Swirl | } RamDevice; |
649 | bda42033 | Blue Swirl | |
650 | bda42033 | Blue Swirl | /* System RAM */
|
651 | 81a322d4 | Gerd Hoffmann | static int ram_init1(SysBusDevice *dev) |
652 | bda42033 | Blue Swirl | { |
653 | c227f099 | Anthony Liguori | ram_addr_t RAM_size, ram_offset; |
654 | bda42033 | Blue Swirl | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
655 | bda42033 | Blue Swirl | |
656 | bda42033 | Blue Swirl | RAM_size = d->size; |
657 | bda42033 | Blue Swirl | |
658 | bda42033 | Blue Swirl | ram_offset = qemu_ram_alloc(RAM_size); |
659 | bda42033 | Blue Swirl | sysbus_init_mmio(dev, RAM_size, ram_offset); |
660 | 81a322d4 | Gerd Hoffmann | return 0; |
661 | bda42033 | Blue Swirl | } |
662 | bda42033 | Blue Swirl | |
663 | c227f099 | Anthony Liguori | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) |
664 | bda42033 | Blue Swirl | { |
665 | bda42033 | Blue Swirl | DeviceState *dev; |
666 | bda42033 | Blue Swirl | SysBusDevice *s; |
667 | bda42033 | Blue Swirl | RamDevice *d; |
668 | bda42033 | Blue Swirl | |
669 | bda42033 | Blue Swirl | /* allocate RAM */
|
670 | bda42033 | Blue Swirl | dev = qdev_create(NULL, "memory"); |
671 | bda42033 | Blue Swirl | s = sysbus_from_qdev(dev); |
672 | bda42033 | Blue Swirl | |
673 | bda42033 | Blue Swirl | d = FROM_SYSBUS(RamDevice, s); |
674 | bda42033 | Blue Swirl | d->size = RAM_size; |
675 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
676 | bda42033 | Blue Swirl | |
677 | bda42033 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
678 | bda42033 | Blue Swirl | } |
679 | bda42033 | Blue Swirl | |
680 | bda42033 | Blue Swirl | static SysBusDeviceInfo ram_info = {
|
681 | bda42033 | Blue Swirl | .init = ram_init1, |
682 | bda42033 | Blue Swirl | .qdev.name = "memory",
|
683 | bda42033 | Blue Swirl | .qdev.size = sizeof(RamDevice),
|
684 | bda42033 | Blue Swirl | .qdev.props = (Property[]) { |
685 | 32a7ee98 | Gerd Hoffmann | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
686 | 32a7ee98 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
687 | bda42033 | Blue Swirl | } |
688 | bda42033 | Blue Swirl | }; |
689 | bda42033 | Blue Swirl | |
690 | bda42033 | Blue Swirl | static void ram_register_devices(void) |
691 | bda42033 | Blue Swirl | { |
692 | bda42033 | Blue Swirl | sysbus_register_withprop(&ram_info); |
693 | bda42033 | Blue Swirl | } |
694 | bda42033 | Blue Swirl | |
695 | bda42033 | Blue Swirl | device_init(ram_register_devices); |
696 | bda42033 | Blue Swirl | |
697 | 7b833f5b | Blue Swirl | static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
698 | 3475187d | bellard | { |
699 | c68ea704 | bellard | CPUState *env; |
700 | e87231d4 | blueswir1 | ResetData *reset_info; |
701 | 3475187d | bellard | |
702 | 8f4efc55 | Igor V. Kovalenko | uint32_t tick_frequency = 100*1000000; |
703 | 8f4efc55 | Igor V. Kovalenko | uint32_t stick_frequency = 100*1000000; |
704 | 8f4efc55 | Igor V. Kovalenko | uint32_t hstick_frequency = 100*1000000; |
705 | 8f4efc55 | Igor V. Kovalenko | |
706 | c7ba218d | blueswir1 | if (!cpu_model)
|
707 | c7ba218d | blueswir1 | cpu_model = hwdef->default_cpu_model; |
708 | aaed909a | bellard | env = cpu_init(cpu_model); |
709 | aaed909a | bellard | if (!env) {
|
710 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
711 | 62724a37 | blueswir1 | exit(1);
|
712 | 62724a37 | blueswir1 | } |
713 | 20c9f095 | blueswir1 | |
714 | 8f4efc55 | Igor V. Kovalenko | env->tick = cpu_timer_create("tick", env, tick_irq,
|
715 | 8f4efc55 | Igor V. Kovalenko | tick_frequency, TICK_NPT_MASK); |
716 | 8f4efc55 | Igor V. Kovalenko | |
717 | 8f4efc55 | Igor V. Kovalenko | env->stick = cpu_timer_create("stick", env, stick_irq,
|
718 | 8f4efc55 | Igor V. Kovalenko | stick_frequency, TICK_INT_DIS); |
719 | 20c9f095 | blueswir1 | |
720 | 8f4efc55 | Igor V. Kovalenko | env->hstick = cpu_timer_create("hstick", env, hstick_irq,
|
721 | 8f4efc55 | Igor V. Kovalenko | hstick_frequency, TICK_INT_DIS); |
722 | e87231d4 | blueswir1 | |
723 | e87231d4 | blueswir1 | reset_info = qemu_mallocz(sizeof(ResetData));
|
724 | e87231d4 | blueswir1 | reset_info->env = env; |
725 | 44a99354 | Blue Swirl | reset_info->prom_addr = hwdef->prom_addr; |
726 | a08d4367 | Jan Kiszka | qemu_register_reset(main_cpu_reset, reset_info); |
727 | c68ea704 | bellard | |
728 | 7b833f5b | Blue Swirl | return env;
|
729 | 7b833f5b | Blue Swirl | } |
730 | 7b833f5b | Blue Swirl | |
731 | c227f099 | Anthony Liguori | static void sun4uv_init(ram_addr_t RAM_size, |
732 | 7b833f5b | Blue Swirl | const char *boot_devices, |
733 | 7b833f5b | Blue Swirl | const char *kernel_filename, const char *kernel_cmdline, |
734 | 7b833f5b | Blue Swirl | const char *initrd_filename, const char *cpu_model, |
735 | 7b833f5b | Blue Swirl | const struct hwdef *hwdef) |
736 | 7b833f5b | Blue Swirl | { |
737 | 7b833f5b | Blue Swirl | CPUState *env; |
738 | 43a34704 | Blue Swirl | M48t59State *nvram; |
739 | 7b833f5b | Blue Swirl | unsigned int i; |
740 | 7b833f5b | Blue Swirl | long initrd_size, kernel_size;
|
741 | 7b833f5b | Blue Swirl | PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
742 | 7b833f5b | Blue Swirl | qemu_irq *irq; |
743 | f455e98c | Gerd Hoffmann | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
744 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
745 | 7b833f5b | Blue Swirl | void *fw_cfg;
|
746 | 7b833f5b | Blue Swirl | |
747 | 7b833f5b | Blue Swirl | /* init CPUs */
|
748 | 7b833f5b | Blue Swirl | env = cpu_devinit(cpu_model, hwdef); |
749 | 7b833f5b | Blue Swirl | |
750 | bda42033 | Blue Swirl | /* set up devices */
|
751 | bda42033 | Blue Swirl | ram_init(0, RAM_size);
|
752 | 3475187d | bellard | |
753 | 1baffa46 | Blue Swirl | prom_init(hwdef->prom_addr, bios_name); |
754 | 3475187d | bellard | |
755 | 7d55273f | Igor Kovalenko | |
756 | 7d55273f | Igor Kovalenko | irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
757 | 7d55273f | Igor Kovalenko | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2, |
758 | c190ea07 | blueswir1 | &pci_bus3); |
759 | 83469015 | bellard | isa_mem_base = VGA_BASE; |
760 | fbe1b595 | Paul Brook | pci_vga_init(pci_bus, 0, 0); |
761 | 83469015 | bellard | |
762 | c190ea07 | blueswir1 | // XXX Should be pci_bus3
|
763 | c190ea07 | blueswir1 | pci_ebus_init(pci_bus, -1);
|
764 | c190ea07 | blueswir1 | |
765 | e87231d4 | blueswir1 | i = 0;
|
766 | e87231d4 | blueswir1 | if (hwdef->console_serial_base) {
|
767 | e87231d4 | blueswir1 | serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, |
768 | e87231d4 | blueswir1 | serial_hds[i], 1);
|
769 | e87231d4 | blueswir1 | i++; |
770 | e87231d4 | blueswir1 | } |
771 | e87231d4 | blueswir1 | for(; i < MAX_SERIAL_PORTS; i++) {
|
772 | 83469015 | bellard | if (serial_hds[i]) {
|
773 | ac0be998 | Gerd Hoffmann | serial_isa_init(i, serial_hds[i]); |
774 | 83469015 | bellard | } |
775 | 83469015 | bellard | } |
776 | 83469015 | bellard | |
777 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
778 | 83469015 | bellard | if (parallel_hds[i]) {
|
779 | 021f0674 | Gerd Hoffmann | parallel_init(i, parallel_hds[i]); |
780 | 83469015 | bellard | } |
781 | 83469015 | bellard | } |
782 | 83469015 | bellard | |
783 | cb457d76 | aliguori | for(i = 0; i < nb_nics; i++) |
784 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
785 | 83469015 | bellard | |
786 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
787 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
788 | e4bcb14c | ths | exit(1);
|
789 | e4bcb14c | ths | } |
790 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
791 | f455e98c | Gerd Hoffmann | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, |
792 | 751c6a17 | Gerd Hoffmann | i % MAX_IDE_DEVS); |
793 | e4bcb14c | ths | } |
794 | e4bcb14c | ths | |
795 | 3b898dda | blueswir1 | pci_cmd646_ide_init(pci_bus, hd, 1);
|
796 | 3b898dda | blueswir1 | |
797 | 2e15e23b | Gerd Hoffmann | isa_create_simple("i8042");
|
798 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
799 | fd8014e1 | Gerd Hoffmann | fd[i] = drive_get(IF_FLOPPY, 0, i);
|
800 | e4bcb14c | ths | } |
801 | 86c86157 | Gerd Hoffmann | fdctrl_init_isa(fd); |
802 | f80237d4 | Blue Swirl | nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59); |
803 | 636aa70a | Blue Swirl | |
804 | 636aa70a | Blue Swirl | initrd_size = 0;
|
805 | 636aa70a | Blue Swirl | kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, |
806 | 636aa70a | Blue Swirl | ram_size, &initrd_size); |
807 | 636aa70a | Blue Swirl | |
808 | 22548760 | blueswir1 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
809 | 0d31cb99 | blueswir1 | KERNEL_LOAD_ADDR, kernel_size, |
810 | 0d31cb99 | blueswir1 | kernel_cmdline, |
811 | 0d31cb99 | blueswir1 | INITRD_LOAD_ADDR, initrd_size, |
812 | 0d31cb99 | blueswir1 | /* XXX: need an option to load a NVRAM image */
|
813 | 0d31cb99 | blueswir1 | 0,
|
814 | 0d31cb99 | blueswir1 | graphic_width, graphic_height, graphic_depth, |
815 | 0d31cb99 | blueswir1 | (uint8_t *)&nd_table[0].macaddr);
|
816 | 83469015 | bellard | |
817 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
818 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
819 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
820 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
821 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
822 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
823 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
824 | 9c9b0512 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
825 | 9c9b0512 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
826 | 6bb4ca57 | Blue Swirl | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
827 | 6bb4ca57 | Blue Swirl | (uint8_t*)strdup(kernel_cmdline), |
828 | 6bb4ca57 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
829 | 513f789f | blueswir1 | } else {
|
830 | 9c9b0512 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
831 | 513f789f | blueswir1 | } |
832 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
833 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
834 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
|
835 | 7589690c | Blue Swirl | |
836 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); |
837 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); |
838 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); |
839 | 7589690c | Blue Swirl | |
840 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
841 | 3475187d | bellard | } |
842 | 3475187d | bellard | |
843 | 905fdcb5 | blueswir1 | enum {
|
844 | 905fdcb5 | blueswir1 | sun4u_id = 0,
|
845 | 905fdcb5 | blueswir1 | sun4v_id = 64,
|
846 | e87231d4 | blueswir1 | niagara_id, |
847 | 905fdcb5 | blueswir1 | }; |
848 | 905fdcb5 | blueswir1 | |
849 | c7ba218d | blueswir1 | static const struct hwdef hwdefs[] = { |
850 | c7ba218d | blueswir1 | /* Sun4u generic PC-like machine */
|
851 | c7ba218d | blueswir1 | { |
852 | c7ba218d | blueswir1 | .default_cpu_model = "TI UltraSparc II",
|
853 | 905fdcb5 | blueswir1 | .machine_id = sun4u_id, |
854 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
855 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
856 | c7ba218d | blueswir1 | }, |
857 | c7ba218d | blueswir1 | /* Sun4v generic PC-like machine */
|
858 | c7ba218d | blueswir1 | { |
859 | c7ba218d | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
860 | 905fdcb5 | blueswir1 | .machine_id = sun4v_id, |
861 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
862 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
863 | e87231d4 | blueswir1 | }, |
864 | e87231d4 | blueswir1 | /* Sun4v generic Niagara machine */
|
865 | e87231d4 | blueswir1 | { |
866 | e87231d4 | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
867 | e87231d4 | blueswir1 | .machine_id = niagara_id, |
868 | e87231d4 | blueswir1 | .prom_addr = 0xfff0000000ULL,
|
869 | e87231d4 | blueswir1 | .console_serial_base = 0xfff0c2c000ULL,
|
870 | c7ba218d | blueswir1 | }, |
871 | c7ba218d | blueswir1 | }; |
872 | c7ba218d | blueswir1 | |
873 | c7ba218d | blueswir1 | /* Sun4u hardware initialisation */
|
874 | c227f099 | Anthony Liguori | static void sun4u_init(ram_addr_t RAM_size, |
875 | 3023f332 | aliguori | const char *boot_devices, |
876 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
877 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
878 | c7ba218d | blueswir1 | { |
879 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
880 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
881 | c7ba218d | blueswir1 | } |
882 | c7ba218d | blueswir1 | |
883 | c7ba218d | blueswir1 | /* Sun4v hardware initialisation */
|
884 | c227f099 | Anthony Liguori | static void sun4v_init(ram_addr_t RAM_size, |
885 | 3023f332 | aliguori | const char *boot_devices, |
886 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
887 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
888 | c7ba218d | blueswir1 | { |
889 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
890 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
891 | c7ba218d | blueswir1 | } |
892 | c7ba218d | blueswir1 | |
893 | e87231d4 | blueswir1 | /* Niagara hardware initialisation */
|
894 | c227f099 | Anthony Liguori | static void niagara_init(ram_addr_t RAM_size, |
895 | 3023f332 | aliguori | const char *boot_devices, |
896 | e87231d4 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
897 | e87231d4 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
898 | e87231d4 | blueswir1 | { |
899 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
900 | e87231d4 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
901 | e87231d4 | blueswir1 | } |
902 | e87231d4 | blueswir1 | |
903 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4u_machine = {
|
904 | 66de733b | blueswir1 | .name = "sun4u",
|
905 | 66de733b | blueswir1 | .desc = "Sun4u platform",
|
906 | 66de733b | blueswir1 | .init = sun4u_init, |
907 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
908 | 0c257437 | Anthony Liguori | .is_default = 1,
|
909 | 3475187d | bellard | }; |
910 | c7ba218d | blueswir1 | |
911 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4v_machine = {
|
912 | 66de733b | blueswir1 | .name = "sun4v",
|
913 | 66de733b | blueswir1 | .desc = "Sun4v platform",
|
914 | 66de733b | blueswir1 | .init = sun4v_init, |
915 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
916 | c7ba218d | blueswir1 | }; |
917 | e87231d4 | blueswir1 | |
918 | f80f9ec9 | Anthony Liguori | static QEMUMachine niagara_machine = {
|
919 | e87231d4 | blueswir1 | .name = "Niagara",
|
920 | e87231d4 | blueswir1 | .desc = "Sun4v platform, Niagara",
|
921 | e87231d4 | blueswir1 | .init = niagara_init, |
922 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
923 | e87231d4 | blueswir1 | }; |
924 | f80f9ec9 | Anthony Liguori | |
925 | f80f9ec9 | Anthony Liguori | static void sun4u_machine_init(void) |
926 | f80f9ec9 | Anthony Liguori | { |
927 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4u_machine); |
928 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4v_machine); |
929 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&niagara_machine); |
930 | f80f9ec9 | Anthony Liguori | } |
931 | f80f9ec9 | Anthony Liguori | |
932 | f80f9ec9 | Anthony Liguori | machine_init(sun4u_machine_init); |