root / tcg / tcg-op.h @ 3d575329
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1 | c896fe29 | bellard | /*
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2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
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3 | c896fe29 | bellard | *
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4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
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5 | c896fe29 | bellard | *
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6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
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9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
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12 | c896fe29 | bellard | *
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13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
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15 | c896fe29 | bellard | *
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16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | c896fe29 | bellard | * THE SOFTWARE.
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23 | c896fe29 | bellard | */
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24 | c896fe29 | bellard | #include "tcg.h" |
25 | c896fe29 | bellard | |
26 | c896fe29 | bellard | /* legacy dyngen operations */
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27 | c896fe29 | bellard | #include "gen-op.h" |
28 | c896fe29 | bellard | |
29 | c896fe29 | bellard | int gen_new_label(void); |
30 | c896fe29 | bellard | |
31 | c896fe29 | bellard | static inline void tcg_gen_op1(int opc, TCGArg arg1) |
32 | c896fe29 | bellard | { |
33 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
34 | c896fe29 | bellard | *gen_opparam_ptr++ = arg1; |
35 | c896fe29 | bellard | } |
36 | c896fe29 | bellard | |
37 | c896fe29 | bellard | static inline void tcg_gen_op2(int opc, TCGArg arg1, TCGArg arg2) |
38 | c896fe29 | bellard | { |
39 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
40 | c896fe29 | bellard | *gen_opparam_ptr++ = arg1; |
41 | c896fe29 | bellard | *gen_opparam_ptr++ = arg2; |
42 | c896fe29 | bellard | } |
43 | c896fe29 | bellard | |
44 | c896fe29 | bellard | static inline void tcg_gen_op3(int opc, TCGArg arg1, TCGArg arg2, TCGArg arg3) |
45 | c896fe29 | bellard | { |
46 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
47 | c896fe29 | bellard | *gen_opparam_ptr++ = arg1; |
48 | c896fe29 | bellard | *gen_opparam_ptr++ = arg2; |
49 | c896fe29 | bellard | *gen_opparam_ptr++ = arg3; |
50 | c896fe29 | bellard | } |
51 | c896fe29 | bellard | |
52 | c896fe29 | bellard | static inline void tcg_gen_op4(int opc, TCGArg arg1, TCGArg arg2, TCGArg arg3, |
53 | c896fe29 | bellard | TCGArg arg4) |
54 | c896fe29 | bellard | { |
55 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
56 | c896fe29 | bellard | *gen_opparam_ptr++ = arg1; |
57 | c896fe29 | bellard | *gen_opparam_ptr++ = arg2; |
58 | c896fe29 | bellard | *gen_opparam_ptr++ = arg3; |
59 | c896fe29 | bellard | *gen_opparam_ptr++ = arg4; |
60 | c896fe29 | bellard | } |
61 | c896fe29 | bellard | |
62 | c896fe29 | bellard | static inline void tcg_gen_op5(int opc, TCGArg arg1, TCGArg arg2, |
63 | c896fe29 | bellard | TCGArg arg3, TCGArg arg4, |
64 | c896fe29 | bellard | TCGArg arg5) |
65 | c896fe29 | bellard | { |
66 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
67 | c896fe29 | bellard | *gen_opparam_ptr++ = arg1; |
68 | c896fe29 | bellard | *gen_opparam_ptr++ = arg2; |
69 | c896fe29 | bellard | *gen_opparam_ptr++ = arg3; |
70 | c896fe29 | bellard | *gen_opparam_ptr++ = arg4; |
71 | c896fe29 | bellard | *gen_opparam_ptr++ = arg5; |
72 | c896fe29 | bellard | } |
73 | c896fe29 | bellard | |
74 | c896fe29 | bellard | static inline void tcg_gen_op6(int opc, TCGArg arg1, TCGArg arg2, |
75 | c896fe29 | bellard | TCGArg arg3, TCGArg arg4, |
76 | c896fe29 | bellard | TCGArg arg5, TCGArg arg6) |
77 | c896fe29 | bellard | { |
78 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
79 | c896fe29 | bellard | *gen_opparam_ptr++ = arg1; |
80 | c896fe29 | bellard | *gen_opparam_ptr++ = arg2; |
81 | c896fe29 | bellard | *gen_opparam_ptr++ = arg3; |
82 | c896fe29 | bellard | *gen_opparam_ptr++ = arg4; |
83 | c896fe29 | bellard | *gen_opparam_ptr++ = arg5; |
84 | c896fe29 | bellard | *gen_opparam_ptr++ = arg6; |
85 | c896fe29 | bellard | } |
86 | c896fe29 | bellard | |
87 | c896fe29 | bellard | static inline void gen_set_label(int n) |
88 | c896fe29 | bellard | { |
89 | c896fe29 | bellard | tcg_gen_op1(INDEX_op_set_label, n); |
90 | c896fe29 | bellard | } |
91 | c896fe29 | bellard | |
92 | c896fe29 | bellard | static inline void tcg_gen_mov_i32(int ret, int arg) |
93 | c896fe29 | bellard | { |
94 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_mov_i32, ret, arg); |
95 | c896fe29 | bellard | } |
96 | c896fe29 | bellard | |
97 | c896fe29 | bellard | static inline void tcg_gen_movi_i32(int ret, int32_t arg) |
98 | c896fe29 | bellard | { |
99 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_movi_i32, ret, arg); |
100 | c896fe29 | bellard | } |
101 | c896fe29 | bellard | |
102 | c896fe29 | bellard | /* helper calls */
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103 | c896fe29 | bellard | #define TCG_HELPER_CALL_FLAGS 0 |
104 | c896fe29 | bellard | |
105 | c896fe29 | bellard | static inline void tcg_gen_helper_0_0(void *func) |
106 | c896fe29 | bellard | { |
107 | c896fe29 | bellard | tcg_gen_call(&tcg_ctx, |
108 | c896fe29 | bellard | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
109 | c896fe29 | bellard | 0, NULL, 0, NULL); |
110 | c896fe29 | bellard | } |
111 | c896fe29 | bellard | |
112 | c896fe29 | bellard | static inline void tcg_gen_helper_0_1(void *func, TCGArg arg) |
113 | c896fe29 | bellard | { |
114 | c896fe29 | bellard | tcg_gen_call(&tcg_ctx, |
115 | c896fe29 | bellard | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
116 | c896fe29 | bellard | 0, NULL, 1, &arg); |
117 | c896fe29 | bellard | } |
118 | c896fe29 | bellard | |
119 | c896fe29 | bellard | static inline void tcg_gen_helper_0_2(void *func, TCGArg arg1, TCGArg arg2) |
120 | c896fe29 | bellard | { |
121 | c896fe29 | bellard | TCGArg args[2];
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122 | c896fe29 | bellard | args[0] = arg1;
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123 | c896fe29 | bellard | args[1] = arg2;
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124 | c896fe29 | bellard | tcg_gen_call(&tcg_ctx, |
125 | c896fe29 | bellard | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
126 | c896fe29 | bellard | 0, NULL, 2, args); |
127 | c896fe29 | bellard | } |
128 | c896fe29 | bellard | |
129 | c896fe29 | bellard | static inline void tcg_gen_helper_1_2(void *func, TCGArg ret, |
130 | c896fe29 | bellard | TCGArg arg1, TCGArg arg2) |
131 | c896fe29 | bellard | { |
132 | c896fe29 | bellard | TCGArg args[2];
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133 | c896fe29 | bellard | args[0] = arg1;
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134 | c896fe29 | bellard | args[1] = arg2;
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135 | c896fe29 | bellard | tcg_gen_call(&tcg_ctx, |
136 | c896fe29 | bellard | tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
137 | c896fe29 | bellard | 1, &ret, 2, args); |
138 | c896fe29 | bellard | } |
139 | c896fe29 | bellard | |
140 | c896fe29 | bellard | /* 32 bit ops */
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141 | c896fe29 | bellard | |
142 | c896fe29 | bellard | static inline void tcg_gen_ld8u_i32(int ret, int arg2, tcg_target_long offset) |
143 | c896fe29 | bellard | { |
144 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_ld8u_i32, ret, arg2, offset); |
145 | c896fe29 | bellard | } |
146 | c896fe29 | bellard | |
147 | c896fe29 | bellard | static inline void tcg_gen_ld8s_i32(int ret, int arg2, tcg_target_long offset) |
148 | c896fe29 | bellard | { |
149 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_ld8s_i32, ret, arg2, offset); |
150 | c896fe29 | bellard | } |
151 | c896fe29 | bellard | |
152 | c896fe29 | bellard | static inline void tcg_gen_ld16u_i32(int ret, int arg2, tcg_target_long offset) |
153 | c896fe29 | bellard | { |
154 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_ld16u_i32, ret, arg2, offset); |
155 | c896fe29 | bellard | } |
156 | c896fe29 | bellard | |
157 | c896fe29 | bellard | static inline void tcg_gen_ld16s_i32(int ret, int arg2, tcg_target_long offset) |
158 | c896fe29 | bellard | { |
159 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_ld16s_i32, ret, arg2, offset); |
160 | c896fe29 | bellard | } |
161 | c896fe29 | bellard | |
162 | c896fe29 | bellard | static inline void tcg_gen_ld_i32(int ret, int arg2, tcg_target_long offset) |
163 | c896fe29 | bellard | { |
164 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_ld_i32, ret, arg2, offset); |
165 | c896fe29 | bellard | } |
166 | c896fe29 | bellard | |
167 | c896fe29 | bellard | static inline void tcg_gen_st8_i32(int arg1, int arg2, tcg_target_long offset) |
168 | c896fe29 | bellard | { |
169 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_st8_i32, arg1, arg2, offset); |
170 | c896fe29 | bellard | } |
171 | c896fe29 | bellard | |
172 | c896fe29 | bellard | static inline void tcg_gen_st16_i32(int arg1, int arg2, tcg_target_long offset) |
173 | c896fe29 | bellard | { |
174 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_st16_i32, arg1, arg2, offset); |
175 | c896fe29 | bellard | } |
176 | c896fe29 | bellard | |
177 | c896fe29 | bellard | static inline void tcg_gen_st_i32(int arg1, int arg2, tcg_target_long offset) |
178 | c896fe29 | bellard | { |
179 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_st_i32, arg1, arg2, offset); |
180 | c896fe29 | bellard | } |
181 | c896fe29 | bellard | |
182 | c896fe29 | bellard | static inline void tcg_gen_add_i32(int ret, int arg1, int arg2) |
183 | c896fe29 | bellard | { |
184 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_add_i32, ret, arg1, arg2); |
185 | c896fe29 | bellard | } |
186 | c896fe29 | bellard | |
187 | c896fe29 | bellard | static inline void tcg_gen_addi_i32(int ret, int arg1, int32_t arg2) |
188 | c896fe29 | bellard | { |
189 | c896fe29 | bellard | tcg_gen_add_i32(ret, arg1, tcg_const_i32(arg2)); |
190 | c896fe29 | bellard | } |
191 | c896fe29 | bellard | |
192 | c896fe29 | bellard | static inline void tcg_gen_sub_i32(int ret, int arg1, int arg2) |
193 | c896fe29 | bellard | { |
194 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_sub_i32, ret, arg1, arg2); |
195 | c896fe29 | bellard | } |
196 | c896fe29 | bellard | |
197 | c896fe29 | bellard | static inline void tcg_gen_subi_i32(int ret, int arg1, int32_t arg2) |
198 | c896fe29 | bellard | { |
199 | c896fe29 | bellard | tcg_gen_sub_i32(ret, arg1, tcg_const_i32(arg2)); |
200 | c896fe29 | bellard | } |
201 | c896fe29 | bellard | |
202 | c896fe29 | bellard | static inline void tcg_gen_and_i32(int ret, int arg1, int arg2) |
203 | c896fe29 | bellard | { |
204 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_and_i32, ret, arg1, arg2); |
205 | c896fe29 | bellard | } |
206 | c896fe29 | bellard | |
207 | c896fe29 | bellard | static inline void tcg_gen_andi_i32(int ret, int arg1, int32_t arg2) |
208 | c896fe29 | bellard | { |
209 | c896fe29 | bellard | /* some cases can be optimized here */
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210 | c896fe29 | bellard | if (arg2 == 0) { |
211 | c896fe29 | bellard | tcg_gen_movi_i32(ret, 0);
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212 | c896fe29 | bellard | } else if (arg2 == 0xffffffff) { |
213 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg1); |
214 | c896fe29 | bellard | } else {
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215 | c896fe29 | bellard | tcg_gen_and_i32(ret, arg1, tcg_const_i32(arg2)); |
216 | c896fe29 | bellard | } |
217 | c896fe29 | bellard | } |
218 | c896fe29 | bellard | |
219 | c896fe29 | bellard | static inline void tcg_gen_or_i32(int ret, int arg1, int arg2) |
220 | c896fe29 | bellard | { |
221 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_or_i32, ret, arg1, arg2); |
222 | c896fe29 | bellard | } |
223 | c896fe29 | bellard | |
224 | c896fe29 | bellard | static inline void tcg_gen_ori_i32(int ret, int arg1, int32_t arg2) |
225 | c896fe29 | bellard | { |
226 | c896fe29 | bellard | /* some cases can be optimized here */
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227 | c896fe29 | bellard | if (arg2 == 0xffffffff) { |
228 | c896fe29 | bellard | tcg_gen_movi_i32(ret, 0);
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229 | c896fe29 | bellard | } else if (arg2 == 0) { |
230 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg1); |
231 | c896fe29 | bellard | } else {
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232 | c896fe29 | bellard | tcg_gen_or_i32(ret, arg1, tcg_const_i32(arg2)); |
233 | c896fe29 | bellard | } |
234 | c896fe29 | bellard | } |
235 | c896fe29 | bellard | |
236 | c896fe29 | bellard | static inline void tcg_gen_xor_i32(int ret, int arg1, int arg2) |
237 | c896fe29 | bellard | { |
238 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_xor_i32, ret, arg1, arg2); |
239 | c896fe29 | bellard | } |
240 | c896fe29 | bellard | |
241 | c896fe29 | bellard | static inline void tcg_gen_xori_i32(int ret, int arg1, int32_t arg2) |
242 | c896fe29 | bellard | { |
243 | c896fe29 | bellard | /* some cases can be optimized here */
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244 | c896fe29 | bellard | if (arg2 == 0) { |
245 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg1); |
246 | c896fe29 | bellard | } else {
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247 | c896fe29 | bellard | tcg_gen_xor_i32(ret, arg1, tcg_const_i32(arg2)); |
248 | c896fe29 | bellard | } |
249 | c896fe29 | bellard | } |
250 | c896fe29 | bellard | |
251 | c896fe29 | bellard | static inline void tcg_gen_shl_i32(int ret, int arg1, int arg2) |
252 | c896fe29 | bellard | { |
253 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_shl_i32, ret, arg1, arg2); |
254 | c896fe29 | bellard | } |
255 | c896fe29 | bellard | |
256 | c896fe29 | bellard | static inline void tcg_gen_shli_i32(int ret, int arg1, int32_t arg2) |
257 | c896fe29 | bellard | { |
258 | c896fe29 | bellard | tcg_gen_shl_i32(ret, arg1, tcg_const_i32(arg2)); |
259 | c896fe29 | bellard | } |
260 | c896fe29 | bellard | |
261 | c896fe29 | bellard | static inline void tcg_gen_shr_i32(int ret, int arg1, int arg2) |
262 | c896fe29 | bellard | { |
263 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_shr_i32, ret, arg1, arg2); |
264 | c896fe29 | bellard | } |
265 | c896fe29 | bellard | |
266 | c896fe29 | bellard | static inline void tcg_gen_shri_i32(int ret, int arg1, int32_t arg2) |
267 | c896fe29 | bellard | { |
268 | c896fe29 | bellard | tcg_gen_shr_i32(ret, arg1, tcg_const_i32(arg2)); |
269 | c896fe29 | bellard | } |
270 | c896fe29 | bellard | |
271 | c896fe29 | bellard | static inline void tcg_gen_sar_i32(int ret, int arg1, int arg2) |
272 | c896fe29 | bellard | { |
273 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_sar_i32, ret, arg1, arg2); |
274 | c896fe29 | bellard | } |
275 | c896fe29 | bellard | |
276 | c896fe29 | bellard | static inline void tcg_gen_sari_i32(int ret, int arg1, int32_t arg2) |
277 | c896fe29 | bellard | { |
278 | c896fe29 | bellard | tcg_gen_sar_i32(ret, arg1, tcg_const_i32(arg2)); |
279 | c896fe29 | bellard | } |
280 | c896fe29 | bellard | |
281 | c896fe29 | bellard | static inline void tcg_gen_brcond_i32(int cond, TCGArg arg1, TCGArg arg2, |
282 | c896fe29 | bellard | int label_index)
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283 | c896fe29 | bellard | { |
284 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
285 | c896fe29 | bellard | } |
286 | c896fe29 | bellard | |
287 | c896fe29 | bellard | static inline void tcg_gen_mul_i32(int ret, int arg1, int arg2) |
288 | c896fe29 | bellard | { |
289 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_mul_i32, ret, arg1, arg2); |
290 | c896fe29 | bellard | } |
291 | c896fe29 | bellard | |
292 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i32
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293 | c896fe29 | bellard | static inline void tcg_gen_div_i32(int ret, int arg1, int arg2) |
294 | c896fe29 | bellard | { |
295 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_div_i32, ret, arg1, arg2); |
296 | c896fe29 | bellard | } |
297 | c896fe29 | bellard | |
298 | c896fe29 | bellard | static inline void tcg_gen_rem_i32(int ret, int arg1, int arg2) |
299 | c896fe29 | bellard | { |
300 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_rem_i32, ret, arg1, arg2); |
301 | c896fe29 | bellard | } |
302 | c896fe29 | bellard | |
303 | c896fe29 | bellard | static inline void tcg_gen_divu_i32(int ret, int arg1, int arg2) |
304 | c896fe29 | bellard | { |
305 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_divu_i32, ret, arg1, arg2); |
306 | c896fe29 | bellard | } |
307 | c896fe29 | bellard | |
308 | c896fe29 | bellard | static inline void tcg_gen_remu_i32(int ret, int arg1, int arg2) |
309 | c896fe29 | bellard | { |
310 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_remu_i32, ret, arg1, arg2); |
311 | c896fe29 | bellard | } |
312 | c896fe29 | bellard | #else
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313 | c896fe29 | bellard | static inline void tcg_gen_div_i32(int ret, int arg1, int arg2) |
314 | c896fe29 | bellard | { |
315 | c896fe29 | bellard | int t0;
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316 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
317 | c896fe29 | bellard | tcg_gen_sari_i32(t0, arg1, 31);
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318 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
319 | c896fe29 | bellard | } |
320 | c896fe29 | bellard | |
321 | c896fe29 | bellard | static inline void tcg_gen_rem_i32(int ret, int arg1, int arg2) |
322 | c896fe29 | bellard | { |
323 | c896fe29 | bellard | int t0;
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324 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
325 | c896fe29 | bellard | tcg_gen_sari_i32(t0, arg1, 31);
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326 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
327 | c896fe29 | bellard | } |
328 | c896fe29 | bellard | |
329 | c896fe29 | bellard | static inline void tcg_gen_divu_i32(int ret, int arg1, int arg2) |
330 | c896fe29 | bellard | { |
331 | c896fe29 | bellard | int t0;
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332 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
333 | c896fe29 | bellard | tcg_gen_movi_i32(t0, 0);
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334 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
335 | c896fe29 | bellard | } |
336 | c896fe29 | bellard | |
337 | c896fe29 | bellard | static inline void tcg_gen_remu_i32(int ret, int arg1, int arg2) |
338 | c896fe29 | bellard | { |
339 | c896fe29 | bellard | int t0;
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340 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
341 | c896fe29 | bellard | tcg_gen_movi_i32(t0, 0);
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342 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
343 | c896fe29 | bellard | } |
344 | c896fe29 | bellard | #endif
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345 | c896fe29 | bellard | |
346 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
347 | c896fe29 | bellard | |
348 | c896fe29 | bellard | static inline void tcg_gen_mov_i64(int ret, int arg) |
349 | c896fe29 | bellard | { |
350 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg); |
351 | c896fe29 | bellard | tcg_gen_mov_i32(ret + 1, arg + 1); |
352 | c896fe29 | bellard | } |
353 | c896fe29 | bellard | |
354 | c896fe29 | bellard | static inline void tcg_gen_movi_i64(int ret, int64_t arg) |
355 | c896fe29 | bellard | { |
356 | c896fe29 | bellard | tcg_gen_movi_i32(ret, arg); |
357 | c896fe29 | bellard | tcg_gen_movi_i32(ret + 1, arg >> 32); |
358 | c896fe29 | bellard | } |
359 | c896fe29 | bellard | |
360 | c896fe29 | bellard | static inline void tcg_gen_ld8u_i64(int ret, int arg2, tcg_target_long offset) |
361 | c896fe29 | bellard | { |
362 | c896fe29 | bellard | tcg_gen_ld8u_i32(ret, arg2, offset); |
363 | c896fe29 | bellard | tcg_gen_movi_i32(ret + 1, 0); |
364 | c896fe29 | bellard | } |
365 | c896fe29 | bellard | |
366 | c896fe29 | bellard | static inline void tcg_gen_ld8s_i64(int ret, int arg2, tcg_target_long offset) |
367 | c896fe29 | bellard | { |
368 | c896fe29 | bellard | tcg_gen_ld8s_i32(ret, arg2, offset); |
369 | c896fe29 | bellard | tcg_gen_sari_i32(ret + 1, ret, 31); |
370 | c896fe29 | bellard | } |
371 | c896fe29 | bellard | |
372 | c896fe29 | bellard | static inline void tcg_gen_ld16u_i64(int ret, int arg2, tcg_target_long offset) |
373 | c896fe29 | bellard | { |
374 | c896fe29 | bellard | tcg_gen_ld16u_i32(ret, arg2, offset); |
375 | c896fe29 | bellard | tcg_gen_movi_i32(ret + 1, 0); |
376 | c896fe29 | bellard | } |
377 | c896fe29 | bellard | |
378 | c896fe29 | bellard | static inline void tcg_gen_ld16s_i64(int ret, int arg2, tcg_target_long offset) |
379 | c896fe29 | bellard | { |
380 | c896fe29 | bellard | tcg_gen_ld16s_i32(ret, arg2, offset); |
381 | c896fe29 | bellard | tcg_gen_sari_i32(ret + 1, ret, 31); |
382 | c896fe29 | bellard | } |
383 | c896fe29 | bellard | |
384 | c896fe29 | bellard | static inline void tcg_gen_ld32u_i64(int ret, int arg2, tcg_target_long offset) |
385 | c896fe29 | bellard | { |
386 | c896fe29 | bellard | tcg_gen_ld_i32(ret, arg2, offset); |
387 | c896fe29 | bellard | tcg_gen_movi_i32(ret + 1, 0); |
388 | c896fe29 | bellard | } |
389 | c896fe29 | bellard | |
390 | c896fe29 | bellard | static inline void tcg_gen_ld32s_i64(int ret, int arg2, tcg_target_long offset) |
391 | c896fe29 | bellard | { |
392 | c896fe29 | bellard | tcg_gen_ld_i32(ret, arg2, offset); |
393 | c896fe29 | bellard | tcg_gen_sari_i32(ret + 1, ret, 31); |
394 | c896fe29 | bellard | } |
395 | c896fe29 | bellard | |
396 | c896fe29 | bellard | static inline void tcg_gen_ld_i64(int ret, int arg2, tcg_target_long offset) |
397 | c896fe29 | bellard | { |
398 | c896fe29 | bellard | /* since arg2 and ret have different types, they cannot be the
|
399 | c896fe29 | bellard | same temporary */
|
400 | c896fe29 | bellard | #ifdef TCG_TARGET_WORDS_BIGENDIAN
|
401 | c896fe29 | bellard | tcg_gen_ld_i32(ret + 1, arg2, offset);
|
402 | c896fe29 | bellard | tcg_gen_ld_i32(ret, arg2, offset + 4);
|
403 | c896fe29 | bellard | #else
|
404 | c896fe29 | bellard | tcg_gen_ld_i32(ret, arg2, offset); |
405 | c896fe29 | bellard | tcg_gen_ld_i32(ret + 1, arg2, offset + 4); |
406 | c896fe29 | bellard | #endif
|
407 | c896fe29 | bellard | } |
408 | c896fe29 | bellard | |
409 | c896fe29 | bellard | static inline void tcg_gen_st8_i64(int arg1, int arg2, tcg_target_long offset) |
410 | c896fe29 | bellard | { |
411 | c896fe29 | bellard | tcg_gen_st8_i32(arg1, arg2, offset); |
412 | c896fe29 | bellard | } |
413 | c896fe29 | bellard | |
414 | c896fe29 | bellard | static inline void tcg_gen_st16_i64(int arg1, int arg2, tcg_target_long offset) |
415 | c896fe29 | bellard | { |
416 | c896fe29 | bellard | tcg_gen_st16_i32(arg1, arg2, offset); |
417 | c896fe29 | bellard | } |
418 | c896fe29 | bellard | |
419 | c896fe29 | bellard | static inline void tcg_gen_st32_i64(int arg1, int arg2, tcg_target_long offset) |
420 | c896fe29 | bellard | { |
421 | c896fe29 | bellard | tcg_gen_st_i32(arg1, arg2, offset); |
422 | c896fe29 | bellard | } |
423 | c896fe29 | bellard | |
424 | c896fe29 | bellard | static inline void tcg_gen_st_i64(int arg1, int arg2, tcg_target_long offset) |
425 | c896fe29 | bellard | { |
426 | c896fe29 | bellard | #ifdef TCG_TARGET_WORDS_BIGENDIAN
|
427 | c896fe29 | bellard | tcg_gen_st_i32(arg1 + 1, arg2, offset);
|
428 | c896fe29 | bellard | tcg_gen_st_i32(arg1, arg2, offset + 4);
|
429 | c896fe29 | bellard | #else
|
430 | c896fe29 | bellard | tcg_gen_st_i32(arg1, arg2, offset); |
431 | c896fe29 | bellard | tcg_gen_st_i32(arg1 + 1, arg2, offset + 4); |
432 | c896fe29 | bellard | #endif
|
433 | c896fe29 | bellard | } |
434 | c896fe29 | bellard | |
435 | c896fe29 | bellard | static inline void tcg_gen_add_i64(int ret, int arg1, int arg2) |
436 | c896fe29 | bellard | { |
437 | c896fe29 | bellard | tcg_gen_op6(INDEX_op_add2_i32, ret, ret + 1,
|
438 | c896fe29 | bellard | arg1, arg1 + 1, arg2, arg2 + 1); |
439 | c896fe29 | bellard | } |
440 | c896fe29 | bellard | |
441 | c896fe29 | bellard | static inline void tcg_gen_addi_i64(int ret, int arg1, int64_t arg2) |
442 | c896fe29 | bellard | { |
443 | c896fe29 | bellard | tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2)); |
444 | c896fe29 | bellard | } |
445 | c896fe29 | bellard | |
446 | c896fe29 | bellard | static inline void tcg_gen_sub_i64(int ret, int arg1, int arg2) |
447 | c896fe29 | bellard | { |
448 | c896fe29 | bellard | tcg_gen_op6(INDEX_op_sub2_i32, ret, ret + 1,
|
449 | c896fe29 | bellard | arg1, arg1 + 1, arg2, arg2 + 1); |
450 | c896fe29 | bellard | } |
451 | c896fe29 | bellard | |
452 | c896fe29 | bellard | static inline void tcg_gen_subi_i64(int ret, int arg1, int64_t arg2) |
453 | c896fe29 | bellard | { |
454 | c896fe29 | bellard | tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2)); |
455 | c896fe29 | bellard | } |
456 | c896fe29 | bellard | |
457 | c896fe29 | bellard | static inline void tcg_gen_and_i64(int ret, int arg1, int arg2) |
458 | c896fe29 | bellard | { |
459 | c896fe29 | bellard | tcg_gen_and_i32(ret, arg1, arg2); |
460 | c896fe29 | bellard | tcg_gen_and_i32(ret + 1, arg1 + 1, arg2 + 1); |
461 | c896fe29 | bellard | } |
462 | c896fe29 | bellard | |
463 | c896fe29 | bellard | static inline void tcg_gen_andi_i64(int ret, int arg1, int64_t arg2) |
464 | c896fe29 | bellard | { |
465 | c896fe29 | bellard | tcg_gen_andi_i32(ret, arg1, arg2); |
466 | c896fe29 | bellard | tcg_gen_andi_i32(ret + 1, arg1 + 1, arg2 >> 32); |
467 | c896fe29 | bellard | } |
468 | c896fe29 | bellard | |
469 | c896fe29 | bellard | static inline void tcg_gen_or_i64(int ret, int arg1, int arg2) |
470 | c896fe29 | bellard | { |
471 | c896fe29 | bellard | tcg_gen_or_i32(ret, arg1, arg2); |
472 | c896fe29 | bellard | tcg_gen_or_i32(ret + 1, arg1 + 1, arg2 + 1); |
473 | c896fe29 | bellard | } |
474 | c896fe29 | bellard | |
475 | c896fe29 | bellard | static inline void tcg_gen_ori_i64(int ret, int arg1, int64_t arg2) |
476 | c896fe29 | bellard | { |
477 | c896fe29 | bellard | tcg_gen_ori_i32(ret, arg1, arg2); |
478 | c896fe29 | bellard | tcg_gen_ori_i32(ret + 1, arg1 + 1, arg2 >> 32); |
479 | c896fe29 | bellard | } |
480 | c896fe29 | bellard | |
481 | c896fe29 | bellard | static inline void tcg_gen_xor_i64(int ret, int arg1, int arg2) |
482 | c896fe29 | bellard | { |
483 | c896fe29 | bellard | tcg_gen_xor_i32(ret, arg1, arg2); |
484 | c896fe29 | bellard | tcg_gen_xor_i32(ret + 1, arg1 + 1, arg2 + 1); |
485 | c896fe29 | bellard | } |
486 | c896fe29 | bellard | |
487 | c896fe29 | bellard | static inline void tcg_gen_xori_i64(int ret, int arg1, int64_t arg2) |
488 | c896fe29 | bellard | { |
489 | c896fe29 | bellard | tcg_gen_xori_i32(ret, arg1, arg2); |
490 | c896fe29 | bellard | tcg_gen_xori_i32(ret + 1, arg1 + 1, arg2 >> 32); |
491 | c896fe29 | bellard | } |
492 | c896fe29 | bellard | |
493 | c896fe29 | bellard | /* XXX: use generic code when basic block handling is OK or CPU
|
494 | c896fe29 | bellard | specific code (x86) */
|
495 | c896fe29 | bellard | static inline void tcg_gen_shl_i64(int ret, int arg1, int64_t arg2) |
496 | c896fe29 | bellard | { |
497 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_shl_i64, ret, arg1, arg2); |
498 | c896fe29 | bellard | } |
499 | c896fe29 | bellard | |
500 | c896fe29 | bellard | static inline void tcg_gen_shli_i64(int ret, int arg1, int64_t arg2) |
501 | c896fe29 | bellard | { |
502 | c896fe29 | bellard | tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
503 | c896fe29 | bellard | } |
504 | c896fe29 | bellard | |
505 | c896fe29 | bellard | static inline void tcg_gen_shr_i64(int ret, int arg1, int64_t arg2) |
506 | c896fe29 | bellard | { |
507 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_shr_i64, ret, arg1, arg2); |
508 | c896fe29 | bellard | } |
509 | c896fe29 | bellard | |
510 | c896fe29 | bellard | static inline void tcg_gen_shri_i64(int ret, int arg1, int64_t arg2) |
511 | c896fe29 | bellard | { |
512 | c896fe29 | bellard | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
513 | c896fe29 | bellard | } |
514 | c896fe29 | bellard | |
515 | c896fe29 | bellard | static inline void tcg_gen_sar_i64(int ret, int arg1, int64_t arg2) |
516 | c896fe29 | bellard | { |
517 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_sar_i64, ret, arg1, arg2); |
518 | c896fe29 | bellard | } |
519 | c896fe29 | bellard | |
520 | c896fe29 | bellard | static inline void tcg_gen_sari_i64(int ret, int arg1, int64_t arg2) |
521 | c896fe29 | bellard | { |
522 | c896fe29 | bellard | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
523 | c896fe29 | bellard | } |
524 | c896fe29 | bellard | |
525 | c896fe29 | bellard | static inline void tcg_gen_brcond_i64(int cond, TCGArg arg1, TCGArg arg2, |
526 | c896fe29 | bellard | int label_index)
|
527 | c896fe29 | bellard | { |
528 | c896fe29 | bellard | tcg_gen_op6(INDEX_op_brcond2_i32, |
529 | c896fe29 | bellard | arg1, arg1 + 1, arg2, arg2 + 1, cond, label_index); |
530 | c896fe29 | bellard | } |
531 | c896fe29 | bellard | |
532 | c896fe29 | bellard | static inline void tcg_gen_mul_i64(int ret, int arg1, int arg2) |
533 | c896fe29 | bellard | { |
534 | c896fe29 | bellard | int t0, t1;
|
535 | c896fe29 | bellard | |
536 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I64); |
537 | c896fe29 | bellard | t1 = tcg_temp_new(TCG_TYPE_I32); |
538 | c896fe29 | bellard | |
539 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_mulu2_i32, t0, t0 + 1, arg1, arg2);
|
540 | c896fe29 | bellard | |
541 | c896fe29 | bellard | tcg_gen_mul_i32(t1, arg1, arg2 + 1);
|
542 | c896fe29 | bellard | tcg_gen_add_i32(t0 + 1, t0 + 1, t1); |
543 | c896fe29 | bellard | tcg_gen_mul_i32(t1, arg1 + 1, arg2);
|
544 | c896fe29 | bellard | tcg_gen_add_i32(t0 + 1, t0 + 1, t1); |
545 | c896fe29 | bellard | |
546 | c896fe29 | bellard | tcg_gen_mov_i64(ret, t0); |
547 | c896fe29 | bellard | } |
548 | c896fe29 | bellard | |
549 | c896fe29 | bellard | static inline void tcg_gen_div_i64(int ret, int arg1, int64_t arg2) |
550 | c896fe29 | bellard | { |
551 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_div_i64, ret, arg1, arg2); |
552 | c896fe29 | bellard | } |
553 | c896fe29 | bellard | |
554 | c896fe29 | bellard | static inline void tcg_gen_rem_i64(int ret, int arg1, int64_t arg2) |
555 | c896fe29 | bellard | { |
556 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_rem_i64, ret, arg1, arg2); |
557 | c896fe29 | bellard | } |
558 | c896fe29 | bellard | |
559 | c896fe29 | bellard | static inline void tcg_gen_divu_i64(int ret, int arg1, int64_t arg2) |
560 | c896fe29 | bellard | { |
561 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_divu_i64, ret, arg1, arg2); |
562 | c896fe29 | bellard | } |
563 | c896fe29 | bellard | |
564 | c896fe29 | bellard | static inline void tcg_gen_remu_i64(int ret, int arg1, int64_t arg2) |
565 | c896fe29 | bellard | { |
566 | c896fe29 | bellard | tcg_gen_helper_1_2(tcg_helper_remu_i64, ret, arg1, arg2); |
567 | c896fe29 | bellard | } |
568 | c896fe29 | bellard | |
569 | c896fe29 | bellard | #else
|
570 | c896fe29 | bellard | |
571 | c896fe29 | bellard | static inline void tcg_gen_mov_i64(int ret, int arg) |
572 | c896fe29 | bellard | { |
573 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_mov_i64, ret, arg); |
574 | c896fe29 | bellard | } |
575 | c896fe29 | bellard | |
576 | c896fe29 | bellard | static inline void tcg_gen_movi_i64(int ret, int64_t arg) |
577 | c896fe29 | bellard | { |
578 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_movi_i64, ret, arg); |
579 | c896fe29 | bellard | } |
580 | c896fe29 | bellard | |
581 | c896fe29 | bellard | static inline void tcg_gen_ld8u_i64(int ret, int arg2, tcg_target_long offset) |
582 | c896fe29 | bellard | { |
583 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_ld8u_i64, ret, arg2, offset); |
584 | c896fe29 | bellard | } |
585 | c896fe29 | bellard | |
586 | c896fe29 | bellard | static inline void tcg_gen_ld8s_i64(int ret, int arg2, tcg_target_long offset) |
587 | c896fe29 | bellard | { |
588 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_ld8s_i64, ret, arg2, offset); |
589 | c896fe29 | bellard | } |
590 | c896fe29 | bellard | |
591 | c896fe29 | bellard | static inline void tcg_gen_ld16u_i64(int ret, int arg2, tcg_target_long offset) |
592 | c896fe29 | bellard | { |
593 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_ld16u_i64, ret, arg2, offset); |
594 | c896fe29 | bellard | } |
595 | c896fe29 | bellard | |
596 | c896fe29 | bellard | static inline void tcg_gen_ld16s_i64(int ret, int arg2, tcg_target_long offset) |
597 | c896fe29 | bellard | { |
598 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_ld16s_i64, ret, arg2, offset); |
599 | c896fe29 | bellard | } |
600 | c896fe29 | bellard | |
601 | c896fe29 | bellard | static inline void tcg_gen_ld32u_i64(int ret, int arg2, tcg_target_long offset) |
602 | c896fe29 | bellard | { |
603 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_ld32u_i64, ret, arg2, offset); |
604 | c896fe29 | bellard | } |
605 | c896fe29 | bellard | |
606 | c896fe29 | bellard | static inline void tcg_gen_ld32s_i64(int ret, int arg2, tcg_target_long offset) |
607 | c896fe29 | bellard | { |
608 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_ld32s_i64, ret, arg2, offset); |
609 | c896fe29 | bellard | } |
610 | c896fe29 | bellard | |
611 | c896fe29 | bellard | static inline void tcg_gen_ld_i64(int ret, int arg2, tcg_target_long offset) |
612 | c896fe29 | bellard | { |
613 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_ld_i64, ret, arg2, offset); |
614 | c896fe29 | bellard | } |
615 | c896fe29 | bellard | |
616 | c896fe29 | bellard | static inline void tcg_gen_st8_i64(int arg1, int arg2, tcg_target_long offset) |
617 | c896fe29 | bellard | { |
618 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_st8_i64, arg1, arg2, offset); |
619 | c896fe29 | bellard | } |
620 | c896fe29 | bellard | |
621 | c896fe29 | bellard | static inline void tcg_gen_st16_i64(int arg1, int arg2, tcg_target_long offset) |
622 | c896fe29 | bellard | { |
623 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_st16_i64, arg1, arg2, offset); |
624 | c896fe29 | bellard | } |
625 | c896fe29 | bellard | |
626 | c896fe29 | bellard | static inline void tcg_gen_st32_i64(int arg1, int arg2, tcg_target_long offset) |
627 | c896fe29 | bellard | { |
628 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_st32_i64, arg1, arg2, offset); |
629 | c896fe29 | bellard | } |
630 | c896fe29 | bellard | |
631 | c896fe29 | bellard | static inline void tcg_gen_st_i64(int arg1, int arg2, tcg_target_long offset) |
632 | c896fe29 | bellard | { |
633 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_st_i64, arg1, arg2, offset); |
634 | c896fe29 | bellard | } |
635 | c896fe29 | bellard | |
636 | c896fe29 | bellard | static inline void tcg_gen_add_i64(int ret, int arg1, int arg2) |
637 | c896fe29 | bellard | { |
638 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_add_i64, ret, arg1, arg2); |
639 | c896fe29 | bellard | } |
640 | c896fe29 | bellard | |
641 | c896fe29 | bellard | static inline void tcg_gen_addi_i64(int ret, int arg1, int64_t arg2) |
642 | c896fe29 | bellard | { |
643 | c896fe29 | bellard | tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2)); |
644 | c896fe29 | bellard | } |
645 | c896fe29 | bellard | |
646 | c896fe29 | bellard | static inline void tcg_gen_sub_i64(int ret, int arg1, int arg2) |
647 | c896fe29 | bellard | { |
648 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_sub_i64, ret, arg1, arg2); |
649 | c896fe29 | bellard | } |
650 | c896fe29 | bellard | |
651 | c896fe29 | bellard | static inline void tcg_gen_subi_i64(int ret, int arg1, int64_t arg2) |
652 | c896fe29 | bellard | { |
653 | c896fe29 | bellard | tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2)); |
654 | c896fe29 | bellard | } |
655 | c896fe29 | bellard | |
656 | c896fe29 | bellard | static inline void tcg_gen_and_i64(int ret, int arg1, int arg2) |
657 | c896fe29 | bellard | { |
658 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_and_i64, ret, arg1, arg2); |
659 | c896fe29 | bellard | } |
660 | c896fe29 | bellard | |
661 | c896fe29 | bellard | static inline void tcg_gen_andi_i64(int ret, int arg1, int64_t arg2) |
662 | c896fe29 | bellard | { |
663 | c896fe29 | bellard | tcg_gen_and_i64(ret, arg1, tcg_const_i64(arg2)); |
664 | c896fe29 | bellard | } |
665 | c896fe29 | bellard | |
666 | c896fe29 | bellard | static inline void tcg_gen_or_i64(int ret, int arg1, int arg2) |
667 | c896fe29 | bellard | { |
668 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_or_i64, ret, arg1, arg2); |
669 | c896fe29 | bellard | } |
670 | c896fe29 | bellard | |
671 | c896fe29 | bellard | static inline void tcg_gen_ori_i64(int ret, int arg1, int64_t arg2) |
672 | c896fe29 | bellard | { |
673 | c896fe29 | bellard | tcg_gen_or_i64(ret, arg1, tcg_const_i64(arg2)); |
674 | c896fe29 | bellard | } |
675 | c896fe29 | bellard | |
676 | c896fe29 | bellard | static inline void tcg_gen_xor_i64(int ret, int arg1, int arg2) |
677 | c896fe29 | bellard | { |
678 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_xor_i64, ret, arg1, arg2); |
679 | c896fe29 | bellard | } |
680 | c896fe29 | bellard | |
681 | c896fe29 | bellard | static inline void tcg_gen_xori_i64(int ret, int arg1, int64_t arg2) |
682 | c896fe29 | bellard | { |
683 | c896fe29 | bellard | tcg_gen_xor_i64(ret, arg1, tcg_const_i64(arg2)); |
684 | c896fe29 | bellard | } |
685 | c896fe29 | bellard | |
686 | c896fe29 | bellard | static inline void tcg_gen_shl_i64(int ret, int arg1, int arg2) |
687 | c896fe29 | bellard | { |
688 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_shl_i64, ret, arg1, arg2); |
689 | c896fe29 | bellard | } |
690 | c896fe29 | bellard | |
691 | c896fe29 | bellard | static inline void tcg_gen_shli_i64(int ret, int arg1, int64_t arg2) |
692 | c896fe29 | bellard | { |
693 | c896fe29 | bellard | tcg_gen_shl_i64(ret, arg1, tcg_const_i64(arg2)); |
694 | c896fe29 | bellard | } |
695 | c896fe29 | bellard | |
696 | c896fe29 | bellard | static inline void tcg_gen_shr_i64(int ret, int arg1, int arg2) |
697 | c896fe29 | bellard | { |
698 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_shr_i64, ret, arg1, arg2); |
699 | c896fe29 | bellard | } |
700 | c896fe29 | bellard | |
701 | c896fe29 | bellard | static inline void tcg_gen_shri_i64(int ret, int arg1, int64_t arg2) |
702 | c896fe29 | bellard | { |
703 | c896fe29 | bellard | tcg_gen_shr_i64(ret, arg1, tcg_const_i64(arg2)); |
704 | c896fe29 | bellard | } |
705 | c896fe29 | bellard | |
706 | c896fe29 | bellard | static inline void tcg_gen_sar_i64(int ret, int arg1, int arg2) |
707 | c896fe29 | bellard | { |
708 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_sar_i64, ret, arg1, arg2); |
709 | c896fe29 | bellard | } |
710 | c896fe29 | bellard | |
711 | c896fe29 | bellard | static inline void tcg_gen_sari_i64(int ret, int arg1, int64_t arg2) |
712 | c896fe29 | bellard | { |
713 | c896fe29 | bellard | tcg_gen_sar_i64(ret, arg1, tcg_const_i64(arg2)); |
714 | c896fe29 | bellard | } |
715 | c896fe29 | bellard | |
716 | c896fe29 | bellard | static inline void tcg_gen_brcond_i64(int cond, TCGArg arg1, TCGArg arg2, |
717 | c896fe29 | bellard | int label_index)
|
718 | c896fe29 | bellard | { |
719 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
720 | c896fe29 | bellard | } |
721 | c896fe29 | bellard | |
722 | c896fe29 | bellard | static inline void tcg_gen_mul_i64(int ret, int arg1, int arg2) |
723 | c896fe29 | bellard | { |
724 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_mul_i64, ret, arg1, arg2); |
725 | c896fe29 | bellard | } |
726 | c896fe29 | bellard | |
727 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i64
|
728 | c896fe29 | bellard | static inline void tcg_gen_div_i64(int ret, int arg1, int arg2) |
729 | c896fe29 | bellard | { |
730 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_div_i64, ret, arg1, arg2); |
731 | c896fe29 | bellard | } |
732 | c896fe29 | bellard | |
733 | c896fe29 | bellard | static inline void tcg_gen_rem_i64(int ret, int arg1, int arg2) |
734 | c896fe29 | bellard | { |
735 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_rem_i64, ret, arg1, arg2); |
736 | c896fe29 | bellard | } |
737 | c896fe29 | bellard | |
738 | c896fe29 | bellard | static inline void tcg_gen_divu_i64(int ret, int arg1, int arg2) |
739 | c896fe29 | bellard | { |
740 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_divu_i64, ret, arg1, arg2); |
741 | c896fe29 | bellard | } |
742 | c896fe29 | bellard | |
743 | c896fe29 | bellard | static inline void tcg_gen_remu_i64(int ret, int arg1, int arg2) |
744 | c896fe29 | bellard | { |
745 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_remu_i64, ret, arg1, arg2); |
746 | c896fe29 | bellard | } |
747 | c896fe29 | bellard | #else
|
748 | c896fe29 | bellard | static inline void tcg_gen_div_i64(int ret, int arg1, int arg2) |
749 | c896fe29 | bellard | { |
750 | c896fe29 | bellard | int t0;
|
751 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I64); |
752 | c896fe29 | bellard | tcg_gen_sari_i64(t0, arg1, 63);
|
753 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
754 | c896fe29 | bellard | } |
755 | c896fe29 | bellard | |
756 | c896fe29 | bellard | static inline void tcg_gen_rem_i64(int ret, int arg1, int arg2) |
757 | c896fe29 | bellard | { |
758 | c896fe29 | bellard | int t0;
|
759 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I64); |
760 | c896fe29 | bellard | tcg_gen_sari_i64(t0, arg1, 63);
|
761 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
762 | c896fe29 | bellard | } |
763 | c896fe29 | bellard | |
764 | c896fe29 | bellard | static inline void tcg_gen_divu_i64(int ret, int arg1, int arg2) |
765 | c896fe29 | bellard | { |
766 | c896fe29 | bellard | int t0;
|
767 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I64); |
768 | c896fe29 | bellard | tcg_gen_movi_i64(t0, 0);
|
769 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
770 | c896fe29 | bellard | } |
771 | c896fe29 | bellard | |
772 | c896fe29 | bellard | static inline void tcg_gen_remu_i64(int ret, int arg1, int arg2) |
773 | c896fe29 | bellard | { |
774 | c896fe29 | bellard | int t0;
|
775 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I64); |
776 | c896fe29 | bellard | tcg_gen_movi_i64(t0, 0);
|
777 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
778 | c896fe29 | bellard | } |
779 | c896fe29 | bellard | #endif
|
780 | c896fe29 | bellard | |
781 | c896fe29 | bellard | #endif
|
782 | c896fe29 | bellard | |
783 | c896fe29 | bellard | /***************************************/
|
784 | c896fe29 | bellard | /* optional operations */
|
785 | c896fe29 | bellard | |
786 | c896fe29 | bellard | static inline void tcg_gen_ext8s_i32(int ret, int arg) |
787 | c896fe29 | bellard | { |
788 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i32
|
789 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_ext8s_i32, ret, arg); |
790 | c896fe29 | bellard | #else
|
791 | c896fe29 | bellard | tcg_gen_shli_i32(ret, arg, 24);
|
792 | c896fe29 | bellard | tcg_gen_sari_i32(ret, arg, 24);
|
793 | c896fe29 | bellard | #endif
|
794 | c896fe29 | bellard | } |
795 | c896fe29 | bellard | |
796 | c896fe29 | bellard | static inline void tcg_gen_ext16s_i32(int ret, int arg) |
797 | c896fe29 | bellard | { |
798 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i32
|
799 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_ext16s_i32, ret, arg); |
800 | c896fe29 | bellard | #else
|
801 | c896fe29 | bellard | tcg_gen_shli_i32(ret, arg, 16);
|
802 | c896fe29 | bellard | tcg_gen_sari_i32(ret, arg, 16);
|
803 | c896fe29 | bellard | #endif
|
804 | c896fe29 | bellard | } |
805 | c896fe29 | bellard | |
806 | c896fe29 | bellard | /* Note: we assume the two high bytes are set to zero */
|
807 | c896fe29 | bellard | static inline void tcg_gen_bswap16_i32(TCGArg ret, TCGArg arg) |
808 | c896fe29 | bellard | { |
809 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_bswap16_i32
|
810 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_bswap16_i32, ret, arg); |
811 | c896fe29 | bellard | #else
|
812 | c896fe29 | bellard | TCGArg t0, t1; |
813 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
814 | c896fe29 | bellard | t1 = tcg_temp_new(TCG_TYPE_I32); |
815 | c896fe29 | bellard | |
816 | c896fe29 | bellard | tcg_gen_shri_i32(t0, arg, 8);
|
817 | c896fe29 | bellard | tcg_gen_andi_i32(t1, arg, 0x000000ff);
|
818 | c896fe29 | bellard | tcg_gen_shli_i32(t1, t1, 8);
|
819 | c896fe29 | bellard | tcg_gen_or_i32(ret, t0, t1); |
820 | c896fe29 | bellard | #endif
|
821 | c896fe29 | bellard | } |
822 | c896fe29 | bellard | |
823 | c896fe29 | bellard | static inline void tcg_gen_bswap_i32(TCGArg ret, TCGArg arg) |
824 | c896fe29 | bellard | { |
825 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_bswap_i32
|
826 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_bswap_i32, ret, arg); |
827 | c896fe29 | bellard | #else
|
828 | c896fe29 | bellard | TCGArg t0, t1; |
829 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
830 | c896fe29 | bellard | t1 = tcg_temp_new(TCG_TYPE_I32); |
831 | c896fe29 | bellard | |
832 | c896fe29 | bellard | tcg_gen_shli_i32(t0, arg, 24);
|
833 | c896fe29 | bellard | |
834 | c896fe29 | bellard | tcg_gen_andi_i32(t1, arg, 0x0000ff00);
|
835 | c896fe29 | bellard | tcg_gen_shli_i32(t1, t1, 8);
|
836 | c896fe29 | bellard | tcg_gen_or_i32(t0, t0, t1); |
837 | c896fe29 | bellard | |
838 | c896fe29 | bellard | tcg_gen_shri_i32(t1, arg, 8);
|
839 | c896fe29 | bellard | tcg_gen_andi_i32(t1, t1, 0x0000ff00);
|
840 | c896fe29 | bellard | tcg_gen_or_i32(t0, t0, t1); |
841 | c896fe29 | bellard | |
842 | c896fe29 | bellard | tcg_gen_shri_i32(t1, arg, 24);
|
843 | c896fe29 | bellard | tcg_gen_or_i32(ret, t0, t1); |
844 | c896fe29 | bellard | #endif
|
845 | c896fe29 | bellard | } |
846 | c896fe29 | bellard | |
847 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
848 | c896fe29 | bellard | static inline void tcg_gen_ext8s_i64(int ret, int arg) |
849 | c896fe29 | bellard | { |
850 | c896fe29 | bellard | tcg_gen_ext8s_i32(ret, arg); |
851 | c896fe29 | bellard | tcg_gen_sari_i32(ret + 1, ret, 31); |
852 | c896fe29 | bellard | } |
853 | c896fe29 | bellard | |
854 | c896fe29 | bellard | static inline void tcg_gen_ext16s_i64(int ret, int arg) |
855 | c896fe29 | bellard | { |
856 | c896fe29 | bellard | tcg_gen_ext16s_i32(ret, arg); |
857 | c896fe29 | bellard | tcg_gen_sari_i32(ret + 1, ret, 31); |
858 | c896fe29 | bellard | } |
859 | c896fe29 | bellard | |
860 | c896fe29 | bellard | static inline void tcg_gen_ext32s_i64(int ret, int arg) |
861 | c896fe29 | bellard | { |
862 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg); |
863 | c896fe29 | bellard | tcg_gen_sari_i32(ret + 1, ret, 31); |
864 | c896fe29 | bellard | } |
865 | c896fe29 | bellard | |
866 | c896fe29 | bellard | static inline void tcg_gen_trunc_i64_i32(int ret, int arg) |
867 | c896fe29 | bellard | { |
868 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg); |
869 | c896fe29 | bellard | } |
870 | c896fe29 | bellard | |
871 | c896fe29 | bellard | static inline void tcg_gen_extu_i32_i64(int ret, int arg) |
872 | c896fe29 | bellard | { |
873 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg); |
874 | c896fe29 | bellard | tcg_gen_movi_i32(ret + 1, 0); |
875 | c896fe29 | bellard | } |
876 | c896fe29 | bellard | |
877 | c896fe29 | bellard | static inline void tcg_gen_ext_i32_i64(int ret, int arg) |
878 | c896fe29 | bellard | { |
879 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg); |
880 | c896fe29 | bellard | tcg_gen_sari_i32(ret + 1, ret, 31); |
881 | c896fe29 | bellard | } |
882 | c896fe29 | bellard | |
883 | c896fe29 | bellard | static inline void tcg_gen_bswap_i64(int ret, int arg) |
884 | c896fe29 | bellard | { |
885 | c896fe29 | bellard | int t0, t1;
|
886 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
887 | c896fe29 | bellard | t1 = tcg_temp_new(TCG_TYPE_I32); |
888 | c896fe29 | bellard | |
889 | c896fe29 | bellard | tcg_gen_bswap_i32(t0, arg); |
890 | c896fe29 | bellard | tcg_gen_bswap_i32(t1, arg + 1);
|
891 | c896fe29 | bellard | tcg_gen_mov_i32(ret, t1); |
892 | c896fe29 | bellard | tcg_gen_mov_i32(ret + 1, t0);
|
893 | c896fe29 | bellard | } |
894 | c896fe29 | bellard | #else
|
895 | c896fe29 | bellard | |
896 | c896fe29 | bellard | static inline void tcg_gen_ext8s_i64(int ret, int arg) |
897 | c896fe29 | bellard | { |
898 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i64
|
899 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_ext8s_i64, ret, arg); |
900 | c896fe29 | bellard | #else
|
901 | c896fe29 | bellard | tcg_gen_shli_i64(ret, arg, 56);
|
902 | c896fe29 | bellard | tcg_gen_sari_i64(ret, arg, 56);
|
903 | c896fe29 | bellard | #endif
|
904 | c896fe29 | bellard | } |
905 | c896fe29 | bellard | |
906 | c896fe29 | bellard | static inline void tcg_gen_ext16s_i64(int ret, int arg) |
907 | c896fe29 | bellard | { |
908 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i64
|
909 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_ext16s_i64, ret, arg); |
910 | c896fe29 | bellard | #else
|
911 | c896fe29 | bellard | tcg_gen_shli_i64(ret, arg, 48);
|
912 | c896fe29 | bellard | tcg_gen_sari_i64(ret, arg, 48);
|
913 | c896fe29 | bellard | #endif
|
914 | c896fe29 | bellard | } |
915 | c896fe29 | bellard | |
916 | c896fe29 | bellard | static inline void tcg_gen_ext32s_i64(int ret, int arg) |
917 | c896fe29 | bellard | { |
918 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext32s_i64
|
919 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_ext32s_i64, ret, arg); |
920 | c896fe29 | bellard | #else
|
921 | c896fe29 | bellard | tcg_gen_shli_i64(ret, arg, 32);
|
922 | c896fe29 | bellard | tcg_gen_sari_i64(ret, arg, 32);
|
923 | c896fe29 | bellard | #endif
|
924 | c896fe29 | bellard | } |
925 | c896fe29 | bellard | |
926 | c896fe29 | bellard | /* Note: we assume the target supports move between 32 and 64 bit
|
927 | c896fe29 | bellard | registers */
|
928 | c896fe29 | bellard | static inline void tcg_gen_trunc_i64_i32(int ret, int arg) |
929 | c896fe29 | bellard | { |
930 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg); |
931 | c896fe29 | bellard | } |
932 | c896fe29 | bellard | |
933 | c896fe29 | bellard | /* Note: we assume the target supports move between 32 and 64 bit
|
934 | c896fe29 | bellard | registers */
|
935 | c896fe29 | bellard | static inline void tcg_gen_extu_i32_i64(int ret, int arg) |
936 | c896fe29 | bellard | { |
937 | c896fe29 | bellard | tcg_gen_andi_i64(ret, arg, 0xffffffff);
|
938 | c896fe29 | bellard | } |
939 | c896fe29 | bellard | |
940 | c896fe29 | bellard | /* Note: we assume the target supports move between 32 and 64 bit
|
941 | c896fe29 | bellard | registers */
|
942 | c896fe29 | bellard | static inline void tcg_gen_ext_i32_i64(int ret, int arg) |
943 | c896fe29 | bellard | { |
944 | c896fe29 | bellard | tcg_gen_ext32s_i64(ret, arg); |
945 | c896fe29 | bellard | } |
946 | c896fe29 | bellard | |
947 | c896fe29 | bellard | static inline void tcg_gen_bswap_i64(TCGArg ret, TCGArg arg) |
948 | c896fe29 | bellard | { |
949 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_bswap_i64
|
950 | c896fe29 | bellard | tcg_gen_op2(INDEX_op_bswap_i64, ret, arg); |
951 | c896fe29 | bellard | #else
|
952 | c896fe29 | bellard | TCGArg t0, t1; |
953 | c896fe29 | bellard | t0 = tcg_temp_new(TCG_TYPE_I32); |
954 | c896fe29 | bellard | t1 = tcg_temp_new(TCG_TYPE_I32); |
955 | c896fe29 | bellard | |
956 | c896fe29 | bellard | tcg_gen_shli_i64(t0, arg, 56);
|
957 | c896fe29 | bellard | |
958 | c896fe29 | bellard | tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
959 | c896fe29 | bellard | tcg_gen_shli_i64(t1, t1, 40);
|
960 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
961 | c896fe29 | bellard | |
962 | c896fe29 | bellard | tcg_gen_andi_i64(t1, arg, 0x00ff0000);
|
963 | c896fe29 | bellard | tcg_gen_shli_i64(t1, t1, 24);
|
964 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
965 | c896fe29 | bellard | |
966 | c896fe29 | bellard | tcg_gen_andi_i64(t1, arg, 0xff000000);
|
967 | c896fe29 | bellard | tcg_gen_shli_i64(t1, t1, 8);
|
968 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
969 | c896fe29 | bellard | |
970 | c896fe29 | bellard | tcg_gen_shri_i64(t1, arg, 8);
|
971 | c896fe29 | bellard | tcg_gen_andi_i64(t1, t1, 0xff000000);
|
972 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
973 | c896fe29 | bellard | |
974 | c896fe29 | bellard | tcg_gen_shri_i64(t1, arg, 24);
|
975 | c896fe29 | bellard | tcg_gen_andi_i64(t1, t1, 0x00ff0000);
|
976 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
977 | c896fe29 | bellard | |
978 | c896fe29 | bellard | tcg_gen_shri_i64(t1, arg, 40);
|
979 | c896fe29 | bellard | tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
980 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
981 | c896fe29 | bellard | |
982 | c896fe29 | bellard | tcg_gen_shri_i64(t1, arg, 56);
|
983 | c896fe29 | bellard | tcg_gen_or_i64(ret, t0, t1); |
984 | c896fe29 | bellard | #endif
|
985 | c896fe29 | bellard | } |
986 | c896fe29 | bellard | |
987 | c896fe29 | bellard | #endif
|
988 | c896fe29 | bellard | |
989 | c896fe29 | bellard | /***************************************/
|
990 | c896fe29 | bellard | static inline void tcg_gen_macro_2(int ret0, int ret1, int macro_id) |
991 | c896fe29 | bellard | { |
992 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_macro_2, ret0, ret1, macro_id); |
993 | c896fe29 | bellard | } |
994 | c896fe29 | bellard | |
995 | c896fe29 | bellard | /***************************************/
|
996 | c896fe29 | bellard | /* QEMU specific operations. Their type depend on the QEMU CPU
|
997 | c896fe29 | bellard | type. */
|
998 | c896fe29 | bellard | #ifndef TARGET_LONG_BITS
|
999 | c896fe29 | bellard | #error must include QEMU headers
|
1000 | c896fe29 | bellard | #endif
|
1001 | c896fe29 | bellard | |
1002 | c896fe29 | bellard | static inline void tcg_gen_exit_tb(tcg_target_long val) |
1003 | c896fe29 | bellard | { |
1004 | c896fe29 | bellard | tcg_gen_op1(INDEX_op_exit_tb, val); |
1005 | c896fe29 | bellard | } |
1006 | c896fe29 | bellard | |
1007 | c896fe29 | bellard | static inline void tcg_gen_goto_tb(int idx) |
1008 | c896fe29 | bellard | { |
1009 | c896fe29 | bellard | tcg_gen_op1(INDEX_op_goto_tb, idx); |
1010 | c896fe29 | bellard | } |
1011 | c896fe29 | bellard | |
1012 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
1013 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld8u(int ret, int addr, int mem_index) |
1014 | c896fe29 | bellard | { |
1015 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1016 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
1017 | c896fe29 | bellard | #else
|
1018 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_qemu_ld8u, ret, addr, addr + 1, mem_index);
|
1019 | c896fe29 | bellard | tcg_gen_movi_i32(ret + 1, 0); |
1020 | c896fe29 | bellard | #endif
|
1021 | c896fe29 | bellard | } |
1022 | c896fe29 | bellard | |
1023 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld8s(int ret, int addr, int mem_index) |
1024 | c896fe29 | bellard | { |
1025 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1026 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
1027 | c896fe29 | bellard | #else
|
1028 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_qemu_ld8s, ret, addr, addr + 1, mem_index);
|
1029 | c896fe29 | bellard | tcg_gen_ext8s_i32(ret + 1, ret);
|
1030 | c896fe29 | bellard | #endif
|
1031 | c896fe29 | bellard | } |
1032 | c896fe29 | bellard | |
1033 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld16u(int ret, int addr, int mem_index) |
1034 | c896fe29 | bellard | { |
1035 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1036 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
1037 | c896fe29 | bellard | #else
|
1038 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_qemu_ld16u, ret, addr, addr + 1, mem_index);
|
1039 | c896fe29 | bellard | tcg_gen_movi_i32(ret + 1, 0); |
1040 | c896fe29 | bellard | #endif
|
1041 | c896fe29 | bellard | } |
1042 | c896fe29 | bellard | |
1043 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld16s(int ret, int addr, int mem_index) |
1044 | c896fe29 | bellard | { |
1045 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1046 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
1047 | c896fe29 | bellard | #else
|
1048 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_qemu_ld16s, ret, addr, addr + 1, mem_index);
|
1049 | c896fe29 | bellard | tcg_gen_ext16s_i32(ret + 1, ret);
|
1050 | c896fe29 | bellard | #endif
|
1051 | c896fe29 | bellard | } |
1052 | c896fe29 | bellard | |
1053 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld32u(int ret, int addr, int mem_index) |
1054 | c896fe29 | bellard | { |
1055 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1056 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
1057 | c896fe29 | bellard | #else
|
1058 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_qemu_ld32u, ret, addr, addr + 1, mem_index);
|
1059 | c896fe29 | bellard | tcg_gen_movi_i32(ret + 1, 0); |
1060 | c896fe29 | bellard | #endif
|
1061 | c896fe29 | bellard | } |
1062 | c896fe29 | bellard | |
1063 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld32s(int ret, int addr, int mem_index) |
1064 | c896fe29 | bellard | { |
1065 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1066 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
1067 | c896fe29 | bellard | #else
|
1068 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_qemu_ld32u, ret, addr, addr + 1, mem_index);
|
1069 | c896fe29 | bellard | tcg_gen_sari_i32(ret + 1, ret, 31); |
1070 | c896fe29 | bellard | #endif
|
1071 | c896fe29 | bellard | } |
1072 | c896fe29 | bellard | |
1073 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld64(int ret, int addr, int mem_index) |
1074 | c896fe29 | bellard | { |
1075 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1076 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_qemu_ld64, ret, ret + 1, addr, mem_index);
|
1077 | c896fe29 | bellard | #else
|
1078 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_qemu_ld64, ret, ret + 1, addr, addr + 1, mem_index); |
1079 | c896fe29 | bellard | #endif
|
1080 | c896fe29 | bellard | } |
1081 | c896fe29 | bellard | |
1082 | c896fe29 | bellard | static inline void tcg_gen_qemu_st8(int arg, int addr, int mem_index) |
1083 | c896fe29 | bellard | { |
1084 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1085 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_st8, arg, addr, mem_index); |
1086 | c896fe29 | bellard | #else
|
1087 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_qemu_st8, arg, addr, addr + 1, mem_index);
|
1088 | c896fe29 | bellard | #endif
|
1089 | c896fe29 | bellard | } |
1090 | c896fe29 | bellard | |
1091 | c896fe29 | bellard | static inline void tcg_gen_qemu_st16(int arg, int addr, int mem_index) |
1092 | c896fe29 | bellard | { |
1093 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1094 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_st16, arg, addr, mem_index); |
1095 | c896fe29 | bellard | #else
|
1096 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_qemu_st16, arg, addr, addr + 1, mem_index);
|
1097 | c896fe29 | bellard | #endif
|
1098 | c896fe29 | bellard | } |
1099 | c896fe29 | bellard | |
1100 | c896fe29 | bellard | static inline void tcg_gen_qemu_st32(int arg, int addr, int mem_index) |
1101 | c896fe29 | bellard | { |
1102 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1103 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_st32, arg, addr, mem_index); |
1104 | c896fe29 | bellard | #else
|
1105 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_qemu_st32, arg, addr, addr + 1, mem_index);
|
1106 | c896fe29 | bellard | #endif
|
1107 | c896fe29 | bellard | } |
1108 | c896fe29 | bellard | |
1109 | c896fe29 | bellard | static inline void tcg_gen_qemu_st64(int arg, int addr, int mem_index) |
1110 | c896fe29 | bellard | { |
1111 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1112 | c896fe29 | bellard | tcg_gen_op4(INDEX_op_qemu_st64, arg, arg + 1, addr, mem_index);
|
1113 | c896fe29 | bellard | #else
|
1114 | c896fe29 | bellard | tcg_gen_op5(INDEX_op_qemu_st64, arg, arg + 1, addr, addr + 1, mem_index); |
1115 | c896fe29 | bellard | #endif
|
1116 | c896fe29 | bellard | } |
1117 | c896fe29 | bellard | |
1118 | c896fe29 | bellard | #else /* TCG_TARGET_REG_BITS == 32 */ |
1119 | c896fe29 | bellard | |
1120 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld8u(int ret, int addr, int mem_index) |
1121 | c896fe29 | bellard | { |
1122 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
1123 | c896fe29 | bellard | } |
1124 | c896fe29 | bellard | |
1125 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld8s(int ret, int addr, int mem_index) |
1126 | c896fe29 | bellard | { |
1127 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
1128 | c896fe29 | bellard | } |
1129 | c896fe29 | bellard | |
1130 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld16u(int ret, int addr, int mem_index) |
1131 | c896fe29 | bellard | { |
1132 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
1133 | c896fe29 | bellard | } |
1134 | c896fe29 | bellard | |
1135 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld16s(int ret, int addr, int mem_index) |
1136 | c896fe29 | bellard | { |
1137 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
1138 | c896fe29 | bellard | } |
1139 | c896fe29 | bellard | |
1140 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld32u(int ret, int addr, int mem_index) |
1141 | c896fe29 | bellard | { |
1142 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
1143 | c896fe29 | bellard | } |
1144 | c896fe29 | bellard | |
1145 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld32s(int ret, int addr, int mem_index) |
1146 | c896fe29 | bellard | { |
1147 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
1148 | c896fe29 | bellard | } |
1149 | c896fe29 | bellard | |
1150 | c896fe29 | bellard | static inline void tcg_gen_qemu_ld64(int ret, int addr, int mem_index) |
1151 | c896fe29 | bellard | { |
1152 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_ld64, ret, addr, mem_index); |
1153 | c896fe29 | bellard | } |
1154 | c896fe29 | bellard | |
1155 | c896fe29 | bellard | static inline void tcg_gen_qemu_st8(int arg, int addr, int mem_index) |
1156 | c896fe29 | bellard | { |
1157 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_st8, arg, addr, mem_index); |
1158 | c896fe29 | bellard | } |
1159 | c896fe29 | bellard | |
1160 | c896fe29 | bellard | static inline void tcg_gen_qemu_st16(int arg, int addr, int mem_index) |
1161 | c896fe29 | bellard | { |
1162 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_st16, arg, addr, mem_index); |
1163 | c896fe29 | bellard | } |
1164 | c896fe29 | bellard | |
1165 | c896fe29 | bellard | static inline void tcg_gen_qemu_st32(int arg, int addr, int mem_index) |
1166 | c896fe29 | bellard | { |
1167 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_st32, arg, addr, mem_index); |
1168 | c896fe29 | bellard | } |
1169 | c896fe29 | bellard | |
1170 | c896fe29 | bellard | static inline void tcg_gen_qemu_st64(int arg, int addr, int mem_index) |
1171 | c896fe29 | bellard | { |
1172 | c896fe29 | bellard | tcg_gen_op3(INDEX_op_qemu_st64, arg, addr, mem_index); |
1173 | c896fe29 | bellard | } |
1174 | c896fe29 | bellard | |
1175 | c896fe29 | bellard | #endif /* TCG_TARGET_REG_BITS != 32 */ |