## root / target-mips / translate_init.c @ 41db4607

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1 | 33d68b5f | ths | ```
/*
``` |
---|---|---|---|

2 | 33d68b5f | ths | ```
* MIPS emulation for qemu: CPU initialisation routines.
``` |

3 | 33d68b5f | ths | ```
*
``` |

4 | 33d68b5f | ths | ```
* Copyright (c) 2004-2005 Jocelyn Mayer
``` |

5 | 33d68b5f | ths | ```
* Copyright (c) 2007 Herve Poussineau
``` |

6 | 33d68b5f | ths | ```
*
``` |

7 | 33d68b5f | ths | ```
* This library is free software; you can redistribute it and/or
``` |

8 | 33d68b5f | ths | ```
* modify it under the terms of the GNU Lesser General Public
``` |

9 | 33d68b5f | ths | ```
* License as published by the Free Software Foundation; either
``` |

10 | 33d68b5f | ths | ```
* version 2 of the License, or (at your option) any later version.
``` |

11 | 33d68b5f | ths | ```
*
``` |

12 | 33d68b5f | ths | ```
* This library is distributed in the hope that it will be useful,
``` |

13 | 33d68b5f | ths | ```
* but WITHOUT ANY WARRANTY; without even the implied warranty of
``` |

14 | 33d68b5f | ths | ```
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
``` |

15 | 33d68b5f | ths | ```
* Lesser General Public License for more details.
``` |

16 | 33d68b5f | ths | ```
*
``` |

17 | 33d68b5f | ths | ```
* You should have received a copy of the GNU Lesser General Public
``` |

18 | 33d68b5f | ths | ```
* License along with this library; if not, write to the Free Software
``` |

19 | fad6cb1a | aurel32 | ```
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
``` |

20 | 33d68b5f | ths | ```
*/
``` |

21 | 33d68b5f | ths | |

22 | 3953d786 | ths | ```
/* CPU / CPU family specific config register values. */
``` |

23 | 3953d786 | ths | |

24 | 6d35524c | ths | ```
/* Have config1, uncached coherency */
``` |

25 | 3953d786 | ths | ```
#define MIPS_CONFIG0 \
``` |

26 | 6d35524c | ths | ((1 << CP0C0_M) | (0x2 << CP0C0_K0)) |

27 | 3953d786 | ths | |

28 | ae5d8053 | ths | ```
/* Have config2, no coprocessor2 attached, no MDMX support attached,
``` |

29 | 3953d786 | ths | ```
no performance counters, watch registers present,
``` |

30 | 3953d786 | ths | ```
no code compression, EJTAG present, no FPU */
``` |

31 | 3953d786 | ths | ```
#define MIPS_CONFIG1 \
``` |

32 | fcb4a419 | ths | ```
((1 << CP0C1_M) | \
``` |

33 | 3953d786 | ths | (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |

34 | 3953d786 | ths | (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ |

35 | 3953d786 | ths | ```
(0 << CP0C1_FP))
``` |

36 | 3953d786 | ths | |

37 | 3953d786 | ths | ```
/* Have config3, no tertiary/secondary caches implemented */
``` |

38 | 3953d786 | ths | ```
#define MIPS_CONFIG2 \
``` |

39 | 3953d786 | ths | ```
((1 << CP0C2_M))
``` |

40 | 3953d786 | ths | |

41 | 6d35524c | ths | ```
/* No config4, no DSP ASE, no large physaddr (PABITS),
``` |

42 | 3953d786 | ths | ```
no external interrupt controller, no vectored interupts,
``` |

43 | ead9360e | ths | ```
no 1kb pages, no SmartMIPS ASE, no trace logic */
``` |

44 | 3953d786 | ths | ```
#define MIPS_CONFIG3 \
``` |

45 | 3953d786 | ths | ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |

46 | 3953d786 | ths | (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |

47 | ead9360e | ths | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |

48 | 3953d786 | ths | |

49 | 3953d786 | ths | ```
/* Define a implementation number of 1.
``` |

50 | 3953d786 | ths | ```
Define a major version 1, minor version 0. */
``` |

51 | 5a5012ec | ths | #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV)) |

52 | 3953d786 | ths | |

53 | 6d35524c | ths | ```
/* MMU types, the first four entries have the same layout as the
``` |

54 | 6d35524c | ths | ```
CP0C0_MT field. */
``` |

55 | 6d35524c | ths | ```
enum mips_mmu_types {
``` |

56 | 6d35524c | ths | MMU_TYPE_NONE, |

57 | 6d35524c | ths | MMU_TYPE_R4000, |

58 | 6d35524c | ths | MMU_TYPE_RESERVED, |

59 | 6d35524c | ths | MMU_TYPE_FMT, |

60 | 6d35524c | ths | MMU_TYPE_R3000, |

61 | 6d35524c | ths | MMU_TYPE_R6000, |

62 | 6d35524c | ths | MMU_TYPE_R8000 |

63 | 6d35524c | ths | }; |

64 | 6d35524c | ths | |

65 | 33d68b5f | ths | ```
struct mips_def_t {
``` |

66 | 50366fe9 | ths | const char *name; |

67 | 33d68b5f | ths | int32_t CP0_PRid; |

68 | 33d68b5f | ths | int32_t CP0_Config0; |

69 | 33d68b5f | ths | int32_t CP0_Config1; |

70 | 3953d786 | ths | int32_t CP0_Config2; |

71 | 3953d786 | ths | int32_t CP0_Config3; |

72 | 34ee2ede | ths | int32_t CP0_Config6; |

73 | 34ee2ede | ths | int32_t CP0_Config7; |

74 | 2f644545 | ths | int32_t SYNCI_Step; |

75 | 2f644545 | ths | int32_t CCRes; |

76 | ead9360e | ths | int32_t CP0_Status_rw_bitmask; |

77 | ead9360e | ths | int32_t CP0_TCStatus_rw_bitmask; |

78 | ead9360e | ths | int32_t CP0_SRSCtl; |

79 | 3953d786 | ths | int32_t CP1_fcr0; |

80 | e034e2c3 | ths | int32_t SEGBITS; |

81 | 6d35524c | ths | int32_t PABITS; |

82 | ead9360e | ths | int32_t CP0_SRSConf0_rw_bitmask; |

83 | ead9360e | ths | int32_t CP0_SRSConf0; |

84 | ead9360e | ths | int32_t CP0_SRSConf1_rw_bitmask; |

85 | ead9360e | ths | int32_t CP0_SRSConf1; |

86 | ead9360e | ths | int32_t CP0_SRSConf2_rw_bitmask; |

87 | ead9360e | ths | int32_t CP0_SRSConf2; |

88 | ead9360e | ths | int32_t CP0_SRSConf3_rw_bitmask; |

89 | ead9360e | ths | int32_t CP0_SRSConf3; |

90 | ead9360e | ths | int32_t CP0_SRSConf4_rw_bitmask; |

91 | ead9360e | ths | int32_t CP0_SRSConf4; |

92 | e189e748 | ths | ```
int insn_flags;
``` |

93 | 6d35524c | ths | ```
enum mips_mmu_types mmu_type;
``` |

94 | 33d68b5f | ths | }; |

95 | 33d68b5f | ths | |

96 | 33d68b5f | ths | ```
/*****************************************************************************/
``` |

97 | 33d68b5f | ths | ```
/* MIPS CPU definitions */
``` |

98 | 8706c382 | ths | static const mips_def_t mips_defs[] = |

99 | 33d68b5f | ths | { |

100 | 33d68b5f | ths | { |

101 | 33d68b5f | ths | ```
.name = "4Kc",
``` |

102 | 33d68b5f | ths | ```
.CP0_PRid = 0x00018000,
``` |

103 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |

104 | ae5d8053 | ths | ```
.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
``` |

105 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |

106 | 6958549d | aurel32 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |

107 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |

108 | 3953d786 | ths | .CP0_Config3 = MIPS_CONFIG3, |

109 | 2f644545 | ths | ```
.SYNCI_Step = 32,
``` |

110 | 2f644545 | ths | ```
.CCRes = 2,
``` |

111 | ead9360e | ths | ```
.CP0_Status_rw_bitmask = 0x1278FF17,
``` |

112 | 6d35524c | ths | ```
.SEGBITS = 32,
``` |

113 | 6d35524c | ths | ```
.PABITS = 32,
``` |

114 | e189e748 | ths | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |

115 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |

116 | 33d68b5f | ths | }, |

117 | 33d68b5f | ths | { |

118 | 8d162c2b | ths | ```
.name = "4Km",
``` |

119 | 8d162c2b | ths | ```
.CP0_PRid = 0x00018300,
``` |

120 | 8d162c2b | ths | ```
/* Config1 implemented, fixed mapping MMU,
``` |

121 | 8d162c2b | ths | ```
no virtual icache, uncached coherency. */
``` |

122 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |

123 | 8d162c2b | ths | .CP0_Config1 = MIPS_CONFIG1 | |

124 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |

125 | 6958549d | aurel32 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |

126 | 8d162c2b | ths | .CP0_Config2 = MIPS_CONFIG2, |

127 | 8d162c2b | ths | .CP0_Config3 = MIPS_CONFIG3, |

128 | 8d162c2b | ths | ```
.SYNCI_Step = 32,
``` |

129 | 8d162c2b | ths | ```
.CCRes = 2,
``` |

130 | 8d162c2b | ths | ```
.CP0_Status_rw_bitmask = 0x1258FF17,
``` |

131 | 6d35524c | ths | ```
.SEGBITS = 32,
``` |

132 | 6d35524c | ths | ```
.PABITS = 32,
``` |

133 | 8d162c2b | ths | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |

134 | 6d35524c | ths | .mmu_type = MMU_TYPE_FMT, |

135 | 8d162c2b | ths | }, |

136 | 8d162c2b | ths | { |

137 | 34ee2ede | ths | ```
.name = "4KEcR1",
``` |

138 | 33d68b5f | ths | ```
.CP0_PRid = 0x00018400,
``` |

139 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |

140 | ae5d8053 | ths | ```
.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
``` |

141 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |

142 | 6958549d | aurel32 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |

143 | 34ee2ede | ths | .CP0_Config2 = MIPS_CONFIG2, |

144 | 34ee2ede | ths | .CP0_Config3 = MIPS_CONFIG3, |

145 | 2f644545 | ths | ```
.SYNCI_Step = 32,
``` |

146 | 2f644545 | ths | ```
.CCRes = 2,
``` |

147 | ead9360e | ths | ```
.CP0_Status_rw_bitmask = 0x1278FF17,
``` |

148 | 6d35524c | ths | ```
.SEGBITS = 32,
``` |

149 | 6d35524c | ths | ```
.PABITS = 32,
``` |

150 | e189e748 | ths | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |

151 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |

152 | 34ee2ede | ths | }, |

153 | 34ee2ede | ths | { |

154 | 8d162c2b | ths | ```
.name = "4KEmR1",
``` |

155 | 8d162c2b | ths | ```
.CP0_PRid = 0x00018500,
``` |

156 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |

157 | 8d162c2b | ths | .CP0_Config1 = MIPS_CONFIG1 | |

158 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |

159 | 6958549d | aurel32 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |

160 | 8d162c2b | ths | .CP0_Config2 = MIPS_CONFIG2, |

161 | 8d162c2b | ths | .CP0_Config3 = MIPS_CONFIG3, |

162 | 8d162c2b | ths | ```
.SYNCI_Step = 32,
``` |

163 | 8d162c2b | ths | ```
.CCRes = 2,
``` |

164 | 8d162c2b | ths | ```
.CP0_Status_rw_bitmask = 0x1258FF17,
``` |

165 | 6d35524c | ths | ```
.SEGBITS = 32,
``` |

166 | 6d35524c | ths | ```
.PABITS = 32,
``` |

167 | 8d162c2b | ths | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |

168 | 6d35524c | ths | .mmu_type = MMU_TYPE_FMT, |

169 | 8d162c2b | ths | }, |

170 | 8d162c2b | ths | { |

171 | 34ee2ede | ths | ```
.name = "4KEc",
``` |

172 | 34ee2ede | ths | ```
.CP0_PRid = 0x00019000,
``` |

173 | 6d35524c | ths | ```
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
``` |

174 | 6d35524c | ths | (MMU_TYPE_R4000 << CP0C0_MT), |

175 | ae5d8053 | ths | ```
.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
``` |

176 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |

177 | 6958549d | aurel32 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |

178 | 34ee2ede | ths | .CP0_Config2 = MIPS_CONFIG2, |

179 | ead9360e | ths | ```
.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
``` |

180 | 2f644545 | ths | ```
.SYNCI_Step = 32,
``` |

181 | 2f644545 | ths | ```
.CCRes = 2,
``` |

182 | ead9360e | ths | ```
.CP0_Status_rw_bitmask = 0x1278FF17,
``` |

183 | 6d35524c | ths | ```
.SEGBITS = 32,
``` |

184 | 6d35524c | ths | ```
.PABITS = 32,
``` |

185 | e189e748 | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |

186 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |

187 | 34ee2ede | ths | }, |

188 | 34ee2ede | ths | { |

189 | 3e4587d5 | ths | ```
.name = "4KEm",
``` |

190 | 3e4587d5 | ths | ```
.CP0_PRid = 0x00019100,
``` |

191 | 6d35524c | ths | ```
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
``` |

192 | 6958549d | aurel32 | (MMU_TYPE_FMT << CP0C0_MT), |

193 | 3e4587d5 | ths | .CP0_Config1 = MIPS_CONFIG1 | |

194 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |

195 | 6958549d | aurel32 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |

196 | 3e4587d5 | ths | .CP0_Config2 = MIPS_CONFIG2, |

197 | 3e4587d5 | ths | .CP0_Config3 = MIPS_CONFIG3, |

198 | 3e4587d5 | ths | ```
.SYNCI_Step = 32,
``` |

199 | 3e4587d5 | ths | ```
.CCRes = 2,
``` |

200 | 3e4587d5 | ths | ```
.CP0_Status_rw_bitmask = 0x1258FF17,
``` |

201 | 6d35524c | ths | ```
.SEGBITS = 32,
``` |

202 | 6d35524c | ths | ```
.PABITS = 32,
``` |

203 | 3e4587d5 | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |

204 | 6d35524c | ths | .mmu_type = MMU_TYPE_FMT, |

205 | 3e4587d5 | ths | }, |

206 | 3e4587d5 | ths | { |

207 | 34ee2ede | ths | ```
.name = "24Kc",
``` |

208 | 34ee2ede | ths | ```
.CP0_PRid = 0x00019300,
``` |

209 | 6d35524c | ths | ```
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
``` |

210 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |

211 | ae5d8053 | ths | ```
.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
``` |

212 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |

213 | 6958549d | aurel32 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |

214 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |

215 | ead9360e | ths | ```
.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
``` |

216 | 2f644545 | ths | ```
.SYNCI_Step = 32,
``` |

217 | 2f644545 | ths | ```
.CCRes = 2,
``` |

218 | ead9360e | ths | ```
/* No DSP implemented. */
``` |

219 | 671880e6 | ths | ```
.CP0_Status_rw_bitmask = 0x1278FF1F,
``` |

220 | 6d35524c | ths | ```
.SEGBITS = 32,
``` |

221 | 6d35524c | ths | ```
.PABITS = 32,
``` |

222 | 3e4587d5 | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |

223 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |

224 | 33d68b5f | ths | }, |

225 | 33d68b5f | ths | { |

226 | 33d68b5f | ths | ```
.name = "24Kf",
``` |

227 | 33d68b5f | ths | ```
.CP0_PRid = 0x00019300,
``` |

228 | 6d35524c | ths | ```
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
``` |

229 | 6d35524c | ths | (MMU_TYPE_R4000 << CP0C0_MT), |

230 | ae5d8053 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |

231 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |

232 | 6958549d | aurel32 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |

233 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |

234 | ead9360e | ths | ```
.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
``` |

235 | 2f644545 | ths | ```
.SYNCI_Step = 32,
``` |

236 | 2f644545 | ths | ```
.CCRes = 2,
``` |

237 | ead9360e | ths | ```
/* No DSP implemented. */
``` |

238 | 671880e6 | ths | ```
.CP0_Status_rw_bitmask = 0x3678FF1F,
``` |

239 | 5a5012ec | ths | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |

240 | 5a5012ec | ths | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |

241 | 6d35524c | ths | ```
.SEGBITS = 32,
``` |

242 | 6d35524c | ths | ```
.PABITS = 32,
``` |

243 | 3e4587d5 | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |

244 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |

245 | 33d68b5f | ths | }, |

246 | ead9360e | ths | { |

247 | ead9360e | ths | ```
.name = "34Kf",
``` |

248 | ead9360e | ths | ```
.CP0_PRid = 0x00019500,
``` |

249 | 6d35524c | ths | ```
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
``` |

250 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |

251 | ead9360e | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |

252 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |

253 | 6958549d | aurel32 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |

254 | ead9360e | ths | .CP0_Config2 = MIPS_CONFIG2, |

255 | ead9360e | ths | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT), |

256 | ead9360e | ths | ```
.SYNCI_Step = 32,
``` |

257 | ead9360e | ths | ```
.CCRes = 2,
``` |

258 | ead9360e | ths | ```
/* No DSP implemented. */
``` |

259 | 671880e6 | ths | ```
.CP0_Status_rw_bitmask = 0x3678FF1F,
``` |

260 | ead9360e | ths | ```
/* No DSP implemented. */
``` |

261 | ead9360e | ths | .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | |

262 | ead9360e | ths | (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | |

263 | ead9360e | ths | (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | |

264 | ead9360e | ths | (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | |

265 | ead9360e | ths | (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | |

266 | ead9360e | ths | ```
(0xff << CP0TCSt_TASID),
``` |

267 | ead9360e | ths | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |

268 | ead9360e | ths | (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), |

269 | ead9360e | ths | ```
.CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
``` |

270 | ead9360e | ths | ```
.CP0_SRSConf0_rw_bitmask = 0x3fffffff,
``` |

271 | ead9360e | ths | .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | |

272 | ead9360e | ths | (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), |

273 | ead9360e | ths | ```
.CP0_SRSConf1_rw_bitmask = 0x3fffffff,
``` |

274 | ead9360e | ths | .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | |

275 | ead9360e | ths | (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), |

276 | ead9360e | ths | ```
.CP0_SRSConf2_rw_bitmask = 0x3fffffff,
``` |

277 | ead9360e | ths | .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | |

278 | ead9360e | ths | (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), |

279 | ead9360e | ths | ```
.CP0_SRSConf3_rw_bitmask = 0x3fffffff,
``` |

280 | ead9360e | ths | .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | |

281 | ead9360e | ths | (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), |

282 | ead9360e | ths | ```
.CP0_SRSConf4_rw_bitmask = 0x3fffffff,
``` |

283 | ead9360e | ths | ```
.CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
``` |

284 | ead9360e | ths | (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), |

285 | 6d35524c | ths | ```
.SEGBITS = 32,
``` |

286 | 6d35524c | ths | ```
.PABITS = 32,
``` |

287 | 7385ac0b | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, |

288 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |

289 | ead9360e | ths | }, |

290 | d26bc211 | ths | ```
#if defined(TARGET_MIPS64)
``` |

291 | 33d68b5f | ths | { |

292 | 33d68b5f | ths | ```
.name = "R4000",
``` |

293 | 33d68b5f | ths | ```
.CP0_PRid = 0x00000400,
``` |

294 | 6d35524c | ths | ```
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
``` |

295 | 6d35524c | ths | .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |

296 | 6958549d | aurel32 | ```
/* Note: Config1 is only used internally, the R4000 has only Config0. */
``` |

297 | 6d35524c | ths | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |

298 | 2f644545 | ths | ```
.SYNCI_Step = 16,
``` |

299 | 2f644545 | ths | ```
.CCRes = 2,
``` |

300 | ead9360e | ths | ```
.CP0_Status_rw_bitmask = 0x3678FFFF,
``` |

301 | 6958549d | aurel32 | ```
/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
``` |

302 | c9c1a064 | ths | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |

303 | e034e2c3 | ths | ```
.SEGBITS = 40,
``` |

304 | 6d35524c | ths | ```
.PABITS = 36,
``` |

305 | e189e748 | ths | .insn_flags = CPU_MIPS3, |

306 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |

307 | c9c1a064 | ths | }, |

308 | e9c71dd1 | ths | { |

309 | e9c71dd1 | ths | ```
.name = "VR5432",
``` |

310 | e9c71dd1 | ths | ```
.CP0_PRid = 0x00005400,
``` |

311 | e9c71dd1 | ths | ```
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
``` |

312 | e9c71dd1 | ths | .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |

313 | e9c71dd1 | ths | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |

314 | e9c71dd1 | ths | ```
.SYNCI_Step = 16,
``` |

315 | e9c71dd1 | ths | ```
.CCRes = 2,
``` |

316 | e9c71dd1 | ths | ```
.CP0_Status_rw_bitmask = 0x3678FFFF,
``` |

317 | e9c71dd1 | ths | ```
/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
``` |

318 | e9c71dd1 | ths | .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), |

319 | e9c71dd1 | ths | ```
.SEGBITS = 40,
``` |

320 | e9c71dd1 | ths | ```
.PABITS = 32,
``` |

321 | e9c71dd1 | ths | .insn_flags = CPU_VR54XX, |

322 | e9c71dd1 | ths | .mmu_type = MMU_TYPE_R4000, |

323 | e9c71dd1 | ths | }, |

324 | c9c1a064 | ths | { |

325 | c9c1a064 | ths | ```
.name = "5Kc",
``` |

326 | c9c1a064 | ths | ```
.CP0_PRid = 0x00018100,
``` |

327 | 29fe0e34 | ths | ```
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
``` |

328 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |

329 | c9c1a064 | ths | ```
.CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
``` |

330 | 6958549d | aurel32 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |

331 | 6958549d | aurel32 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |

332 | 6958549d | aurel32 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |

333 | c9c1a064 | ths | .CP0_Config2 = MIPS_CONFIG2, |

334 | c9c1a064 | ths | .CP0_Config3 = MIPS_CONFIG3, |

335 | c9c1a064 | ths | ```
.SYNCI_Step = 32,
``` |

336 | c9c1a064 | ths | ```
.CCRes = 2,
``` |

337 | ead9360e | ths | ```
.CP0_Status_rw_bitmask = 0x32F8FFFF,
``` |

338 | e034e2c3 | ths | ```
.SEGBITS = 42,
``` |

339 | 6d35524c | ths | ```
.PABITS = 36,
``` |

340 | e189e748 | ths | .insn_flags = CPU_MIPS64, |

341 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |

342 | c9c1a064 | ths | }, |

343 | c9c1a064 | ths | { |

344 | c9c1a064 | ths | ```
.name = "5Kf",
``` |

345 | c9c1a064 | ths | ```
.CP0_PRid = 0x00018100,
``` |

346 | 29fe0e34 | ths | ```
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
``` |

347 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |

348 | c9c1a064 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |

349 | 6958549d | aurel32 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |

350 | 6958549d | aurel32 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |

351 | 6958549d | aurel32 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |

352 | c9c1a064 | ths | .CP0_Config2 = MIPS_CONFIG2, |

353 | c9c1a064 | ths | .CP0_Config3 = MIPS_CONFIG3, |

354 | c9c1a064 | ths | ```
.SYNCI_Step = 32,
``` |

355 | c9c1a064 | ths | ```
.CCRes = 2,
``` |

356 | ead9360e | ths | ```
.CP0_Status_rw_bitmask = 0x36F8FFFF,
``` |

357 | 6958549d | aurel32 | ```
/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
``` |

358 | c9c1a064 | ths | .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |

359 | c9c1a064 | ths | (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |

360 | e034e2c3 | ths | ```
.SEGBITS = 42,
``` |

361 | 6d35524c | ths | ```
.PABITS = 36,
``` |

362 | e189e748 | ths | .insn_flags = CPU_MIPS64, |

363 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |

364 | c9c1a064 | ths | }, |

365 | c9c1a064 | ths | { |

366 | c9c1a064 | ths | ```
.name = "20Kc",
``` |

367 | 6958549d | aurel32 | ```
/* We emulate a later version of the 20Kc, earlier ones had a broken
``` |

368 | bd04c6fe | ths | ```
WAIT instruction. */
``` |

369 | bd04c6fe | ths | ```
.CP0_PRid = 0x000182a0,
``` |

370 | 29fe0e34 | ths | ```
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
``` |

371 | 6d35524c | ths | ```
(MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
``` |

372 | c9c1a064 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | |

373 | 6958549d | aurel32 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |

374 | 6958549d | aurel32 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |

375 | 6958549d | aurel32 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |

376 | c9c1a064 | ths | .CP0_Config2 = MIPS_CONFIG2, |

377 | c9c1a064 | ths | .CP0_Config3 = MIPS_CONFIG3, |

378 | c9c1a064 | ths | ```
.SYNCI_Step = 32,
``` |

379 | a1daafd8 | ths | ```
.CCRes = 1,
``` |

380 | ead9360e | ths | ```
.CP0_Status_rw_bitmask = 0x36FBFFFF,
``` |

381 | 6958549d | aurel32 | ```
/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
``` |

382 | c9c1a064 | ths | .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |

383 | 5a5012ec | ths | (1 << FCR0_D) | (1 << FCR0_S) | |

384 | c9c1a064 | ths | (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |

385 | e034e2c3 | ths | ```
.SEGBITS = 40,
``` |

386 | 6d35524c | ths | ```
.PABITS = 36,
``` |

387 | e189e748 | ths | .insn_flags = CPU_MIPS64 | ASE_MIPS3D, |

388 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |

389 | 33d68b5f | ths | }, |

390 | d2123ead | ths | { |

391 | 6958549d | aurel32 | ```
/* A generic CPU providing MIPS64 Release 2 features.
``` |

392 | d2123ead | ths | ```
FIXME: Eventually this should be replaced by a real CPU model. */
``` |

393 | d2123ead | ths | ```
.name = "MIPS64R2-generic",
``` |

394 | 8c89395e | ths | ```
.CP0_PRid = 0x00010000,
``` |

395 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |

396 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |

397 | d2123ead | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |

398 | 6958549d | aurel32 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |

399 | 6958549d | aurel32 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |

400 | 6958549d | aurel32 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |

401 | d2123ead | ths | .CP0_Config2 = MIPS_CONFIG2, |

402 | 6d35524c | ths | ```
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
``` |

403 | d2123ead | ths | ```
.SYNCI_Step = 32,
``` |

404 | d2123ead | ths | ```
.CCRes = 2,
``` |

405 | d2123ead | ths | ```
.CP0_Status_rw_bitmask = 0x36FBFFFF,
``` |

406 | ea4b07f7 | ths | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |

407 | ea4b07f7 | ths | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |

408 | ea4b07f7 | ths | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |

409 | 6d35524c | ths | ```
.SEGBITS = 42,
``` |

410 | 6d35524c | ths | ```
/* The architectural limit is 59, but we have hardcoded 36 bit
``` |

411 | 6d35524c | ths | ```
in some places...
``` |

412 | 6d35524c | ths | .PABITS = 59, */ /* the architectural limit */ |

413 | 6d35524c | ths | ```
.PABITS = 36,
``` |

414 | d2123ead | ths | .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, |

415 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |

416 | d2123ead | ths | }, |

417 | 33d68b5f | ths | ```
#endif
``` |

418 | 33d68b5f | ths | }; |

419 | 33d68b5f | ths | |

420 | 929a62a0 | aurel32 | static const mips_def_t *cpu_mips_find_by_name (const char *name) |

421 | 33d68b5f | ths | { |

422 | aaed909a | bellard | ```
int i;
``` |

423 | 33d68b5f | ths | |

424 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |

425 | 33d68b5f | ths | if (strcasecmp(name, mips_defs[i].name) == 0) { |

426 | aaed909a | bellard | ```
return &mips_defs[i];
``` |

427 | 33d68b5f | ths | } |

428 | 33d68b5f | ths | } |

429 | aaed909a | bellard | return NULL; |

430 | 33d68b5f | ths | } |

431 | 33d68b5f | ths | |

432 | 33d68b5f | ths | void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |

433 | 33d68b5f | ths | { |

434 | 33d68b5f | ths | ```
int i;
``` |

435 | 33d68b5f | ths | |

436 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |

437 | 33d68b5f | ths | ```
(*cpu_fprintf)(f, "MIPS '%s'\n",
``` |

438 | 33d68b5f | ths | mips_defs[i].name); |

439 | 33d68b5f | ths | } |

440 | 33d68b5f | ths | } |

441 | 33d68b5f | ths | |

442 | f8a6ec58 | ths | ```
#ifndef CONFIG_USER_ONLY
``` |

443 | aaed909a | bellard | static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) |

444 | 29929e34 | ths | { |

445 | ead9360e | ths | ```
env->tlb->nb_tlb = 1;
``` |

446 | ead9360e | ths | env->tlb->map_address = &no_mmu_map_address; |

447 | 29929e34 | ths | } |

448 | 29929e34 | ths | |

449 | aaed909a | bellard | static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) |

450 | 29929e34 | ths | { |

451 | ead9360e | ths | ```
env->tlb->nb_tlb = 1;
``` |

452 | ead9360e | ths | env->tlb->map_address = &fixed_mmu_map_address; |

453 | 29929e34 | ths | } |

454 | 29929e34 | ths | |

455 | aaed909a | bellard | static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) |

456 | 29929e34 | ths | { |

457 | ead9360e | ths | env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |

458 | ead9360e | ths | env->tlb->map_address = &r4k_map_address; |

459 | c01fccd2 | aurel32 | env->tlb->helper_tlbwi = r4k_helper_tlbwi; |

460 | c01fccd2 | aurel32 | env->tlb->helper_tlbwr = r4k_helper_tlbwr; |

461 | c01fccd2 | aurel32 | env->tlb->helper_tlbp = r4k_helper_tlbp; |

462 | c01fccd2 | aurel32 | env->tlb->helper_tlbr = r4k_helper_tlbr; |

463 | ead9360e | ths | } |

464 | ead9360e | ths | |

465 | aaed909a | bellard | static void mmu_init (CPUMIPSState *env, const mips_def_t *def) |

466 | ead9360e | ths | { |

467 | ead9360e | ths | ```
env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
``` |

468 | ead9360e | ths | |

469 | 6d35524c | ths | ```
switch (def->mmu_type) {
``` |

470 | 6d35524c | ths | ```
case MMU_TYPE_NONE:
``` |

471 | ead9360e | ths | no_mmu_init(env, def); |

472 | ead9360e | ths | ```
break;
``` |

473 | 6d35524c | ths | ```
case MMU_TYPE_R4000:
``` |

474 | ead9360e | ths | r4k_mmu_init(env, def); |

475 | ead9360e | ths | ```
break;
``` |

476 | 6d35524c | ths | ```
case MMU_TYPE_FMT:
``` |

477 | ead9360e | ths | fixed_mmu_init(env, def); |

478 | ead9360e | ths | ```
break;
``` |

479 | 6d35524c | ths | ```
case MMU_TYPE_R3000:
``` |

480 | 6d35524c | ths | ```
case MMU_TYPE_R6000:
``` |

481 | 6d35524c | ths | ```
case MMU_TYPE_R8000:
``` |

482 | ead9360e | ths | ```
default:
``` |

483 | ead9360e | ths | ```
cpu_abort(env, "MMU type not supported\n");
``` |

484 | ead9360e | ths | } |

485 | ead9360e | ths | ```
env->CP0_Random = env->tlb->nb_tlb - 1;
``` |

486 | ead9360e | ths | env->tlb->tlb_in_use = env->tlb->nb_tlb; |

487 | 29929e34 | ths | } |

488 | f8a6ec58 | ths | #endif /* CONFIG_USER_ONLY */ |

489 | 29929e34 | ths | |

490 | aaed909a | bellard | static void fpu_init (CPUMIPSState *env, const mips_def_t *def) |

491 | ead9360e | ths | { |

492 | f01be154 | ths | ```
int i;
``` |

493 | f01be154 | ths | |

494 | f01be154 | ths | for (i = 0; i < MIPS_FPU_MAX; i++) |

495 | f01be154 | ths | env->fpus[i].fcr0 = def->CP1_fcr0; |

496 | ead9360e | ths | |

497 | f01be154 | ths | memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); |

498 | 932e71cd | aurel32 | ```
#if defined(CONFIG_USER_ONLY)
``` |

499 | 932e71cd | aurel32 | if (env->CP0_Config1 & (1 << CP0C1_FP)) |

500 | 932e71cd | aurel32 | env->hflags |= MIPS_HFLAG_FPU; |

501 | 36271893 | ths | ```
#ifdef TARGET_MIPS64
``` |

502 | 932e71cd | aurel32 | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |

503 | 932e71cd | aurel32 | env->hflags |= MIPS_HFLAG_F64; |

504 | 932e71cd | aurel32 | ```
#endif
``` |

505 | 36271893 | ths | ```
#endif
``` |

506 | ead9360e | ths | } |

507 | ead9360e | ths | |

508 | aaed909a | bellard | static void mvp_init (CPUMIPSState *env, const mips_def_t *def) |

509 | ead9360e | ths | { |

510 | ead9360e | ths | ```
env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
``` |

511 | ead9360e | ths | |

512 | ead9360e | ths | ```
/* MVPConf1 implemented, TLB sharable, no gating storage support,
``` |

513 | ead9360e | ths | ```
programmable cache partitioning implemented, number of allocatable
``` |

514 | ead9360e | ths | ```
and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
``` |

515 | ead9360e | ths | ```
implemented, 5 TCs implemented. */
``` |

516 | ead9360e | ths | env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | |

517 | ead9360e | ths | (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | |

518 | ead9360e | ths | ```
// TODO: actually do 2 VPEs.
``` |

519 | ead9360e | ths | ```
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
``` |

520 | ead9360e | ths | ```
// (0x04 << CP0MVPC0_PTC);
``` |

521 | ead9360e | ths | (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | |

522 | ead9360e | ths | ```
(0x04 << CP0MVPC0_PTC);
``` |

523 | 932e71cd | aurel32 | ```
#if !defined(CONFIG_USER_ONLY)
``` |

524 | 0eaef5aa | ths | ```
/* Usermode has no TLB support */
``` |

525 | 932e71cd | aurel32 | env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); |

526 | 932e71cd | aurel32 | ```
#endif
``` |

527 | 0eaef5aa | ths | |

528 | ead9360e | ths | ```
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
``` |

529 | ead9360e | ths | ```
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
``` |

530 | ead9360e | ths | env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | |

531 | ead9360e | ths | (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | |

532 | ead9360e | ths | ```
(0x1 << CP0MVPC1_PCP1);
``` |

533 | ead9360e | ths | } |

534 | ead9360e | ths | |

535 | aaed909a | bellard | static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def) |

536 | 33d68b5f | ths | { |

537 | 33d68b5f | ths | env->CP0_PRid = def->CP0_PRid; |

538 | 33d68b5f | ths | env->CP0_Config0 = def->CP0_Config0; |

539 | 51b2772f | ths | ```
#ifdef TARGET_WORDS_BIGENDIAN
``` |

540 | 51b2772f | ths | ```
env->CP0_Config0 |= (1 << CP0C0_BE);
``` |

541 | 3953d786 | ths | ```
#endif
``` |

542 | 33d68b5f | ths | env->CP0_Config1 = def->CP0_Config1; |

543 | 3953d786 | ths | env->CP0_Config2 = def->CP0_Config2; |

544 | 3953d786 | ths | env->CP0_Config3 = def->CP0_Config3; |

545 | 34ee2ede | ths | env->CP0_Config6 = def->CP0_Config6; |

546 | 34ee2ede | ths | env->CP0_Config7 = def->CP0_Config7; |

547 | 2f644545 | ths | env->SYNCI_Step = def->SYNCI_Step; |

548 | 2f644545 | ths | env->CCRes = def->CCRes; |

549 | ead9360e | ths | env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask; |

550 | ead9360e | ths | env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask; |

551 | ead9360e | ths | env->CP0_SRSCtl = def->CP0_SRSCtl; |

552 | 958fb4a9 | ths | ```
env->current_tc = 0;
``` |

553 | 6d35524c | ths | env->SEGBITS = def->SEGBITS; |

554 | 6d35524c | ths | env->SEGMask = (target_ulong)((1ULL << def->SEGBITS) - 1); |

555 | d26bc211 | ths | ```
#if defined(TARGET_MIPS64)
``` |

556 | 6d35524c | ths | ```
if (def->insn_flags & ISA_MIPS3) {
``` |

557 | 3ddf0b5c | ths | env->hflags |= MIPS_HFLAG_64; |

558 | 6d35524c | ths | env->SEGMask |= 3ULL << 62; |

559 | 3ddf0b5c | ths | } |

560 | e034e2c3 | ths | ```
#endif
``` |

561 | 6d35524c | ths | env->PABITS = def->PABITS; |

562 | 6d35524c | ths | env->PAMask = (target_ulong)((1ULL << def->PABITS) - 1); |

563 | ead9360e | ths | env->CP0_SRSConf0_rw_bitmask = def->CP0_SRSConf0_rw_bitmask; |

564 | ead9360e | ths | env->CP0_SRSConf0 = def->CP0_SRSConf0; |

565 | ead9360e | ths | env->CP0_SRSConf1_rw_bitmask = def->CP0_SRSConf1_rw_bitmask; |

566 | ead9360e | ths | env->CP0_SRSConf1 = def->CP0_SRSConf1; |

567 | ead9360e | ths | env->CP0_SRSConf2_rw_bitmask = def->CP0_SRSConf2_rw_bitmask; |

568 | ead9360e | ths | env->CP0_SRSConf2 = def->CP0_SRSConf2; |

569 | ead9360e | ths | env->CP0_SRSConf3_rw_bitmask = def->CP0_SRSConf3_rw_bitmask; |

570 | ead9360e | ths | env->CP0_SRSConf3 = def->CP0_SRSConf3; |

571 | ead9360e | ths | env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask; |

572 | ead9360e | ths | env->CP0_SRSConf4 = def->CP0_SRSConf4; |

573 | e189e748 | ths | env->insn_flags = def->insn_flags; |

574 | ead9360e | ths | |

575 | f8a6ec58 | ths | ```
#ifndef CONFIG_USER_ONLY
``` |

576 | 932e71cd | aurel32 | mmu_init(env, def); |

577 | f8a6ec58 | ths | ```
#endif
``` |

578 | ead9360e | ths | fpu_init(env, def); |

579 | ead9360e | ths | mvp_init(env, def); |

580 | 33d68b5f | ths | return 0; |

581 | 33d68b5f | ths | } |