root / target-s390x / helper.c @ 420840e5
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1 | 10ec5117 | Alexander Graf | /*
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2 | 10ec5117 | Alexander Graf | * S/390 helpers
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3 | 10ec5117 | Alexander Graf | *
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4 | 10ec5117 | Alexander Graf | * Copyright (c) 2009 Ulrich Hecht
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5 | d5a43964 | Alexander Graf | * Copyright (c) 2011 Alexander Graf
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6 | 10ec5117 | Alexander Graf | *
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7 | 10ec5117 | Alexander Graf | * This library is free software; you can redistribute it and/or
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8 | 10ec5117 | Alexander Graf | * modify it under the terms of the GNU Lesser General Public
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9 | 10ec5117 | Alexander Graf | * License as published by the Free Software Foundation; either
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10 | 10ec5117 | Alexander Graf | * version 2 of the License, or (at your option) any later version.
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11 | 10ec5117 | Alexander Graf | *
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12 | 10ec5117 | Alexander Graf | * This library is distributed in the hope that it will be useful,
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13 | 10ec5117 | Alexander Graf | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 10ec5117 | Alexander Graf | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 10ec5117 | Alexander Graf | * Lesser General Public License for more details.
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16 | 10ec5117 | Alexander Graf | *
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17 | 10ec5117 | Alexander Graf | * You should have received a copy of the GNU Lesser General Public
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18 | 70539e18 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 10ec5117 | Alexander Graf | */
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20 | 10ec5117 | Alexander Graf | |
21 | 10ec5117 | Alexander Graf | #include "cpu.h" |
22 | 022c62cb | Paolo Bonzini | #include "exec/gdbstub.h" |
23 | 1de7afc9 | Paolo Bonzini | #include "qemu/timer.h" |
24 | ef81522b | Alexander Graf | #ifndef CONFIG_USER_ONLY
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25 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
26 | ef81522b | Alexander Graf | #endif
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27 | 10ec5117 | Alexander Graf | |
28 | d5a43964 | Alexander Graf | //#define DEBUG_S390
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29 | d5a43964 | Alexander Graf | //#define DEBUG_S390_PTE
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30 | d5a43964 | Alexander Graf | //#define DEBUG_S390_STDOUT
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31 | d5a43964 | Alexander Graf | |
32 | d5a43964 | Alexander Graf | #ifdef DEBUG_S390
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33 | d5a43964 | Alexander Graf | #ifdef DEBUG_S390_STDOUT
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34 | d5a43964 | Alexander Graf | #define DPRINTF(fmt, ...) \
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35 | d5a43964 | Alexander Graf | do { fprintf(stderr, fmt, ## __VA_ARGS__); \ |
36 | d5a43964 | Alexander Graf | qemu_log(fmt, ##__VA_ARGS__); } while (0) |
37 | d5a43964 | Alexander Graf | #else
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38 | d5a43964 | Alexander Graf | #define DPRINTF(fmt, ...) \
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39 | d5a43964 | Alexander Graf | do { qemu_log(fmt, ## __VA_ARGS__); } while (0) |
40 | d5a43964 | Alexander Graf | #endif
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41 | d5a43964 | Alexander Graf | #else
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42 | d5a43964 | Alexander Graf | #define DPRINTF(fmt, ...) \
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43 | d5a43964 | Alexander Graf | do { } while (0) |
44 | d5a43964 | Alexander Graf | #endif
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45 | d5a43964 | Alexander Graf | |
46 | d5a43964 | Alexander Graf | #ifdef DEBUG_S390_PTE
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47 | d5a43964 | Alexander Graf | #define PTE_DPRINTF DPRINTF
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48 | d5a43964 | Alexander Graf | #else
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49 | d5a43964 | Alexander Graf | #define PTE_DPRINTF(fmt, ...) \
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50 | d5a43964 | Alexander Graf | do { } while (0) |
51 | d5a43964 | Alexander Graf | #endif
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52 | d5a43964 | Alexander Graf | |
53 | d5a43964 | Alexander Graf | #ifndef CONFIG_USER_ONLY
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54 | 8f22e0df | Andreas Färber | void s390x_tod_timer(void *opaque) |
55 | d5a43964 | Alexander Graf | { |
56 | b8ba6799 | Andreas Färber | S390CPU *cpu = opaque; |
57 | b8ba6799 | Andreas Färber | CPUS390XState *env = &cpu->env; |
58 | d5a43964 | Alexander Graf | |
59 | d5a43964 | Alexander Graf | env->pending_int |= INTERRUPT_TOD; |
60 | c3affe56 | Andreas Färber | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); |
61 | d5a43964 | Alexander Graf | } |
62 | d5a43964 | Alexander Graf | |
63 | 8f22e0df | Andreas Färber | void s390x_cpu_timer(void *opaque) |
64 | d5a43964 | Alexander Graf | { |
65 | b8ba6799 | Andreas Färber | S390CPU *cpu = opaque; |
66 | b8ba6799 | Andreas Färber | CPUS390XState *env = &cpu->env; |
67 | d5a43964 | Alexander Graf | |
68 | d5a43964 | Alexander Graf | env->pending_int |= INTERRUPT_CPUTIMER; |
69 | c3affe56 | Andreas Färber | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); |
70 | d5a43964 | Alexander Graf | } |
71 | d5a43964 | Alexander Graf | #endif
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72 | 10c339a0 | Alexander Graf | |
73 | 564b863d | Andreas Färber | S390CPU *cpu_s390x_init(const char *cpu_model) |
74 | 10ec5117 | Alexander Graf | { |
75 | 29e4bcb2 | Andreas Färber | S390CPU *cpu; |
76 | 10ec5117 | Alexander Graf | CPUS390XState *env; |
77 | 10ec5117 | Alexander Graf | |
78 | 29e4bcb2 | Andreas Färber | cpu = S390_CPU(object_new(TYPE_S390_CPU)); |
79 | 29e4bcb2 | Andreas Färber | env = &cpu->env; |
80 | 10ec5117 | Alexander Graf | env->cpu_model_str = cpu_model; |
81 | 1f136632 | Andreas Färber | |
82 | 1f136632 | Andreas Färber | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); |
83 | 1f136632 | Andreas Färber | |
84 | 564b863d | Andreas Färber | return cpu;
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85 | 10ec5117 | Alexander Graf | } |
86 | 10ec5117 | Alexander Graf | |
87 | d5a43964 | Alexander Graf | #if defined(CONFIG_USER_ONLY)
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88 | d5a43964 | Alexander Graf | |
89 | 97a8ea5a | Andreas Färber | void s390_cpu_do_interrupt(CPUState *cs)
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90 | d5a43964 | Alexander Graf | { |
91 | 97a8ea5a | Andreas Färber | S390CPU *cpu = S390_CPU(cs); |
92 | 97a8ea5a | Andreas Färber | CPUS390XState *env = &cpu->env; |
93 | 97a8ea5a | Andreas Färber | |
94 | d5a43964 | Alexander Graf | env->exception_index = -1;
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95 | d5a43964 | Alexander Graf | } |
96 | d5a43964 | Alexander Graf | |
97 | 71e47088 | Blue Swirl | int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
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98 | 71e47088 | Blue Swirl | int rw, int mmu_idx) |
99 | d5a43964 | Alexander Graf | { |
100 | d5a103cd | Richard Henderson | env->exception_index = EXCP_PGM; |
101 | d5a103cd | Richard Henderson | env->int_pgm_code = PGM_ADDRESSING; |
102 | d5a103cd | Richard Henderson | /* On real machines this value is dropped into LowMem. Since this
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103 | d5a103cd | Richard Henderson | is userland, simply put this someplace that cpu_loop can find it. */
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104 | 71e47088 | Blue Swirl | env->__excp_addr = address; |
105 | d5a43964 | Alexander Graf | return 1; |
106 | d5a43964 | Alexander Graf | } |
107 | d5a43964 | Alexander Graf | |
108 | b7e516ce | Andreas Färber | #else /* !CONFIG_USER_ONLY */ |
109 | d5a43964 | Alexander Graf | |
110 | d5a43964 | Alexander Graf | /* Ensure to exit the TB after this call! */
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111 | 71e47088 | Blue Swirl | static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, |
112 | d5a103cd | Richard Henderson | uint32_t ilen) |
113 | d5a43964 | Alexander Graf | { |
114 | d5a43964 | Alexander Graf | env->exception_index = EXCP_PGM; |
115 | d5a43964 | Alexander Graf | env->int_pgm_code = code; |
116 | d5a103cd | Richard Henderson | env->int_pgm_ilen = ilen; |
117 | d5a43964 | Alexander Graf | } |
118 | d5a43964 | Alexander Graf | |
119 | a4e3ad19 | Andreas Färber | static int trans_bits(CPUS390XState *env, uint64_t mode) |
120 | d5a43964 | Alexander Graf | { |
121 | d5a43964 | Alexander Graf | int bits = 0; |
122 | d5a43964 | Alexander Graf | |
123 | d5a43964 | Alexander Graf | switch (mode) {
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124 | d5a43964 | Alexander Graf | case PSW_ASC_PRIMARY:
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125 | d5a43964 | Alexander Graf | bits = 1;
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126 | d5a43964 | Alexander Graf | break;
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127 | d5a43964 | Alexander Graf | case PSW_ASC_SECONDARY:
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128 | d5a43964 | Alexander Graf | bits = 2;
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129 | d5a43964 | Alexander Graf | break;
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130 | d5a43964 | Alexander Graf | case PSW_ASC_HOME:
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131 | d5a43964 | Alexander Graf | bits = 3;
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132 | d5a43964 | Alexander Graf | break;
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133 | d5a43964 | Alexander Graf | default:
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134 | d5a43964 | Alexander Graf | cpu_abort(env, "unknown asc mode\n");
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135 | d5a43964 | Alexander Graf | break;
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136 | d5a43964 | Alexander Graf | } |
137 | d5a43964 | Alexander Graf | |
138 | d5a43964 | Alexander Graf | return bits;
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139 | d5a43964 | Alexander Graf | } |
140 | d5a43964 | Alexander Graf | |
141 | 71e47088 | Blue Swirl | static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, |
142 | 71e47088 | Blue Swirl | uint64_t mode) |
143 | d5a43964 | Alexander Graf | { |
144 | d5a103cd | Richard Henderson | int ilen = ILEN_LATER_INC;
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145 | d5a43964 | Alexander Graf | int bits = trans_bits(env, mode) | 4; |
146 | d5a43964 | Alexander Graf | |
147 | 71e47088 | Blue Swirl | DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits); |
148 | d5a43964 | Alexander Graf | |
149 | d5a43964 | Alexander Graf | stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits); |
150 | d5a103cd | Richard Henderson | trigger_pgm_exception(env, PGM_PROTECTION, ilen); |
151 | d5a43964 | Alexander Graf | } |
152 | d5a43964 | Alexander Graf | |
153 | 71e47088 | Blue Swirl | static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, |
154 | 71e47088 | Blue Swirl | uint32_t type, uint64_t asc, int rw)
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155 | d5a43964 | Alexander Graf | { |
156 | d5a103cd | Richard Henderson | int ilen = ILEN_LATER;
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157 | d5a43964 | Alexander Graf | int bits = trans_bits(env, asc);
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158 | d5a43964 | Alexander Graf | |
159 | d5a103cd | Richard Henderson | /* Code accesses have an undefined ilc. */
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160 | d5a43964 | Alexander Graf | if (rw == 2) { |
161 | d5a103cd | Richard Henderson | ilen = 2;
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162 | d5a43964 | Alexander Graf | } |
163 | d5a43964 | Alexander Graf | |
164 | 71e47088 | Blue Swirl | DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits); |
165 | d5a43964 | Alexander Graf | |
166 | d5a43964 | Alexander Graf | stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits); |
167 | d5a103cd | Richard Henderson | trigger_pgm_exception(env, type, ilen); |
168 | d5a43964 | Alexander Graf | } |
169 | d5a43964 | Alexander Graf | |
170 | 71e47088 | Blue Swirl | static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, |
171 | 71e47088 | Blue Swirl | uint64_t asc, uint64_t asce, int level,
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172 | 71e47088 | Blue Swirl | target_ulong *raddr, int *flags, int rw) |
173 | c92114b1 | Alexander Graf | { |
174 | d5a43964 | Alexander Graf | uint64_t offs = 0;
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175 | d5a43964 | Alexander Graf | uint64_t origin; |
176 | d5a43964 | Alexander Graf | uint64_t new_asce; |
177 | d5a43964 | Alexander Graf | |
178 | 71e47088 | Blue Swirl | PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce); |
179 | d5a43964 | Alexander Graf | |
180 | d5a43964 | Alexander Graf | if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
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181 | d5a43964 | Alexander Graf | ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) { |
182 | d5a43964 | Alexander Graf | /* XXX different regions have different faults */
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183 | 71e47088 | Blue Swirl | DPRINTF("%s: invalid region\n", __func__);
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184 | d5a43964 | Alexander Graf | trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw); |
185 | d5a43964 | Alexander Graf | return -1; |
186 | d5a43964 | Alexander Graf | } |
187 | d5a43964 | Alexander Graf | |
188 | d5a43964 | Alexander Graf | if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
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189 | d5a43964 | Alexander Graf | trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw); |
190 | d5a43964 | Alexander Graf | return -1; |
191 | d5a43964 | Alexander Graf | } |
192 | d5a43964 | Alexander Graf | |
193 | d5a43964 | Alexander Graf | if (asce & _ASCE_REAL_SPACE) {
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194 | d5a43964 | Alexander Graf | /* direct mapping */
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195 | d5a43964 | Alexander Graf | |
196 | d5a43964 | Alexander Graf | *raddr = vaddr; |
197 | d5a43964 | Alexander Graf | return 0; |
198 | d5a43964 | Alexander Graf | } |
199 | d5a43964 | Alexander Graf | |
200 | d5a43964 | Alexander Graf | origin = asce & _ASCE_ORIGIN; |
201 | d5a43964 | Alexander Graf | |
202 | d5a43964 | Alexander Graf | switch (level) {
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203 | d5a43964 | Alexander Graf | case _ASCE_TYPE_REGION1 + 4: |
204 | d5a43964 | Alexander Graf | offs = (vaddr >> 50) & 0x3ff8; |
205 | d5a43964 | Alexander Graf | break;
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206 | d5a43964 | Alexander Graf | case _ASCE_TYPE_REGION1:
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207 | d5a43964 | Alexander Graf | offs = (vaddr >> 39) & 0x3ff8; |
208 | d5a43964 | Alexander Graf | break;
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209 | d5a43964 | Alexander Graf | case _ASCE_TYPE_REGION2:
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210 | d5a43964 | Alexander Graf | offs = (vaddr >> 28) & 0x3ff8; |
211 | d5a43964 | Alexander Graf | break;
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212 | d5a43964 | Alexander Graf | case _ASCE_TYPE_REGION3:
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213 | d5a43964 | Alexander Graf | offs = (vaddr >> 17) & 0x3ff8; |
214 | d5a43964 | Alexander Graf | break;
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215 | d5a43964 | Alexander Graf | case _ASCE_TYPE_SEGMENT:
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216 | d5a43964 | Alexander Graf | offs = (vaddr >> 9) & 0x07f8; |
217 | d5a43964 | Alexander Graf | origin = asce & _SEGMENT_ENTRY_ORIGIN; |
218 | d5a43964 | Alexander Graf | break;
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219 | d5a43964 | Alexander Graf | } |
220 | d5a43964 | Alexander Graf | |
221 | d5a43964 | Alexander Graf | /* XXX region protection flags */
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222 | d5a43964 | Alexander Graf | /* *flags &= ~PAGE_WRITE */
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223 | d5a43964 | Alexander Graf | |
224 | d5a43964 | Alexander Graf | new_asce = ldq_phys(origin + offs); |
225 | d5a43964 | Alexander Graf | PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n", |
226 | 71e47088 | Blue Swirl | __func__, origin, offs, new_asce); |
227 | d5a43964 | Alexander Graf | |
228 | d5a43964 | Alexander Graf | if (level != _ASCE_TYPE_SEGMENT) {
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229 | d5a43964 | Alexander Graf | /* yet another region */
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230 | d5a43964 | Alexander Graf | return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr, |
231 | d5a43964 | Alexander Graf | flags, rw); |
232 | d5a43964 | Alexander Graf | } |
233 | d5a43964 | Alexander Graf | |
234 | d5a43964 | Alexander Graf | /* PTE */
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235 | d5a43964 | Alexander Graf | if (new_asce & _PAGE_INVALID) {
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236 | 71e47088 | Blue Swirl | DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce); |
237 | d5a43964 | Alexander Graf | trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw); |
238 | d5a43964 | Alexander Graf | return -1; |
239 | d5a43964 | Alexander Graf | } |
240 | d5a43964 | Alexander Graf | |
241 | d5a43964 | Alexander Graf | if (new_asce & _PAGE_RO) {
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242 | d5a43964 | Alexander Graf | *flags &= ~PAGE_WRITE; |
243 | d5a43964 | Alexander Graf | } |
244 | d5a43964 | Alexander Graf | |
245 | d5a43964 | Alexander Graf | *raddr = new_asce & _ASCE_ORIGIN; |
246 | d5a43964 | Alexander Graf | |
247 | 71e47088 | Blue Swirl | PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce); |
248 | d5a43964 | Alexander Graf | |
249 | c92114b1 | Alexander Graf | return 0; |
250 | c92114b1 | Alexander Graf | } |
251 | c92114b1 | Alexander Graf | |
252 | 71e47088 | Blue Swirl | static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, |
253 | 71e47088 | Blue Swirl | uint64_t asc, target_ulong *raddr, int *flags,
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254 | 71e47088 | Blue Swirl | int rw)
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255 | d5a43964 | Alexander Graf | { |
256 | d5a43964 | Alexander Graf | uint64_t asce = 0;
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257 | d5a43964 | Alexander Graf | int level, new_level;
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258 | d5a43964 | Alexander Graf | int r;
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259 | 10c339a0 | Alexander Graf | |
260 | d5a43964 | Alexander Graf | switch (asc) {
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261 | d5a43964 | Alexander Graf | case PSW_ASC_PRIMARY:
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262 | 71e47088 | Blue Swirl | PTE_DPRINTF("%s: asc=primary\n", __func__);
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263 | d5a43964 | Alexander Graf | asce = env->cregs[1];
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264 | d5a43964 | Alexander Graf | break;
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265 | d5a43964 | Alexander Graf | case PSW_ASC_SECONDARY:
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266 | 71e47088 | Blue Swirl | PTE_DPRINTF("%s: asc=secondary\n", __func__);
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267 | d5a43964 | Alexander Graf | asce = env->cregs[7];
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268 | d5a43964 | Alexander Graf | break;
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269 | d5a43964 | Alexander Graf | case PSW_ASC_HOME:
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270 | 71e47088 | Blue Swirl | PTE_DPRINTF("%s: asc=home\n", __func__);
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271 | d5a43964 | Alexander Graf | asce = env->cregs[13];
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272 | d5a43964 | Alexander Graf | break;
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273 | d5a43964 | Alexander Graf | } |
274 | d5a43964 | Alexander Graf | |
275 | d5a43964 | Alexander Graf | switch (asce & _ASCE_TYPE_MASK) {
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276 | d5a43964 | Alexander Graf | case _ASCE_TYPE_REGION1:
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277 | d5a43964 | Alexander Graf | break;
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278 | d5a43964 | Alexander Graf | case _ASCE_TYPE_REGION2:
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279 | d5a43964 | Alexander Graf | if (vaddr & 0xffe0000000000000ULL) { |
280 | d5a43964 | Alexander Graf | DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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281 | 71e47088 | Blue Swirl | " 0xffe0000000000000ULL\n", __func__, vaddr);
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282 | d5a43964 | Alexander Graf | trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw); |
283 | d5a43964 | Alexander Graf | return -1; |
284 | d5a43964 | Alexander Graf | } |
285 | d5a43964 | Alexander Graf | break;
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286 | d5a43964 | Alexander Graf | case _ASCE_TYPE_REGION3:
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287 | d5a43964 | Alexander Graf | if (vaddr & 0xfffffc0000000000ULL) { |
288 | d5a43964 | Alexander Graf | DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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289 | 71e47088 | Blue Swirl | " 0xfffffc0000000000ULL\n", __func__, vaddr);
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290 | d5a43964 | Alexander Graf | trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw); |
291 | d5a43964 | Alexander Graf | return -1; |
292 | d5a43964 | Alexander Graf | } |
293 | d5a43964 | Alexander Graf | break;
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294 | d5a43964 | Alexander Graf | case _ASCE_TYPE_SEGMENT:
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295 | d5a43964 | Alexander Graf | if (vaddr & 0xffffffff80000000ULL) { |
296 | d5a43964 | Alexander Graf | DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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297 | 71e47088 | Blue Swirl | " 0xffffffff80000000ULL\n", __func__, vaddr);
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298 | d5a43964 | Alexander Graf | trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw); |
299 | d5a43964 | Alexander Graf | return -1; |
300 | d5a43964 | Alexander Graf | } |
301 | d5a43964 | Alexander Graf | break;
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302 | d5a43964 | Alexander Graf | } |
303 | d5a43964 | Alexander Graf | |
304 | d5a43964 | Alexander Graf | /* fake level above current */
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305 | d5a43964 | Alexander Graf | level = asce & _ASCE_TYPE_MASK; |
306 | d5a43964 | Alexander Graf | new_level = level + 4;
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307 | d5a43964 | Alexander Graf | asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK); |
308 | d5a43964 | Alexander Graf | |
309 | d5a43964 | Alexander Graf | r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw); |
310 | d5a43964 | Alexander Graf | |
311 | d5a43964 | Alexander Graf | if ((rw == 1) && !(*flags & PAGE_WRITE)) { |
312 | d5a43964 | Alexander Graf | trigger_prot_fault(env, vaddr, asc); |
313 | d5a43964 | Alexander Graf | return -1; |
314 | d5a43964 | Alexander Graf | } |
315 | d5a43964 | Alexander Graf | |
316 | d5a43964 | Alexander Graf | return r;
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317 | d5a43964 | Alexander Graf | } |
318 | d5a43964 | Alexander Graf | |
319 | a4e3ad19 | Andreas Färber | int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, |
320 | d5a43964 | Alexander Graf | target_ulong *raddr, int *flags)
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321 | d5a43964 | Alexander Graf | { |
322 | d5a43964 | Alexander Graf | int r = -1; |
323 | b9959138 | Alexander Graf | uint8_t *sk; |
324 | d5a43964 | Alexander Graf | |
325 | d5a43964 | Alexander Graf | *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
326 | d5a43964 | Alexander Graf | vaddr &= TARGET_PAGE_MASK; |
327 | d5a43964 | Alexander Graf | |
328 | d5a43964 | Alexander Graf | if (!(env->psw.mask & PSW_MASK_DAT)) {
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329 | d5a43964 | Alexander Graf | *raddr = vaddr; |
330 | d5a43964 | Alexander Graf | r = 0;
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331 | d5a43964 | Alexander Graf | goto out;
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332 | d5a43964 | Alexander Graf | } |
333 | d5a43964 | Alexander Graf | |
334 | d5a43964 | Alexander Graf | switch (asc) {
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335 | d5a43964 | Alexander Graf | case PSW_ASC_PRIMARY:
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336 | d5a43964 | Alexander Graf | case PSW_ASC_HOME:
|
337 | d5a43964 | Alexander Graf | r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw); |
338 | d5a43964 | Alexander Graf | break;
|
339 | d5a43964 | Alexander Graf | case PSW_ASC_SECONDARY:
|
340 | d5a43964 | Alexander Graf | /*
|
341 | d5a43964 | Alexander Graf | * Instruction: Primary
|
342 | d5a43964 | Alexander Graf | * Data: Secondary
|
343 | d5a43964 | Alexander Graf | */
|
344 | d5a43964 | Alexander Graf | if (rw == 2) { |
345 | d5a43964 | Alexander Graf | r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags, |
346 | d5a43964 | Alexander Graf | rw); |
347 | d5a43964 | Alexander Graf | *flags &= ~(PAGE_READ | PAGE_WRITE); |
348 | d5a43964 | Alexander Graf | } else {
|
349 | d5a43964 | Alexander Graf | r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags, |
350 | d5a43964 | Alexander Graf | rw); |
351 | d5a43964 | Alexander Graf | *flags &= ~(PAGE_EXEC); |
352 | d5a43964 | Alexander Graf | } |
353 | d5a43964 | Alexander Graf | break;
|
354 | d5a43964 | Alexander Graf | case PSW_ASC_ACCREG:
|
355 | d5a43964 | Alexander Graf | default:
|
356 | d5a43964 | Alexander Graf | hw_error("guest switched to unknown asc mode\n");
|
357 | d5a43964 | Alexander Graf | break;
|
358 | d5a43964 | Alexander Graf | } |
359 | d5a43964 | Alexander Graf | |
360 | 71e47088 | Blue Swirl | out:
|
361 | d5a43964 | Alexander Graf | /* Convert real address -> absolute address */
|
362 | d5a43964 | Alexander Graf | if (*raddr < 0x2000) { |
363 | d5a43964 | Alexander Graf | *raddr = *raddr + env->psa; |
364 | d5a43964 | Alexander Graf | } |
365 | d5a43964 | Alexander Graf | |
366 | b9959138 | Alexander Graf | if (*raddr <= ram_size) {
|
367 | b9959138 | Alexander Graf | sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE]; |
368 | b9959138 | Alexander Graf | if (*flags & PAGE_READ) {
|
369 | b9959138 | Alexander Graf | *sk |= SK_R; |
370 | b9959138 | Alexander Graf | } |
371 | b9959138 | Alexander Graf | |
372 | b9959138 | Alexander Graf | if (*flags & PAGE_WRITE) {
|
373 | b9959138 | Alexander Graf | *sk |= SK_C; |
374 | b9959138 | Alexander Graf | } |
375 | b9959138 | Alexander Graf | } |
376 | b9959138 | Alexander Graf | |
377 | d5a43964 | Alexander Graf | return r;
|
378 | d5a43964 | Alexander Graf | } |
379 | d5a43964 | Alexander Graf | |
380 | 71e47088 | Blue Swirl | int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
|
381 | 71e47088 | Blue Swirl | int rw, int mmu_idx) |
382 | 10c339a0 | Alexander Graf | { |
383 | d5a43964 | Alexander Graf | uint64_t asc = env->psw.mask & PSW_MASK_ASC; |
384 | d5a43964 | Alexander Graf | target_ulong vaddr, raddr; |
385 | 10c339a0 | Alexander Graf | int prot;
|
386 | 10c339a0 | Alexander Graf | |
387 | 97b348e7 | Blue Swirl | DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n", |
388 | 07cc7d12 | Andreas Färber | __func__, orig_vaddr, rw, mmu_idx); |
389 | d5a43964 | Alexander Graf | |
390 | 71e47088 | Blue Swirl | orig_vaddr &= TARGET_PAGE_MASK; |
391 | 71e47088 | Blue Swirl | vaddr = orig_vaddr; |
392 | d5a43964 | Alexander Graf | |
393 | d5a43964 | Alexander Graf | /* 31-Bit mode */
|
394 | d5a43964 | Alexander Graf | if (!(env->psw.mask & PSW_MASK_64)) {
|
395 | d5a43964 | Alexander Graf | vaddr &= 0x7fffffff;
|
396 | d5a43964 | Alexander Graf | } |
397 | d5a43964 | Alexander Graf | |
398 | d5a43964 | Alexander Graf | if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
|
399 | d5a43964 | Alexander Graf | /* Translation ended in exception */
|
400 | d5a43964 | Alexander Graf | return 1; |
401 | d5a43964 | Alexander Graf | } |
402 | 10c339a0 | Alexander Graf | |
403 | d5a43964 | Alexander Graf | /* check out of RAM access */
|
404 | d5a43964 | Alexander Graf | if (raddr > (ram_size + virtio_size)) {
|
405 | a6f921b0 | Andreas Färber | DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__, |
406 | a6f921b0 | Andreas Färber | (uint64_t)raddr, (uint64_t)ram_size); |
407 | d5a103cd | Richard Henderson | trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_LATER); |
408 | d5a43964 | Alexander Graf | return 1; |
409 | d5a43964 | Alexander Graf | } |
410 | 10c339a0 | Alexander Graf | |
411 | 71e47088 | Blue Swirl | DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__, |
412 | d5a43964 | Alexander Graf | (uint64_t)vaddr, (uint64_t)raddr, prot); |
413 | d5a43964 | Alexander Graf | |
414 | 71e47088 | Blue Swirl | tlb_set_page(env, orig_vaddr, raddr, prot, |
415 | d4c430a8 | Paul Brook | mmu_idx, TARGET_PAGE_SIZE); |
416 | d5a43964 | Alexander Graf | |
417 | d4c430a8 | Paul Brook | return 0; |
418 | 10c339a0 | Alexander Graf | } |
419 | d5a43964 | Alexander Graf | |
420 | a8170e5e | Avi Kivity | hwaddr cpu_get_phys_page_debug(CPUS390XState *env, |
421 | 71e47088 | Blue Swirl | target_ulong vaddr) |
422 | d5a43964 | Alexander Graf | { |
423 | d5a43964 | Alexander Graf | target_ulong raddr; |
424 | d5a43964 | Alexander Graf | int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
425 | d5a43964 | Alexander Graf | int old_exc = env->exception_index;
|
426 | d5a43964 | Alexander Graf | uint64_t asc = env->psw.mask & PSW_MASK_ASC; |
427 | d5a43964 | Alexander Graf | |
428 | d5a43964 | Alexander Graf | /* 31-Bit mode */
|
429 | d5a43964 | Alexander Graf | if (!(env->psw.mask & PSW_MASK_64)) {
|
430 | d5a43964 | Alexander Graf | vaddr &= 0x7fffffff;
|
431 | d5a43964 | Alexander Graf | } |
432 | d5a43964 | Alexander Graf | |
433 | d5a43964 | Alexander Graf | mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
|
434 | d5a43964 | Alexander Graf | env->exception_index = old_exc; |
435 | d5a43964 | Alexander Graf | |
436 | d5a43964 | Alexander Graf | return raddr;
|
437 | d5a43964 | Alexander Graf | } |
438 | d5a43964 | Alexander Graf | |
439 | a4e3ad19 | Andreas Färber | void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
|
440 | d5a43964 | Alexander Graf | { |
441 | d5a43964 | Alexander Graf | if (mask & PSW_MASK_WAIT) {
|
442 | 49e15878 | Andreas Färber | S390CPU *cpu = s390_env_get_cpu(env); |
443 | 259186a7 | Andreas Färber | CPUState *cs = CPU(cpu); |
444 | d5a43964 | Alexander Graf | if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
|
445 | 49e15878 | Andreas Färber | if (s390_del_running_cpu(cpu) == 0) { |
446 | ef81522b | Alexander Graf | #ifndef CONFIG_USER_ONLY
|
447 | ef81522b | Alexander Graf | qemu_system_shutdown_request(); |
448 | ef81522b | Alexander Graf | #endif
|
449 | ef81522b | Alexander Graf | } |
450 | d5a43964 | Alexander Graf | } |
451 | 259186a7 | Andreas Färber | cs->halted = 1;
|
452 | ef81522b | Alexander Graf | env->exception_index = EXCP_HLT; |
453 | d5a43964 | Alexander Graf | } |
454 | d5a43964 | Alexander Graf | |
455 | d5a43964 | Alexander Graf | env->psw.addr = addr; |
456 | d5a43964 | Alexander Graf | env->psw.mask = mask; |
457 | 51855ecf | Richard Henderson | env->cc_op = (mask >> 44) & 3; |
458 | d5a43964 | Alexander Graf | } |
459 | d5a43964 | Alexander Graf | |
460 | a4e3ad19 | Andreas Färber | static uint64_t get_psw_mask(CPUS390XState *env)
|
461 | d5a43964 | Alexander Graf | { |
462 | 51855ecf | Richard Henderson | uint64_t r; |
463 | d5a43964 | Alexander Graf | |
464 | d5a43964 | Alexander Graf | env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr); |
465 | d5a43964 | Alexander Graf | |
466 | 51855ecf | Richard Henderson | r = env->psw.mask; |
467 | 51855ecf | Richard Henderson | r &= ~PSW_MASK_CC; |
468 | d5a43964 | Alexander Graf | assert(!(env->cc_op & ~3));
|
469 | 51855ecf | Richard Henderson | r |= (uint64_t)env->cc_op << 44;
|
470 | d5a43964 | Alexander Graf | |
471 | d5a43964 | Alexander Graf | return r;
|
472 | d5a43964 | Alexander Graf | } |
473 | d5a43964 | Alexander Graf | |
474 | 4782a23b | Cornelia Huck | static LowCore *cpu_map_lowcore(CPUS390XState *env)
|
475 | 4782a23b | Cornelia Huck | { |
476 | 4782a23b | Cornelia Huck | LowCore *lowcore; |
477 | 4782a23b | Cornelia Huck | hwaddr len = sizeof(LowCore);
|
478 | 4782a23b | Cornelia Huck | |
479 | 4782a23b | Cornelia Huck | lowcore = cpu_physical_memory_map(env->psa, &len, 1);
|
480 | 4782a23b | Cornelia Huck | |
481 | 4782a23b | Cornelia Huck | if (len < sizeof(LowCore)) { |
482 | 4782a23b | Cornelia Huck | cpu_abort(env, "Could not map lowcore\n");
|
483 | 4782a23b | Cornelia Huck | } |
484 | 4782a23b | Cornelia Huck | |
485 | 4782a23b | Cornelia Huck | return lowcore;
|
486 | 4782a23b | Cornelia Huck | } |
487 | 4782a23b | Cornelia Huck | |
488 | 4782a23b | Cornelia Huck | static void cpu_unmap_lowcore(LowCore *lowcore) |
489 | 4782a23b | Cornelia Huck | { |
490 | 4782a23b | Cornelia Huck | cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore)); |
491 | 4782a23b | Cornelia Huck | } |
492 | 4782a23b | Cornelia Huck | |
493 | 38322ed6 | Cornelia Huck | void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
|
494 | 38322ed6 | Cornelia Huck | int is_write)
|
495 | 38322ed6 | Cornelia Huck | { |
496 | 38322ed6 | Cornelia Huck | hwaddr start = addr; |
497 | 38322ed6 | Cornelia Huck | |
498 | 38322ed6 | Cornelia Huck | /* Mind the prefix area. */
|
499 | 38322ed6 | Cornelia Huck | if (addr < 8192) { |
500 | 38322ed6 | Cornelia Huck | /* Map the lowcore. */
|
501 | 38322ed6 | Cornelia Huck | start += env->psa; |
502 | 38322ed6 | Cornelia Huck | *len = MIN(*len, 8192 - addr);
|
503 | 38322ed6 | Cornelia Huck | } else if ((addr >= env->psa) && (addr < env->psa + 8192)) { |
504 | 38322ed6 | Cornelia Huck | /* Map the 0 page. */
|
505 | 38322ed6 | Cornelia Huck | start -= env->psa; |
506 | 38322ed6 | Cornelia Huck | *len = MIN(*len, 8192 - start);
|
507 | 38322ed6 | Cornelia Huck | } |
508 | 38322ed6 | Cornelia Huck | |
509 | 38322ed6 | Cornelia Huck | return cpu_physical_memory_map(start, len, is_write);
|
510 | 38322ed6 | Cornelia Huck | } |
511 | 38322ed6 | Cornelia Huck | |
512 | 38322ed6 | Cornelia Huck | void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len, |
513 | 38322ed6 | Cornelia Huck | int is_write)
|
514 | 38322ed6 | Cornelia Huck | { |
515 | 38322ed6 | Cornelia Huck | cpu_physical_memory_unmap(addr, len, is_write, len); |
516 | 38322ed6 | Cornelia Huck | } |
517 | 38322ed6 | Cornelia Huck | |
518 | a4e3ad19 | Andreas Färber | static void do_svc_interrupt(CPUS390XState *env) |
519 | d5a43964 | Alexander Graf | { |
520 | d5a43964 | Alexander Graf | uint64_t mask, addr; |
521 | d5a43964 | Alexander Graf | LowCore *lowcore; |
522 | d5a43964 | Alexander Graf | |
523 | 4782a23b | Cornelia Huck | lowcore = cpu_map_lowcore(env); |
524 | d5a43964 | Alexander Graf | |
525 | d5a43964 | Alexander Graf | lowcore->svc_code = cpu_to_be16(env->int_svc_code); |
526 | d5a103cd | Richard Henderson | lowcore->svc_ilen = cpu_to_be16(env->int_svc_ilen); |
527 | d5a43964 | Alexander Graf | lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env)); |
528 | d5a103cd | Richard Henderson | lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + env->int_svc_ilen); |
529 | d5a43964 | Alexander Graf | mask = be64_to_cpu(lowcore->svc_new_psw.mask); |
530 | d5a43964 | Alexander Graf | addr = be64_to_cpu(lowcore->svc_new_psw.addr); |
531 | d5a43964 | Alexander Graf | |
532 | 4782a23b | Cornelia Huck | cpu_unmap_lowcore(lowcore); |
533 | d5a43964 | Alexander Graf | |
534 | d5a43964 | Alexander Graf | load_psw(env, mask, addr); |
535 | d5a43964 | Alexander Graf | } |
536 | d5a43964 | Alexander Graf | |
537 | a4e3ad19 | Andreas Färber | static void do_program_interrupt(CPUS390XState *env) |
538 | d5a43964 | Alexander Graf | { |
539 | d5a43964 | Alexander Graf | uint64_t mask, addr; |
540 | d5a43964 | Alexander Graf | LowCore *lowcore; |
541 | d5a103cd | Richard Henderson | int ilen = env->int_pgm_ilen;
|
542 | d5a43964 | Alexander Graf | |
543 | d5a103cd | Richard Henderson | switch (ilen) {
|
544 | d5a103cd | Richard Henderson | case ILEN_LATER:
|
545 | d5a103cd | Richard Henderson | ilen = get_ilen(cpu_ldub_code(env, env->psw.addr)); |
546 | d5a43964 | Alexander Graf | break;
|
547 | d5a103cd | Richard Henderson | case ILEN_LATER_INC:
|
548 | d5a103cd | Richard Henderson | ilen = get_ilen(cpu_ldub_code(env, env->psw.addr)); |
549 | d5a103cd | Richard Henderson | env->psw.addr += ilen; |
550 | d5a43964 | Alexander Graf | break;
|
551 | d5a103cd | Richard Henderson | default:
|
552 | d5a103cd | Richard Henderson | assert(ilen == 2 || ilen == 4 || ilen == 6); |
553 | d5a43964 | Alexander Graf | } |
554 | d5a43964 | Alexander Graf | |
555 | d5a103cd | Richard Henderson | qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilen=%d\n",
|
556 | d5a103cd | Richard Henderson | __func__, env->int_pgm_code, ilen); |
557 | d5a43964 | Alexander Graf | |
558 | 4782a23b | Cornelia Huck | lowcore = cpu_map_lowcore(env); |
559 | d5a43964 | Alexander Graf | |
560 | d5a103cd | Richard Henderson | lowcore->pgm_ilen = cpu_to_be16(ilen); |
561 | d5a43964 | Alexander Graf | lowcore->pgm_code = cpu_to_be16(env->int_pgm_code); |
562 | d5a43964 | Alexander Graf | lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env)); |
563 | d5a43964 | Alexander Graf | lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr); |
564 | d5a43964 | Alexander Graf | mask = be64_to_cpu(lowcore->program_new_psw.mask); |
565 | d5a43964 | Alexander Graf | addr = be64_to_cpu(lowcore->program_new_psw.addr); |
566 | d5a43964 | Alexander Graf | |
567 | 4782a23b | Cornelia Huck | cpu_unmap_lowcore(lowcore); |
568 | d5a43964 | Alexander Graf | |
569 | 71e47088 | Blue Swirl | DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__, |
570 | d5a103cd | Richard Henderson | env->int_pgm_code, ilen, env->psw.mask, |
571 | d5a43964 | Alexander Graf | env->psw.addr); |
572 | d5a43964 | Alexander Graf | |
573 | d5a43964 | Alexander Graf | load_psw(env, mask, addr); |
574 | d5a43964 | Alexander Graf | } |
575 | d5a43964 | Alexander Graf | |
576 | d5a43964 | Alexander Graf | #define VIRTIO_SUBCODE_64 0x0D00 |
577 | d5a43964 | Alexander Graf | |
578 | a4e3ad19 | Andreas Färber | static void do_ext_interrupt(CPUS390XState *env) |
579 | d5a43964 | Alexander Graf | { |
580 | d5a43964 | Alexander Graf | uint64_t mask, addr; |
581 | d5a43964 | Alexander Graf | LowCore *lowcore; |
582 | d5a43964 | Alexander Graf | ExtQueue *q; |
583 | d5a43964 | Alexander Graf | |
584 | d5a43964 | Alexander Graf | if (!(env->psw.mask & PSW_MASK_EXT)) {
|
585 | d5a43964 | Alexander Graf | cpu_abort(env, "Ext int w/o ext mask\n");
|
586 | d5a43964 | Alexander Graf | } |
587 | d5a43964 | Alexander Graf | |
588 | d5a43964 | Alexander Graf | if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) { |
589 | d5a43964 | Alexander Graf | cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
|
590 | d5a43964 | Alexander Graf | } |
591 | d5a43964 | Alexander Graf | |
592 | d5a43964 | Alexander Graf | q = &env->ext_queue[env->ext_index]; |
593 | 4782a23b | Cornelia Huck | lowcore = cpu_map_lowcore(env); |
594 | d5a43964 | Alexander Graf | |
595 | d5a43964 | Alexander Graf | lowcore->ext_int_code = cpu_to_be16(q->code); |
596 | d5a43964 | Alexander Graf | lowcore->ext_params = cpu_to_be32(q->param); |
597 | d5a43964 | Alexander Graf | lowcore->ext_params2 = cpu_to_be64(q->param64); |
598 | d5a43964 | Alexander Graf | lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env)); |
599 | d5a43964 | Alexander Graf | lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr); |
600 | d5a43964 | Alexander Graf | lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64); |
601 | d5a43964 | Alexander Graf | mask = be64_to_cpu(lowcore->external_new_psw.mask); |
602 | d5a43964 | Alexander Graf | addr = be64_to_cpu(lowcore->external_new_psw.addr); |
603 | d5a43964 | Alexander Graf | |
604 | 4782a23b | Cornelia Huck | cpu_unmap_lowcore(lowcore); |
605 | d5a43964 | Alexander Graf | |
606 | d5a43964 | Alexander Graf | env->ext_index--; |
607 | d5a43964 | Alexander Graf | if (env->ext_index == -1) { |
608 | d5a43964 | Alexander Graf | env->pending_int &= ~INTERRUPT_EXT; |
609 | d5a43964 | Alexander Graf | } |
610 | d5a43964 | Alexander Graf | |
611 | 71e47088 | Blue Swirl | DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__, |
612 | d5a43964 | Alexander Graf | env->psw.mask, env->psw.addr); |
613 | d5a43964 | Alexander Graf | |
614 | d5a43964 | Alexander Graf | load_psw(env, mask, addr); |
615 | d5a43964 | Alexander Graf | } |
616 | 3110e292 | Alexander Graf | |
617 | 5d69c547 | Cornelia Huck | static void do_io_interrupt(CPUS390XState *env) |
618 | 5d69c547 | Cornelia Huck | { |
619 | 5d69c547 | Cornelia Huck | LowCore *lowcore; |
620 | 5d69c547 | Cornelia Huck | IOIntQueue *q; |
621 | 5d69c547 | Cornelia Huck | uint8_t isc; |
622 | 5d69c547 | Cornelia Huck | int disable = 1; |
623 | 5d69c547 | Cornelia Huck | int found = 0; |
624 | 5d69c547 | Cornelia Huck | |
625 | 5d69c547 | Cornelia Huck | if (!(env->psw.mask & PSW_MASK_IO)) {
|
626 | 5d69c547 | Cornelia Huck | cpu_abort(env, "I/O int w/o I/O mask\n");
|
627 | 5d69c547 | Cornelia Huck | } |
628 | 5d69c547 | Cornelia Huck | |
629 | 5d69c547 | Cornelia Huck | for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) { |
630 | 91b0a8f3 | Cornelia Huck | uint64_t isc_bits; |
631 | 91b0a8f3 | Cornelia Huck | |
632 | 5d69c547 | Cornelia Huck | if (env->io_index[isc] < 0) { |
633 | 5d69c547 | Cornelia Huck | continue;
|
634 | 5d69c547 | Cornelia Huck | } |
635 | 5d69c547 | Cornelia Huck | if (env->io_index[isc] > MAX_IO_QUEUE) {
|
636 | 5d69c547 | Cornelia Huck | cpu_abort(env, "I/O queue overrun for isc %d: %d\n",
|
637 | 5d69c547 | Cornelia Huck | isc, env->io_index[isc]); |
638 | 5d69c547 | Cornelia Huck | } |
639 | 5d69c547 | Cornelia Huck | |
640 | 5d69c547 | Cornelia Huck | q = &env->io_queue[env->io_index[isc]][isc]; |
641 | 91b0a8f3 | Cornelia Huck | isc_bits = ISC_TO_ISC_BITS(IO_INT_WORD_ISC(q->word)); |
642 | 91b0a8f3 | Cornelia Huck | if (!(env->cregs[6] & isc_bits)) { |
643 | 5d69c547 | Cornelia Huck | disable = 0;
|
644 | 5d69c547 | Cornelia Huck | continue;
|
645 | 5d69c547 | Cornelia Huck | } |
646 | bd9a8d85 | Cornelia Huck | if (!found) {
|
647 | bd9a8d85 | Cornelia Huck | uint64_t mask, addr; |
648 | 5d69c547 | Cornelia Huck | |
649 | bd9a8d85 | Cornelia Huck | found = 1;
|
650 | bd9a8d85 | Cornelia Huck | lowcore = cpu_map_lowcore(env); |
651 | 5d69c547 | Cornelia Huck | |
652 | bd9a8d85 | Cornelia Huck | lowcore->subchannel_id = cpu_to_be16(q->id); |
653 | bd9a8d85 | Cornelia Huck | lowcore->subchannel_nr = cpu_to_be16(q->nr); |
654 | bd9a8d85 | Cornelia Huck | lowcore->io_int_parm = cpu_to_be32(q->parm); |
655 | bd9a8d85 | Cornelia Huck | lowcore->io_int_word = cpu_to_be32(q->word); |
656 | bd9a8d85 | Cornelia Huck | lowcore->io_old_psw.mask = cpu_to_be64(get_psw_mask(env)); |
657 | bd9a8d85 | Cornelia Huck | lowcore->io_old_psw.addr = cpu_to_be64(env->psw.addr); |
658 | bd9a8d85 | Cornelia Huck | mask = be64_to_cpu(lowcore->io_new_psw.mask); |
659 | bd9a8d85 | Cornelia Huck | addr = be64_to_cpu(lowcore->io_new_psw.addr); |
660 | 5d69c547 | Cornelia Huck | |
661 | bd9a8d85 | Cornelia Huck | cpu_unmap_lowcore(lowcore); |
662 | bd9a8d85 | Cornelia Huck | |
663 | bd9a8d85 | Cornelia Huck | env->io_index[isc]--; |
664 | bd9a8d85 | Cornelia Huck | |
665 | bd9a8d85 | Cornelia Huck | DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__, |
666 | bd9a8d85 | Cornelia Huck | env->psw.mask, env->psw.addr); |
667 | bd9a8d85 | Cornelia Huck | load_psw(env, mask, addr); |
668 | bd9a8d85 | Cornelia Huck | } |
669 | b22dd124 | Stefan Weil | if (env->io_index[isc] >= 0) { |
670 | 5d69c547 | Cornelia Huck | disable = 0;
|
671 | 5d69c547 | Cornelia Huck | } |
672 | bd9a8d85 | Cornelia Huck | continue;
|
673 | 5d69c547 | Cornelia Huck | } |
674 | 5d69c547 | Cornelia Huck | |
675 | 5d69c547 | Cornelia Huck | if (disable) {
|
676 | 5d69c547 | Cornelia Huck | env->pending_int &= ~INTERRUPT_IO; |
677 | 5d69c547 | Cornelia Huck | } |
678 | 5d69c547 | Cornelia Huck | |
679 | 5d69c547 | Cornelia Huck | } |
680 | 5d69c547 | Cornelia Huck | |
681 | 5d69c547 | Cornelia Huck | static void do_mchk_interrupt(CPUS390XState *env) |
682 | 5d69c547 | Cornelia Huck | { |
683 | 5d69c547 | Cornelia Huck | uint64_t mask, addr; |
684 | 5d69c547 | Cornelia Huck | LowCore *lowcore; |
685 | 5d69c547 | Cornelia Huck | MchkQueue *q; |
686 | 5d69c547 | Cornelia Huck | int i;
|
687 | 5d69c547 | Cornelia Huck | |
688 | 5d69c547 | Cornelia Huck | if (!(env->psw.mask & PSW_MASK_MCHECK)) {
|
689 | 5d69c547 | Cornelia Huck | cpu_abort(env, "Machine check w/o mchk mask\n");
|
690 | 5d69c547 | Cornelia Huck | } |
691 | 5d69c547 | Cornelia Huck | |
692 | 5d69c547 | Cornelia Huck | if (env->mchk_index < 0 || env->mchk_index > MAX_MCHK_QUEUE) { |
693 | 5d69c547 | Cornelia Huck | cpu_abort(env, "Mchk queue overrun: %d\n", env->mchk_index);
|
694 | 5d69c547 | Cornelia Huck | } |
695 | 5d69c547 | Cornelia Huck | |
696 | 5d69c547 | Cornelia Huck | q = &env->mchk_queue[env->mchk_index]; |
697 | 5d69c547 | Cornelia Huck | |
698 | 5d69c547 | Cornelia Huck | if (q->type != 1) { |
699 | 5d69c547 | Cornelia Huck | /* Don't know how to handle this... */
|
700 | 5d69c547 | Cornelia Huck | cpu_abort(env, "Unknown machine check type %d\n", q->type);
|
701 | 5d69c547 | Cornelia Huck | } |
702 | 5d69c547 | Cornelia Huck | if (!(env->cregs[14] & (1 << 28))) { |
703 | 5d69c547 | Cornelia Huck | /* CRW machine checks disabled */
|
704 | 5d69c547 | Cornelia Huck | return;
|
705 | 5d69c547 | Cornelia Huck | } |
706 | 5d69c547 | Cornelia Huck | |
707 | 5d69c547 | Cornelia Huck | lowcore = cpu_map_lowcore(env); |
708 | 5d69c547 | Cornelia Huck | |
709 | 5d69c547 | Cornelia Huck | for (i = 0; i < 16; i++) { |
710 | 5d69c547 | Cornelia Huck | lowcore->floating_pt_save_area[i] = cpu_to_be64(env->fregs[i].ll); |
711 | 5d69c547 | Cornelia Huck | lowcore->gpregs_save_area[i] = cpu_to_be64(env->regs[i]); |
712 | 5d69c547 | Cornelia Huck | lowcore->access_regs_save_area[i] = cpu_to_be32(env->aregs[i]); |
713 | 5d69c547 | Cornelia Huck | lowcore->cregs_save_area[i] = cpu_to_be64(env->cregs[i]); |
714 | 5d69c547 | Cornelia Huck | } |
715 | 5d69c547 | Cornelia Huck | lowcore->prefixreg_save_area = cpu_to_be32(env->psa); |
716 | 5d69c547 | Cornelia Huck | lowcore->fpt_creg_save_area = cpu_to_be32(env->fpc); |
717 | 5d69c547 | Cornelia Huck | lowcore->tod_progreg_save_area = cpu_to_be32(env->todpr); |
718 | 5d69c547 | Cornelia Huck | lowcore->cpu_timer_save_area[0] = cpu_to_be32(env->cputm >> 32); |
719 | 5d69c547 | Cornelia Huck | lowcore->cpu_timer_save_area[1] = cpu_to_be32((uint32_t)env->cputm);
|
720 | 5d69c547 | Cornelia Huck | lowcore->clock_comp_save_area[0] = cpu_to_be32(env->ckc >> 32); |
721 | 5d69c547 | Cornelia Huck | lowcore->clock_comp_save_area[1] = cpu_to_be32((uint32_t)env->ckc);
|
722 | 5d69c547 | Cornelia Huck | |
723 | 5d69c547 | Cornelia Huck | lowcore->mcck_interruption_code[0] = cpu_to_be32(0x00400f1d); |
724 | 5d69c547 | Cornelia Huck | lowcore->mcck_interruption_code[1] = cpu_to_be32(0x40330000); |
725 | 5d69c547 | Cornelia Huck | lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env)); |
726 | 5d69c547 | Cornelia Huck | lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr); |
727 | 5d69c547 | Cornelia Huck | mask = be64_to_cpu(lowcore->mcck_new_psw.mask); |
728 | 5d69c547 | Cornelia Huck | addr = be64_to_cpu(lowcore->mcck_new_psw.addr); |
729 | 5d69c547 | Cornelia Huck | |
730 | 5d69c547 | Cornelia Huck | cpu_unmap_lowcore(lowcore); |
731 | 5d69c547 | Cornelia Huck | |
732 | 5d69c547 | Cornelia Huck | env->mchk_index--; |
733 | 5d69c547 | Cornelia Huck | if (env->mchk_index == -1) { |
734 | 5d69c547 | Cornelia Huck | env->pending_int &= ~INTERRUPT_MCHK; |
735 | 5d69c547 | Cornelia Huck | } |
736 | 5d69c547 | Cornelia Huck | |
737 | 5d69c547 | Cornelia Huck | DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__, |
738 | 5d69c547 | Cornelia Huck | env->psw.mask, env->psw.addr); |
739 | 5d69c547 | Cornelia Huck | |
740 | 5d69c547 | Cornelia Huck | load_psw(env, mask, addr); |
741 | 5d69c547 | Cornelia Huck | } |
742 | 5d69c547 | Cornelia Huck | |
743 | 97a8ea5a | Andreas Färber | void s390_cpu_do_interrupt(CPUState *cs)
|
744 | 3110e292 | Alexander Graf | { |
745 | 97a8ea5a | Andreas Färber | S390CPU *cpu = S390_CPU(cs); |
746 | 97a8ea5a | Andreas Färber | CPUS390XState *env = &cpu->env; |
747 | f9466733 | Andreas Färber | |
748 | 0d404541 | Richard Henderson | qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n", |
749 | 0d404541 | Richard Henderson | __func__, env->exception_index, env->psw.addr); |
750 | d5a43964 | Alexander Graf | |
751 | 49e15878 | Andreas Färber | s390_add_running_cpu(cpu); |
752 | 5d69c547 | Cornelia Huck | /* handle machine checks */
|
753 | 5d69c547 | Cornelia Huck | if ((env->psw.mask & PSW_MASK_MCHECK) &&
|
754 | 5d69c547 | Cornelia Huck | (env->exception_index == -1)) {
|
755 | 5d69c547 | Cornelia Huck | if (env->pending_int & INTERRUPT_MCHK) {
|
756 | 5d69c547 | Cornelia Huck | env->exception_index = EXCP_MCHK; |
757 | 5d69c547 | Cornelia Huck | } |
758 | 5d69c547 | Cornelia Huck | } |
759 | d5a43964 | Alexander Graf | /* handle external interrupts */
|
760 | d5a43964 | Alexander Graf | if ((env->psw.mask & PSW_MASK_EXT) &&
|
761 | d5a43964 | Alexander Graf | env->exception_index == -1) {
|
762 | d5a43964 | Alexander Graf | if (env->pending_int & INTERRUPT_EXT) {
|
763 | d5a43964 | Alexander Graf | /* code is already in env */
|
764 | d5a43964 | Alexander Graf | env->exception_index = EXCP_EXT; |
765 | d5a43964 | Alexander Graf | } else if (env->pending_int & INTERRUPT_TOD) { |
766 | f9466733 | Andreas Färber | cpu_inject_ext(cpu, 0x1004, 0, 0); |
767 | d5a43964 | Alexander Graf | env->exception_index = EXCP_EXT; |
768 | d5a43964 | Alexander Graf | env->pending_int &= ~INTERRUPT_EXT; |
769 | d5a43964 | Alexander Graf | env->pending_int &= ~INTERRUPT_TOD; |
770 | d5a43964 | Alexander Graf | } else if (env->pending_int & INTERRUPT_CPUTIMER) { |
771 | f9466733 | Andreas Färber | cpu_inject_ext(cpu, 0x1005, 0, 0); |
772 | d5a43964 | Alexander Graf | env->exception_index = EXCP_EXT; |
773 | d5a43964 | Alexander Graf | env->pending_int &= ~INTERRUPT_EXT; |
774 | d5a43964 | Alexander Graf | env->pending_int &= ~INTERRUPT_TOD; |
775 | d5a43964 | Alexander Graf | } |
776 | d5a43964 | Alexander Graf | } |
777 | 5d69c547 | Cornelia Huck | /* handle I/O interrupts */
|
778 | 5d69c547 | Cornelia Huck | if ((env->psw.mask & PSW_MASK_IO) &&
|
779 | 5d69c547 | Cornelia Huck | (env->exception_index == -1)) {
|
780 | 5d69c547 | Cornelia Huck | if (env->pending_int & INTERRUPT_IO) {
|
781 | 5d69c547 | Cornelia Huck | env->exception_index = EXCP_IO; |
782 | 5d69c547 | Cornelia Huck | } |
783 | 5d69c547 | Cornelia Huck | } |
784 | d5a43964 | Alexander Graf | |
785 | d5a43964 | Alexander Graf | switch (env->exception_index) {
|
786 | d5a43964 | Alexander Graf | case EXCP_PGM:
|
787 | d5a43964 | Alexander Graf | do_program_interrupt(env); |
788 | d5a43964 | Alexander Graf | break;
|
789 | d5a43964 | Alexander Graf | case EXCP_SVC:
|
790 | d5a43964 | Alexander Graf | do_svc_interrupt(env); |
791 | d5a43964 | Alexander Graf | break;
|
792 | d5a43964 | Alexander Graf | case EXCP_EXT:
|
793 | d5a43964 | Alexander Graf | do_ext_interrupt(env); |
794 | d5a43964 | Alexander Graf | break;
|
795 | 5d69c547 | Cornelia Huck | case EXCP_IO:
|
796 | 5d69c547 | Cornelia Huck | do_io_interrupt(env); |
797 | 5d69c547 | Cornelia Huck | break;
|
798 | 5d69c547 | Cornelia Huck | case EXCP_MCHK:
|
799 | 5d69c547 | Cornelia Huck | do_mchk_interrupt(env); |
800 | 5d69c547 | Cornelia Huck | break;
|
801 | d5a43964 | Alexander Graf | } |
802 | d5a43964 | Alexander Graf | env->exception_index = -1;
|
803 | d5a43964 | Alexander Graf | |
804 | d5a43964 | Alexander Graf | if (!env->pending_int) {
|
805 | 259186a7 | Andreas Färber | cs->interrupt_request &= ~CPU_INTERRUPT_HARD; |
806 | d5a43964 | Alexander Graf | } |
807 | 3110e292 | Alexander Graf | } |
808 | d5a43964 | Alexander Graf | |
809 | d5a43964 | Alexander Graf | #endif /* CONFIG_USER_ONLY */ |