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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | 5fafdf24 | ths | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | d4e8164f | bellard | */
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19 | d4e8164f | bellard | |
20 | 875cdcf6 | aliguori | #ifndef _EXEC_ALL_H_
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21 | 875cdcf6 | aliguori | #define _EXEC_ALL_H_
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22 | 7d99a001 | blueswir1 | |
23 | 7d99a001 | blueswir1 | #include "qemu-common.h" |
24 | 7d99a001 | blueswir1 | |
25 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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26 | de9a95f0 | aurel32 | #define DEBUG_DISAS
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27 | b346ff46 | bellard | |
28 | 41c1b1c9 | Paul Brook | /* Page tracking code uses ram addresses in system mode, and virtual
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29 | 41c1b1c9 | Paul Brook | addresses in userspace mode. Define tb_page_addr_t to be an appropriate
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30 | 41c1b1c9 | Paul Brook | type. */
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31 | 41c1b1c9 | Paul Brook | #if defined(CONFIG_USER_ONLY)
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32 | b480d9b7 | Paul Brook | typedef abi_ulong tb_page_addr_t;
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33 | 41c1b1c9 | Paul Brook | #else
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34 | 41c1b1c9 | Paul Brook | typedef ram_addr_t tb_page_addr_t;
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35 | 41c1b1c9 | Paul Brook | #endif
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36 | 41c1b1c9 | Paul Brook | |
37 | b346ff46 | bellard | /* is_jmp field values */
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38 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
39 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
40 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
41 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
42 | b346ff46 | bellard | |
43 | 2e70f6ef | pbrook | typedef struct TranslationBlock TranslationBlock; |
44 | b346ff46 | bellard | |
45 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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46 | 7a86d29a | Alexander Graf | #if (HOST_LONG_BITS == 32) && (TARGET_LONG_BITS == 64) |
47 | 7a86d29a | Alexander Graf | #define MAX_OP_PER_INSTR 128 |
48 | 7a86d29a | Alexander Graf | #else
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49 | b689c622 | Aurelien Jarno | #define MAX_OP_PER_INSTR 96 |
50 | 7a86d29a | Alexander Graf | #endif
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51 | 4d0e4ac7 | Stuart Brady | |
52 | 4d0e4ac7 | Stuart Brady | #if HOST_LONG_BITS == 32 |
53 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_PER_ARG 2 |
54 | 4d0e4ac7 | Stuart Brady | #else
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55 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_PER_ARG 1 |
56 | 4d0e4ac7 | Stuart Brady | #endif
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57 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_IARGS 4 |
58 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_OARGS 1 |
59 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
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60 | 4d0e4ac7 | Stuart Brady | |
61 | 4d0e4ac7 | Stuart Brady | /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
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62 | 4d0e4ac7 | Stuart Brady | * and up to 4 + N parameters on 64-bit archs
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63 | 4d0e4ac7 | Stuart Brady | * (N = number of input arguments + output arguments). */
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64 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) |
65 | 6db73509 | Aurelien Jarno | #define OPC_BUF_SIZE 640 |
66 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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67 | b346ff46 | bellard | |
68 | a208e54a | pbrook | /* Maximum size a TCG op can expand to. This is complicated because a
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69 | 0cbfcd2b | Aurelien Jarno | single op may require several host instructions and register reloads.
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70 | 0cbfcd2b | Aurelien Jarno | For now take a wild guess at 192 bytes, which should allow at least
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71 | a208e54a | pbrook | a couple of fixup instructions per argument. */
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72 | 0cbfcd2b | Aurelien Jarno | #define TCG_MAX_OP_SIZE 192 |
73 | a208e54a | pbrook | |
74 | 0115be31 | pbrook | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
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75 | b346ff46 | bellard | |
76 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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77 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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78 | 2e70f6ef | pbrook | extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
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79 | b346ff46 | bellard | |
80 | 79383c9c | blueswir1 | #include "qemu-log.h" |
81 | b346ff46 | bellard | |
82 | 2cfc5f17 | ths | void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
83 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
84 | e87b7cb0 | Stefan Weil | void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb, |
85 | e87b7cb0 | Stefan Weil | int pc_pos);
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86 | d2856f1a | aurel32 | |
87 | 57fec1fe | bellard | void cpu_gen_init(void); |
88 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
89 | d07bde88 | blueswir1 | int *gen_code_size_ptr);
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90 | 5fafdf24 | ths | int cpu_restore_state(struct TranslationBlock *tb, |
91 | 618ba8e6 | Stefan Weil | CPUState *env, unsigned long searched_pc); |
92 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
93 | 2e70f6ef | pbrook | void cpu_io_recompile(CPUState *env, void *retaddr); |
94 | 2e70f6ef | pbrook | TranslationBlock *tb_gen_code(CPUState *env, |
95 | 2e70f6ef | pbrook | target_ulong pc, target_ulong cs_base, int flags,
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96 | 2e70f6ef | pbrook | int cflags);
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97 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
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98 | a5e50b26 | malc | void QEMU_NORETURN cpu_loop_exit(void); |
99 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
100 | 41c1b1c9 | Paul Brook | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
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101 | 2e12669a | bellard | int is_cpu_write_access);
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102 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
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103 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
104 | c527ee8f | Paul Brook | #if !defined(CONFIG_USER_ONLY)
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105 | d4c430a8 | Paul Brook | void tlb_set_page(CPUState *env, target_ulong vaddr,
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106 | d4c430a8 | Paul Brook | target_phys_addr_t paddr, int prot,
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107 | d4c430a8 | Paul Brook | int mmu_idx, target_ulong size);
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108 | c527ee8f | Paul Brook | #endif
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109 | d4e8164f | bellard | |
110 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
111 | d4e8164f | bellard | |
112 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
113 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
114 | 4390df51 | bellard | |
115 | 26a5f13b | bellard | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024) |
116 | d4e8164f | bellard | |
117 | 4390df51 | bellard | /* estimated block size for TB allocation */
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118 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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119 | 4390df51 | bellard | according to the host CPU */
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120 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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121 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
122 | 4390df51 | bellard | #else
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123 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
124 | 4390df51 | bellard | #endif
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125 | 4390df51 | bellard | |
126 | a8cd70fc | Filip Navara | #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
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127 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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128 | d4e8164f | bellard | #endif
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129 | d4e8164f | bellard | |
130 | 2e70f6ef | pbrook | struct TranslationBlock {
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131 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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132 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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133 | c068688b | j_mayer | uint64_t flags; /* flags defining in which context the code was generated */
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134 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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135 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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136 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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137 | 2e70f6ef | pbrook | #define CF_COUNT_MASK 0x7fff |
138 | 2e70f6ef | pbrook | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ |
139 | 58fe2f10 | bellard | |
140 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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141 | 4390df51 | bellard | /* next matching tb for physical address. */
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142 | 5fafdf24 | ths | struct TranslationBlock *phys_hash_next;
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143 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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144 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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145 | 5fafdf24 | ths | struct TranslationBlock *page_next[2]; |
146 | 41c1b1c9 | Paul Brook | tb_page_addr_t page_addr[2];
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147 | 4390df51 | bellard | |
148 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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149 | d4e8164f | bellard | the code of this one. */
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150 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
151 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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152 | efc0a514 | Filip Navara | uint16_t tb_jmp_offset[2]; /* offset of jump instruction */ |
153 | d4e8164f | bellard | #else
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154 | 57fec1fe | bellard | unsigned long tb_next[2]; /* address of jump generated code */ |
155 | d4e8164f | bellard | #endif
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156 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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157 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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158 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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159 | d4e8164f | bellard | jmp_first */
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160 | 5fafdf24 | ths | struct TranslationBlock *jmp_next[2]; |
161 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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162 | 2e70f6ef | pbrook | uint32_t icount; |
163 | 2e70f6ef | pbrook | }; |
164 | d4e8164f | bellard | |
165 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
166 | b362e5e0 | pbrook | { |
167 | b362e5e0 | pbrook | target_ulong tmp; |
168 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
169 | b5e19d4c | edgar_igl | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
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170 | b362e5e0 | pbrook | } |
171 | b362e5e0 | pbrook | |
172 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
173 | d4e8164f | bellard | { |
174 | b362e5e0 | pbrook | target_ulong tmp; |
175 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
176 | b5e19d4c | edgar_igl | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
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177 | b5e19d4c | edgar_igl | | (tmp & TB_JMP_ADDR_MASK)); |
178 | d4e8164f | bellard | } |
179 | d4e8164f | bellard | |
180 | 41c1b1c9 | Paul Brook | static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) |
181 | 4390df51 | bellard | { |
182 | f96a3834 | Aurelien Jarno | return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1); |
183 | 4390df51 | bellard | } |
184 | 4390df51 | bellard | |
185 | 2e70f6ef | pbrook | void tb_free(TranslationBlock *tb);
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186 | 0124311e | bellard | void tb_flush(CPUState *env);
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187 | 41c1b1c9 | Paul Brook | void tb_link_page(TranslationBlock *tb,
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188 | 41c1b1c9 | Paul Brook | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2); |
189 | 41c1b1c9 | Paul Brook | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
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190 | d4e8164f | bellard | |
191 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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192 | d4e8164f | bellard | |
193 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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194 | 4390df51 | bellard | |
195 | e58ffeb3 | malc | #if defined(_ARCH_PPC)
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196 | 64b85a8f | Blue Swirl | void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr); |
197 | 810260a8 | malc | #define tb_set_jmp_target1 ppc_tb_set_jmp_target
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198 | 57fec1fe | bellard | #elif defined(__i386__) || defined(__x86_64__)
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199 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
200 | 4390df51 | bellard | { |
201 | 4390df51 | bellard | /* patch the branch destination */
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202 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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203 | 1235fc06 | ths | /* no need to flush icache explicitly */
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204 | 4390df51 | bellard | } |
205 | 811d4cf4 | balrog | #elif defined(__arm__)
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206 | 811d4cf4 | balrog | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
207 | 811d4cf4 | balrog | { |
208 | 4a1e19ae | Aurelien Jarno | #if !QEMU_GNUC_PREREQ(4, 1) |
209 | 811d4cf4 | balrog | register unsigned long _beg __asm ("a1"); |
210 | 811d4cf4 | balrog | register unsigned long _end __asm ("a2"); |
211 | 811d4cf4 | balrog | register unsigned long _flg __asm ("a3"); |
212 | 3233f0d4 | balrog | #endif
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213 | 811d4cf4 | balrog | |
214 | 811d4cf4 | balrog | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
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215 | 87b78ad1 | Laurent Desnogues | *(uint32_t *)jmp_addr = |
216 | 87b78ad1 | Laurent Desnogues | (*(uint32_t *)jmp_addr & ~0xffffff)
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217 | 87b78ad1 | Laurent Desnogues | | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff); |
218 | 811d4cf4 | balrog | |
219 | 3233f0d4 | balrog | #if QEMU_GNUC_PREREQ(4, 1) |
220 | 4a1e19ae | Aurelien Jarno | __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); |
221 | 3233f0d4 | balrog | #else
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222 | 811d4cf4 | balrog | /* flush icache */
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223 | 811d4cf4 | balrog | _beg = jmp_addr; |
224 | 811d4cf4 | balrog | _end = jmp_addr + 4;
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225 | 811d4cf4 | balrog | _flg = 0;
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226 | 811d4cf4 | balrog | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
227 | 3233f0d4 | balrog | #endif
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228 | 811d4cf4 | balrog | } |
229 | 4390df51 | bellard | #endif
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230 | d4e8164f | bellard | |
231 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
232 | 4cbb86e1 | bellard | int n, unsigned long addr) |
233 | 4cbb86e1 | bellard | { |
234 | 4cbb86e1 | bellard | unsigned long offset; |
235 | 4cbb86e1 | bellard | |
236 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
237 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
238 | 4cbb86e1 | bellard | } |
239 | 4cbb86e1 | bellard | |
240 | d4e8164f | bellard | #else
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241 | d4e8164f | bellard | |
242 | d4e8164f | bellard | /* set the jump target */
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243 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
244 | d4e8164f | bellard | int n, unsigned long addr) |
245 | d4e8164f | bellard | { |
246 | 95f7652d | bellard | tb->tb_next[n] = addr; |
247 | d4e8164f | bellard | } |
248 | d4e8164f | bellard | |
249 | d4e8164f | bellard | #endif
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250 | d4e8164f | bellard | |
251 | 5fafdf24 | ths | static inline void tb_add_jump(TranslationBlock *tb, int n, |
252 | d4e8164f | bellard | TranslationBlock *tb_next) |
253 | d4e8164f | bellard | { |
254 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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255 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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256 | cf25629d | bellard | /* patch the native jump address */
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257 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
258 | 3b46e624 | ths | |
259 | cf25629d | bellard | /* add in TB jmp circular list */
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260 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
261 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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262 | cf25629d | bellard | } |
263 | d4e8164f | bellard | } |
264 | d4e8164f | bellard | |
265 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
266 | a513fe19 | bellard | |
267 | d5975363 | pbrook | #include "qemu-lock.h" |
268 | d4e8164f | bellard | |
269 | c227f099 | Anthony Liguori | extern spinlock_t tb_lock;
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270 | d4e8164f | bellard | |
271 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
272 | 6e59c1db | bellard | |
273 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
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274 | 6e59c1db | bellard | |
275 | b3755a91 | Paul Brook | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
276 | b3755a91 | Paul Brook | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
277 | b3755a91 | Paul Brook | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
278 | b3755a91 | Paul Brook | |
279 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
280 | 6e59c1db | bellard | void *retaddr);
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281 | 6e59c1db | bellard | |
282 | 79383c9c | blueswir1 | #include "softmmu_defs.h" |
283 | 79383c9c | blueswir1 | |
284 | 6ebbf390 | j_mayer | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
285 | 6e59c1db | bellard | #define MEMSUFFIX _code
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286 | 6e59c1db | bellard | #define env cpu_single_env
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287 | 6e59c1db | bellard | |
288 | 6e59c1db | bellard | #define DATA_SIZE 1 |
289 | 6e59c1db | bellard | #include "softmmu_header.h" |
290 | 6e59c1db | bellard | |
291 | 6e59c1db | bellard | #define DATA_SIZE 2 |
292 | 6e59c1db | bellard | #include "softmmu_header.h" |
293 | 6e59c1db | bellard | |
294 | 6e59c1db | bellard | #define DATA_SIZE 4 |
295 | 6e59c1db | bellard | #include "softmmu_header.h" |
296 | 6e59c1db | bellard | |
297 | c27004ec | bellard | #define DATA_SIZE 8 |
298 | c27004ec | bellard | #include "softmmu_header.h" |
299 | c27004ec | bellard | |
300 | 6e59c1db | bellard | #undef ACCESS_TYPE
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301 | 6e59c1db | bellard | #undef MEMSUFFIX
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302 | 6e59c1db | bellard | #undef env
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303 | 6e59c1db | bellard | |
304 | 6e59c1db | bellard | #endif
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305 | 4390df51 | bellard | |
306 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
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307 | 41c1b1c9 | Paul Brook | static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr) |
308 | 4390df51 | bellard | { |
309 | 4390df51 | bellard | return addr;
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310 | 4390df51 | bellard | } |
311 | 4390df51 | bellard | #else
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312 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
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313 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
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314 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
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315 | 41c1b1c9 | Paul Brook | static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr) |
316 | 4390df51 | bellard | { |
317 | 4d7a0880 | blueswir1 | int mmu_idx, page_index, pd;
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318 | 5579c7f3 | pbrook | void *p;
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319 | 4390df51 | bellard | |
320 | 4d7a0880 | blueswir1 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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321 | 4d7a0880 | blueswir1 | mmu_idx = cpu_mmu_index(env1); |
322 | 551bd27f | ths | if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
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323 | 551bd27f | ths | (addr & TARGET_PAGE_MASK))) { |
324 | c27004ec | bellard | ldub_code(addr); |
325 | c27004ec | bellard | } |
326 | 4d7a0880 | blueswir1 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; |
327 | 2a4188a3 | bellard | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
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328 | 647de6ca | ths | #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
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329 | e18231a3 | blueswir1 | do_unassigned_access(addr, 0, 1, 0, 4); |
330 | 6c36d3fa | blueswir1 | #else
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331 | 4d7a0880 | blueswir1 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
332 | 6c36d3fa | blueswir1 | #endif
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333 | 4390df51 | bellard | } |
334 | 5579c7f3 | pbrook | p = (void *)(unsigned long)addr |
335 | 5579c7f3 | pbrook | + env1->tlb_table[mmu_idx][page_index].addend; |
336 | e890261f | Marcelo Tosatti | return qemu_ram_addr_from_host_nofail(p);
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337 | 4390df51 | bellard | } |
338 | 4390df51 | bellard | #endif
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339 | 9df217a3 | bellard | |
340 | dde2367e | aliguori | typedef void (CPUDebugExcpHandler)(CPUState *env); |
341 | dde2367e | aliguori | |
342 | dde2367e | aliguori | CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler); |
343 | 1b530a6d | aurel32 | |
344 | 1b530a6d | aurel32 | /* vl.c */
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345 | 1b530a6d | aurel32 | extern int singlestep; |
346 | 1b530a6d | aurel32 | |
347 | 1a28cac3 | Marcelo Tosatti | /* cpu-exec.c */
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348 | 1a28cac3 | Marcelo Tosatti | extern volatile sig_atomic_t exit_request; |
349 | 1a28cac3 | Marcelo Tosatti | |
350 | 875cdcf6 | aliguori | #endif |