root / hw / ppce500_mpc8544ds.c @ 43997225
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1 | 1db09b84 | aurel32 | /*
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2 | 5cbdb3a3 | Stefan Weil | * QEMU PowerPC MPC8544DS board emulation
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3 | 1db09b84 | aurel32 | *
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4 | 1db09b84 | aurel32 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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5 | 1db09b84 | aurel32 | *
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6 | 1db09b84 | aurel32 | * Author: Yu Liu, <yu.liu@freescale.com>
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7 | 1db09b84 | aurel32 | *
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8 | 1db09b84 | aurel32 | * This file is derived from hw/ppc440_bamboo.c,
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9 | 1db09b84 | aurel32 | * the copyright for that material belongs to the original owners.
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10 | 1db09b84 | aurel32 | *
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11 | 1db09b84 | aurel32 | * This is free software; you can redistribute it and/or modify
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12 | 1db09b84 | aurel32 | * it under the terms of the GNU General Public License as published by
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13 | 1db09b84 | aurel32 | * the Free Software Foundation; either version 2 of the License, or
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14 | 1db09b84 | aurel32 | * (at your option) any later version.
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15 | 1db09b84 | aurel32 | */
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16 | 1db09b84 | aurel32 | |
17 | 1db09b84 | aurel32 | #include "config.h" |
18 | 1db09b84 | aurel32 | #include "qemu-common.h" |
19 | 1db09b84 | aurel32 | #include "net.h" |
20 | 1db09b84 | aurel32 | #include "hw.h" |
21 | 1db09b84 | aurel32 | #include "pc.h" |
22 | 1db09b84 | aurel32 | #include "pci.h" |
23 | 1db09b84 | aurel32 | #include "boards.h" |
24 | 1db09b84 | aurel32 | #include "sysemu.h" |
25 | 1db09b84 | aurel32 | #include "kvm.h" |
26 | 1db09b84 | aurel32 | #include "kvm_ppc.h" |
27 | 1db09b84 | aurel32 | #include "device_tree.h" |
28 | 1db09b84 | aurel32 | #include "openpic.h" |
29 | 3b989d49 | Alexander Graf | #include "ppc.h" |
30 | ca20cf32 | Blue Swirl | #include "loader.h" |
31 | ca20cf32 | Blue Swirl | #include "elf.h" |
32 | be13cc7a | Alexander Graf | #include "sysbus.h" |
33 | 39186d8a | Richard Henderson | #include "exec-memory.h" |
34 | 1db09b84 | aurel32 | |
35 | 1db09b84 | aurel32 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" |
36 | 1db09b84 | aurel32 | #define UIMAGE_LOAD_BASE 0 |
37 | 75bb6589 | Liu Yu | #define DTC_LOAD_PAD 0x500000 |
38 | 75bb6589 | Liu Yu | #define DTC_PAD_MASK 0xFFFFF |
39 | 75bb6589 | Liu Yu | #define INITRD_LOAD_PAD 0x2000000 |
40 | 75bb6589 | Liu Yu | #define INITRD_PAD_MASK 0xFFFFFF |
41 | 1db09b84 | aurel32 | |
42 | 1db09b84 | aurel32 | #define RAM_SIZES_ALIGN (64UL << 20) |
43 | 1db09b84 | aurel32 | |
44 | 1db09b84 | aurel32 | #define MPC8544_CCSRBAR_BASE 0xE0000000 |
45 | 1db09b84 | aurel32 | #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000) |
46 | 1db09b84 | aurel32 | #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500) |
47 | 1db09b84 | aurel32 | #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600) |
48 | 1db09b84 | aurel32 | #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000) |
49 | 1db09b84 | aurel32 | #define MPC8544_PCI_REGS_SIZE 0x1000 |
50 | 1db09b84 | aurel32 | #define MPC8544_PCI_IO 0xE1000000 |
51 | 1db09b84 | aurel32 | #define MPC8544_PCI_IOLEN 0x10000 |
52 | b0fb8423 | Alexander Graf | #define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000) |
53 | 5c145dac | Alexander Graf | #define MPC8544_SPIN_BASE 0xEF000000 |
54 | 1db09b84 | aurel32 | |
55 | 3b989d49 | Alexander Graf | struct boot_info
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56 | 3b989d49 | Alexander Graf | { |
57 | 3b989d49 | Alexander Graf | uint32_t dt_base; |
58 | 3b989d49 | Alexander Graf | uint32_t entry; |
59 | 3b989d49 | Alexander Graf | }; |
60 | 3b989d49 | Alexander Graf | |
61 | e2684c0b | Andreas Färber | static int mpc8544_load_device_tree(CPUPPCState *env, |
62 | 5de6b46d | Alexander Graf | target_phys_addr_t addr, |
63 | 5de6b46d | Alexander Graf | uint32_t ramsize, |
64 | 5de6b46d | Alexander Graf | target_phys_addr_t initrd_base, |
65 | 5de6b46d | Alexander Graf | target_phys_addr_t initrd_size, |
66 | 5de6b46d | Alexander Graf | const char *kernel_cmdline) |
67 | 1db09b84 | aurel32 | { |
68 | dbf916d8 | Aurelien Jarno | int ret = -1; |
69 | 3f0855b1 | Juan Quintela | #ifdef CONFIG_FDT
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70 | 3b989d49 | Alexander Graf | uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)};
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71 | 5cea8590 | Paul Brook | char *filename;
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72 | 7ec632b4 | pbrook | int fdt_size;
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73 | dbf916d8 | Aurelien Jarno | void *fdt;
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74 | 5de6b46d | Alexander Graf | uint8_t hypercall[16];
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75 | 911d6e7a | Alexander Graf | uint32_t clock_freq = 400000000;
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76 | 911d6e7a | Alexander Graf | uint32_t tb_freq = 400000000;
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77 | 621d05e3 | Alexander Graf | int i;
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78 | 1db09b84 | aurel32 | |
79 | 5cea8590 | Paul Brook | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); |
80 | 5cea8590 | Paul Brook | if (!filename) {
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81 | 1db09b84 | aurel32 | goto out;
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82 | 5cea8590 | Paul Brook | } |
83 | 5cea8590 | Paul Brook | fdt = load_device_tree(filename, &fdt_size); |
84 | 7267c094 | Anthony Liguori | g_free(filename); |
85 | 5cea8590 | Paul Brook | if (fdt == NULL) { |
86 | 5cea8590 | Paul Brook | goto out;
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87 | 5cea8590 | Paul Brook | } |
88 | 1db09b84 | aurel32 | |
89 | 1db09b84 | aurel32 | /* Manipulate device tree in memory. */
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90 | 1db09b84 | aurel32 | ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, |
91 | 1db09b84 | aurel32 | sizeof(mem_reg_property));
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92 | 1db09b84 | aurel32 | if (ret < 0) |
93 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't set /memory/reg\n");
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94 | 1db09b84 | aurel32 | |
95 | 3b989d49 | Alexander Graf | if (initrd_size) {
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96 | 3b989d49 | Alexander Graf | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", |
97 | 3b989d49 | Alexander Graf | initrd_base); |
98 | 3b989d49 | Alexander Graf | if (ret < 0) { |
99 | 3b989d49 | Alexander Graf | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
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100 | 3b989d49 | Alexander Graf | } |
101 | 1db09b84 | aurel32 | |
102 | 3b989d49 | Alexander Graf | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
103 | 3b989d49 | Alexander Graf | (initrd_base + initrd_size)); |
104 | 3b989d49 | Alexander Graf | if (ret < 0) { |
105 | 3b989d49 | Alexander Graf | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
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106 | 3b989d49 | Alexander Graf | } |
107 | 3b989d49 | Alexander Graf | } |
108 | 1db09b84 | aurel32 | |
109 | 1db09b84 | aurel32 | ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", |
110 | 1db09b84 | aurel32 | kernel_cmdline); |
111 | 1db09b84 | aurel32 | if (ret < 0) |
112 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't set /chosen/bootargs\n");
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113 | 1db09b84 | aurel32 | |
114 | 1db09b84 | aurel32 | if (kvm_enabled()) {
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115 | 911d6e7a | Alexander Graf | /* Read out host's frequencies */
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116 | 911d6e7a | Alexander Graf | clock_freq = kvmppc_get_clockfreq(); |
117 | 911d6e7a | Alexander Graf | tb_freq = kvmppc_get_tbfreq(); |
118 | 5de6b46d | Alexander Graf | |
119 | 5de6b46d | Alexander Graf | /* indicate KVM hypercall interface */
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120 | 5de6b46d | Alexander Graf | qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", |
121 | 5de6b46d | Alexander Graf | "linux,kvm");
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122 | 5de6b46d | Alexander Graf | kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
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123 | 5de6b46d | Alexander Graf | qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", |
124 | 5de6b46d | Alexander Graf | hypercall, sizeof(hypercall));
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125 | 1db09b84 | aurel32 | } |
126 | 3b989d49 | Alexander Graf | |
127 | 1e3debf0 | Alexander Graf | /* We need to generate the cpu nodes in reverse order, so Linux can pick
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128 | 1e3debf0 | Alexander Graf | the first node as boot node and be happy */
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129 | 1e3debf0 | Alexander Graf | for (i = smp_cpus - 1; i >= 0; i--) { |
130 | 621d05e3 | Alexander Graf | char cpu_name[128]; |
131 | 1e3debf0 | Alexander Graf | uint64_t cpu_release_addr = cpu_to_be64(MPC8544_SPIN_BASE + (i * 0x20));
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132 | 10f25a46 | Alexander Graf | |
133 | 1e3debf0 | Alexander Graf | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
134 | 1e3debf0 | Alexander Graf | if (env->cpu_index == i) {
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135 | 1e3debf0 | Alexander Graf | break;
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136 | 1e3debf0 | Alexander Graf | } |
137 | 1e3debf0 | Alexander Graf | } |
138 | 1e3debf0 | Alexander Graf | |
139 | 1e3debf0 | Alexander Graf | if (!env) {
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140 | 1e3debf0 | Alexander Graf | continue;
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141 | 1e3debf0 | Alexander Graf | } |
142 | 1e3debf0 | Alexander Graf | |
143 | 1e3debf0 | Alexander Graf | snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index); |
144 | 1e3debf0 | Alexander Graf | qemu_devtree_add_subnode(fdt, cpu_name); |
145 | 621d05e3 | Alexander Graf | qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
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146 | 621d05e3 | Alexander Graf | qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
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147 | 1e3debf0 | Alexander Graf | qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); |
148 | 1e3debf0 | Alexander Graf | qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);
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149 | 1e3debf0 | Alexander Graf | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
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150 | 1e3debf0 | Alexander Graf | env->dcache_line_size); |
151 | 1e3debf0 | Alexander Graf | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
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152 | 1e3debf0 | Alexander Graf | env->icache_line_size); |
153 | 1e3debf0 | Alexander Graf | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); |
154 | 1e3debf0 | Alexander Graf | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); |
155 | 1e3debf0 | Alexander Graf | qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); |
156 | 1e3debf0 | Alexander Graf | if (env->cpu_index) {
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157 | 1e3debf0 | Alexander Graf | qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); |
158 | 1e3debf0 | Alexander Graf | qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); |
159 | 1e3debf0 | Alexander Graf | qemu_devtree_setprop(fdt, cpu_name, "cpu-release-addr",
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160 | 1e3debf0 | Alexander Graf | &cpu_release_addr, sizeof(cpu_release_addr));
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161 | 1e3debf0 | Alexander Graf | } else {
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162 | 1e3debf0 | Alexander Graf | qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); |
163 | 1e3debf0 | Alexander Graf | } |
164 | 1db09b84 | aurel32 | } |
165 | 1db09b84 | aurel32 | |
166 | 04088adb | Liu Yu | ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
167 | 7267c094 | Anthony Liguori | g_free(fdt); |
168 | 7ec632b4 | pbrook | |
169 | 1db09b84 | aurel32 | out:
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170 | 1db09b84 | aurel32 | #endif
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171 | 1db09b84 | aurel32 | |
172 | 04088adb | Liu Yu | return ret;
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173 | 1db09b84 | aurel32 | } |
174 | 1db09b84 | aurel32 | |
175 | 3b989d49 | Alexander Graf | /* Create -kernel TLB entries for BookE, linearly spanning 256MB. */
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176 | d1e256fe | Alexander Graf | static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) |
177 | d1e256fe | Alexander Graf | { |
178 | 2bd9543c | Scott Wood | return ffs(size >> 10) - 1; |
179 | d1e256fe | Alexander Graf | } |
180 | d1e256fe | Alexander Graf | |
181 | e2684c0b | Andreas Färber | static void mmubooke_create_initial_mapping(CPUPPCState *env, |
182 | 3b989d49 | Alexander Graf | target_ulong va, |
183 | 3b989d49 | Alexander Graf | target_phys_addr_t pa) |
184 | 3b989d49 | Alexander Graf | { |
185 | d1e256fe | Alexander Graf | ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); |
186 | d1e256fe | Alexander Graf | target_phys_addr_t size; |
187 | d1e256fe | Alexander Graf | |
188 | d1e256fe | Alexander Graf | size = (booke206_page_size_to_tlb(256 * 1024 * 1024) << MAS1_TSIZE_SHIFT); |
189 | d1e256fe | Alexander Graf | tlb->mas1 = MAS1_VALID | size; |
190 | d1e256fe | Alexander Graf | tlb->mas2 = va & TARGET_PAGE_MASK; |
191 | d1e256fe | Alexander Graf | tlb->mas7_3 = pa & TARGET_PAGE_MASK; |
192 | d1e256fe | Alexander Graf | tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; |
193 | 93dd5e85 | Scott Wood | |
194 | 93dd5e85 | Scott Wood | env->tlb_dirty = true;
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195 | 3b989d49 | Alexander Graf | } |
196 | 3b989d49 | Alexander Graf | |
197 | 5c145dac | Alexander Graf | static void mpc8544ds_cpu_reset_sec(void *opaque) |
198 | 5c145dac | Alexander Graf | { |
199 | e2684c0b | Andreas Färber | CPUPPCState *env = opaque; |
200 | 5c145dac | Alexander Graf | |
201 | 1bba0dc9 | Andreas Färber | cpu_state_reset(env); |
202 | 5c145dac | Alexander Graf | |
203 | 5c145dac | Alexander Graf | /* Secondary CPU starts in halted state for now. Needs to change when
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204 | 5c145dac | Alexander Graf | implementing non-kernel boot. */
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205 | 5c145dac | Alexander Graf | env->halted = 1;
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206 | 5c145dac | Alexander Graf | env->exception_index = EXCP_HLT; |
207 | 3b989d49 | Alexander Graf | } |
208 | 3b989d49 | Alexander Graf | |
209 | 3b989d49 | Alexander Graf | static void mpc8544ds_cpu_reset(void *opaque) |
210 | 3b989d49 | Alexander Graf | { |
211 | e2684c0b | Andreas Färber | CPUPPCState *env = opaque; |
212 | 3b989d49 | Alexander Graf | struct boot_info *bi = env->load_info;
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213 | 3b989d49 | Alexander Graf | |
214 | 1bba0dc9 | Andreas Färber | cpu_state_reset(env); |
215 | 3b989d49 | Alexander Graf | |
216 | 3b989d49 | Alexander Graf | /* Set initial guest state. */
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217 | 5c145dac | Alexander Graf | env->halted = 0;
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218 | 3b989d49 | Alexander Graf | env->gpr[1] = (16<<20) - 8; |
219 | 3b989d49 | Alexander Graf | env->gpr[3] = bi->dt_base;
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220 | 3b989d49 | Alexander Graf | env->nip = bi->entry; |
221 | 3b989d49 | Alexander Graf | mmubooke_create_initial_mapping(env, 0, 0); |
222 | 3b989d49 | Alexander Graf | } |
223 | 3b989d49 | Alexander Graf | |
224 | c227f099 | Anthony Liguori | static void mpc8544ds_init(ram_addr_t ram_size, |
225 | 1db09b84 | aurel32 | const char *boot_device, |
226 | 1db09b84 | aurel32 | const char *kernel_filename, |
227 | 1db09b84 | aurel32 | const char *kernel_cmdline, |
228 | 1db09b84 | aurel32 | const char *initrd_filename, |
229 | 1db09b84 | aurel32 | const char *cpu_model) |
230 | 1db09b84 | aurel32 | { |
231 | 39186d8a | Richard Henderson | MemoryRegion *address_space_mem = get_system_memory(); |
232 | 2646c133 | Avi Kivity | MemoryRegion *ram = g_new(MemoryRegion, 1);
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233 | 1db09b84 | aurel32 | PCIBus *pci_bus; |
234 | e2684c0b | Andreas Färber | CPUPPCState *env = NULL;
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235 | 1db09b84 | aurel32 | uint64_t elf_entry; |
236 | 1db09b84 | aurel32 | uint64_t elf_lowaddr; |
237 | c227f099 | Anthony Liguori | target_phys_addr_t entry=0;
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238 | c227f099 | Anthony Liguori | target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE; |
239 | 1db09b84 | aurel32 | target_long kernel_size=0;
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240 | 75bb6589 | Liu Yu | target_ulong dt_base = 0;
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241 | 75bb6589 | Liu Yu | target_ulong initrd_base = 0;
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242 | 1db09b84 | aurel32 | target_long initrd_size=0;
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243 | 1db09b84 | aurel32 | int i=0; |
244 | 1db09b84 | aurel32 | unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; |
245 | a915249f | Alexander Graf | qemu_irq **irqs, *mpic; |
246 | be13cc7a | Alexander Graf | DeviceState *dev; |
247 | e2684c0b | Andreas Färber | CPUPPCState *firstenv = NULL;
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248 | 1db09b84 | aurel32 | |
249 | e61c36d5 | Alexander Graf | /* Setup CPUs */
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250 | ef250db6 | Alexander Graf | if (cpu_model == NULL) { |
251 | ef250db6 | Alexander Graf | cpu_model = "e500v2_v30";
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252 | ef250db6 | Alexander Graf | } |
253 | ef250db6 | Alexander Graf | |
254 | a915249f | Alexander Graf | irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
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255 | a915249f | Alexander Graf | irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); |
256 | e61c36d5 | Alexander Graf | for (i = 0; i < smp_cpus; i++) { |
257 | e61c36d5 | Alexander Graf | qemu_irq *input; |
258 | e61c36d5 | Alexander Graf | env = cpu_ppc_init(cpu_model); |
259 | e61c36d5 | Alexander Graf | if (!env) {
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260 | e61c36d5 | Alexander Graf | fprintf(stderr, "Unable to initialize CPU!\n");
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261 | e61c36d5 | Alexander Graf | exit(1);
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262 | e61c36d5 | Alexander Graf | } |
263 | 1db09b84 | aurel32 | |
264 | e61c36d5 | Alexander Graf | if (!firstenv) {
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265 | e61c36d5 | Alexander Graf | firstenv = env; |
266 | e61c36d5 | Alexander Graf | } |
267 | 1db09b84 | aurel32 | |
268 | a915249f | Alexander Graf | irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
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269 | a915249f | Alexander Graf | input = (qemu_irq *)env->irq_inputs; |
270 | a915249f | Alexander Graf | irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; |
271 | a915249f | Alexander Graf | irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; |
272 | e61c36d5 | Alexander Graf | env->spr[SPR_BOOKE_PIR] = env->cpu_index = i; |
273 | 3b989d49 | Alexander Graf | |
274 | ddd1055b | Fabien Chouteau | ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500);
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275 | e61c36d5 | Alexander Graf | |
276 | e61c36d5 | Alexander Graf | /* Register reset handler */
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277 | 5c145dac | Alexander Graf | if (!i) {
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278 | 5c145dac | Alexander Graf | /* Primary CPU */
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279 | 5c145dac | Alexander Graf | struct boot_info *boot_info;
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280 | 5c145dac | Alexander Graf | boot_info = g_malloc0(sizeof(struct boot_info)); |
281 | 5c145dac | Alexander Graf | qemu_register_reset(mpc8544ds_cpu_reset, env); |
282 | 5c145dac | Alexander Graf | env->load_info = boot_info; |
283 | 5c145dac | Alexander Graf | } else {
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284 | 5c145dac | Alexander Graf | /* Secondary CPUs */
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285 | 5c145dac | Alexander Graf | qemu_register_reset(mpc8544ds_cpu_reset_sec, env); |
286 | 5c145dac | Alexander Graf | } |
287 | e61c36d5 | Alexander Graf | } |
288 | 3b989d49 | Alexander Graf | |
289 | e61c36d5 | Alexander Graf | env = firstenv; |
290 | 3b989d49 | Alexander Graf | |
291 | 1db09b84 | aurel32 | /* Fixup Memory size on a alignment boundary */
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292 | 1db09b84 | aurel32 | ram_size &= ~(RAM_SIZES_ALIGN - 1);
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293 | 1db09b84 | aurel32 | |
294 | 1db09b84 | aurel32 | /* Register Memory */
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295 | c5705a77 | Avi Kivity | memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
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296 | c5705a77 | Avi Kivity | vmstate_register_ram_global(ram); |
297 | 2646c133 | Avi Kivity | memory_region_add_subregion(address_space_mem, 0, ram);
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298 | 1db09b84 | aurel32 | |
299 | 1db09b84 | aurel32 | /* MPIC */
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300 | df2921d3 | Avi Kivity | mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE, |
301 | df2921d3 | Avi Kivity | smp_cpus, irqs, NULL);
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302 | a915249f | Alexander Graf | |
303 | a915249f | Alexander Graf | if (!mpic) {
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304 | a915249f | Alexander Graf | cpu_abort(env, "MPIC failed to initialize\n");
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305 | a915249f | Alexander Graf | } |
306 | 1db09b84 | aurel32 | |
307 | 1db09b84 | aurel32 | /* Serial */
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308 | 2d48377a | Blue Swirl | if (serial_hds[0]) { |
309 | 39186d8a | Richard Henderson | serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE, |
310 | 49a2942d | Blue Swirl | 0, mpic[12+26], 399193, |
311 | 2ff0c7c3 | Richard Henderson | serial_hds[0], DEVICE_BIG_ENDIAN);
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312 | 2d48377a | Blue Swirl | } |
313 | 1db09b84 | aurel32 | |
314 | 2d48377a | Blue Swirl | if (serial_hds[1]) { |
315 | 39186d8a | Richard Henderson | serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE, |
316 | 49a2942d | Blue Swirl | 0, mpic[12+26], 399193, |
317 | 2ff0c7c3 | Richard Henderson | serial_hds[0], DEVICE_BIG_ENDIAN);
|
318 | 2d48377a | Blue Swirl | } |
319 | 1db09b84 | aurel32 | |
320 | b0fb8423 | Alexander Graf | /* General Utility device */
|
321 | b0fb8423 | Alexander Graf | sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL); |
322 | b0fb8423 | Alexander Graf | |
323 | 1db09b84 | aurel32 | /* PCI */
|
324 | be13cc7a | Alexander Graf | dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
|
325 | be13cc7a | Alexander Graf | mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]], |
326 | be13cc7a | Alexander Graf | mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]], |
327 | be13cc7a | Alexander Graf | NULL);
|
328 | d461e3b9 | Alexander Graf | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
|
329 | 1db09b84 | aurel32 | if (!pci_bus)
|
330 | 1db09b84 | aurel32 | printf("couldn't create PCI controller!\n");
|
331 | 1db09b84 | aurel32 | |
332 | 968d683c | Alexander Graf | isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); |
333 | 1db09b84 | aurel32 | |
334 | 1db09b84 | aurel32 | if (pci_bus) {
|
335 | 1db09b84 | aurel32 | /* Register network interfaces. */
|
336 | 1db09b84 | aurel32 | for (i = 0; i < nb_nics; i++) { |
337 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "virtio", NULL); |
338 | 1db09b84 | aurel32 | } |
339 | 1db09b84 | aurel32 | } |
340 | 1db09b84 | aurel32 | |
341 | 5c145dac | Alexander Graf | /* Register spinning region */
|
342 | 5c145dac | Alexander Graf | sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); |
343 | 5c145dac | Alexander Graf | |
344 | 1db09b84 | aurel32 | /* Load kernel. */
|
345 | 1db09b84 | aurel32 | if (kernel_filename) {
|
346 | 1db09b84 | aurel32 | kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
|
347 | 1db09b84 | aurel32 | if (kernel_size < 0) { |
348 | 409dbce5 | Aurelien Jarno | kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, |
349 | 409dbce5 | Aurelien Jarno | &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); |
350 | 1db09b84 | aurel32 | entry = elf_entry; |
351 | 1db09b84 | aurel32 | loadaddr = elf_lowaddr; |
352 | 1db09b84 | aurel32 | } |
353 | 1db09b84 | aurel32 | /* XXX try again as binary */
|
354 | 1db09b84 | aurel32 | if (kernel_size < 0) { |
355 | 1db09b84 | aurel32 | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
356 | 1db09b84 | aurel32 | kernel_filename); |
357 | 1db09b84 | aurel32 | exit(1);
|
358 | 1db09b84 | aurel32 | } |
359 | 1db09b84 | aurel32 | } |
360 | 1db09b84 | aurel32 | |
361 | 1db09b84 | aurel32 | /* Load initrd. */
|
362 | 1db09b84 | aurel32 | if (initrd_filename) {
|
363 | 75bb6589 | Liu Yu | initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; |
364 | d7585251 | pbrook | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
365 | d7585251 | pbrook | ram_size - initrd_base); |
366 | 1db09b84 | aurel32 | |
367 | 1db09b84 | aurel32 | if (initrd_size < 0) { |
368 | 1db09b84 | aurel32 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
369 | 1db09b84 | aurel32 | initrd_filename); |
370 | 1db09b84 | aurel32 | exit(1);
|
371 | 1db09b84 | aurel32 | } |
372 | 1db09b84 | aurel32 | } |
373 | 1db09b84 | aurel32 | |
374 | 1db09b84 | aurel32 | /* If we're loading a kernel directly, we must load the device tree too. */
|
375 | 1db09b84 | aurel32 | if (kernel_filename) {
|
376 | 5c145dac | Alexander Graf | struct boot_info *boot_info;
|
377 | 5c145dac | Alexander Graf | |
378 | 3b989d49 | Alexander Graf | #ifndef CONFIG_FDT
|
379 | 3b989d49 | Alexander Graf | cpu_abort(env, "Compiled without FDT support - can't load kernel\n");
|
380 | 3b989d49 | Alexander Graf | #endif
|
381 | 75bb6589 | Liu Yu | dt_base = (kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
382 | 5de6b46d | Alexander Graf | if (mpc8544_load_device_tree(env, dt_base, ram_size,
|
383 | 04088adb | Liu Yu | initrd_base, initrd_size, kernel_cmdline) < 0) {
|
384 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't load device tree\n");
|
385 | 1db09b84 | aurel32 | exit(1);
|
386 | 1db09b84 | aurel32 | } |
387 | 1db09b84 | aurel32 | |
388 | e61c36d5 | Alexander Graf | boot_info = env->load_info; |
389 | 3b989d49 | Alexander Graf | boot_info->entry = entry; |
390 | 3b989d49 | Alexander Graf | boot_info->dt_base = dt_base; |
391 | 1db09b84 | aurel32 | } |
392 | 1db09b84 | aurel32 | |
393 | 3b989d49 | Alexander Graf | if (kvm_enabled()) {
|
394 | 1db09b84 | aurel32 | kvmppc_init(); |
395 | 3b989d49 | Alexander Graf | } |
396 | 1db09b84 | aurel32 | } |
397 | 1db09b84 | aurel32 | |
398 | f80f9ec9 | Anthony Liguori | static QEMUMachine mpc8544ds_machine = {
|
399 | 1db09b84 | aurel32 | .name = "mpc8544ds",
|
400 | 1db09b84 | aurel32 | .desc = "mpc8544ds",
|
401 | 1db09b84 | aurel32 | .init = mpc8544ds_init, |
402 | a2a67420 | Alexander Graf | .max_cpus = 15,
|
403 | 1db09b84 | aurel32 | }; |
404 | f80f9ec9 | Anthony Liguori | |
405 | f80f9ec9 | Anthony Liguori | static void mpc8544ds_machine_init(void) |
406 | f80f9ec9 | Anthony Liguori | { |
407 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mpc8544ds_machine); |
408 | f80f9ec9 | Anthony Liguori | } |
409 | f80f9ec9 | Anthony Liguori | |
410 | f80f9ec9 | Anthony Liguori | machine_init(mpc8544ds_machine_init); |