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1 | 3475187d | bellard | /*
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2 | c7ba218d | blueswir1 | * QEMU Sun4u/Sun4v System Emulator
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 18e08a55 | Michael S. Tsirkin | #include "apb_pci.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 87ecb68b | pbrook | #include "nvram.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "net.h" |
31 | 87ecb68b | pbrook | #include "qemu-timer.h" |
32 | 87ecb68b | pbrook | #include "sysemu.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
35 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
36 | 1baffa46 | Blue Swirl | #include "sysbus.h" |
37 | 977e1244 | Gerd Hoffmann | #include "ide.h" |
38 | ca20cf32 | Blue Swirl | #include "loader.h" |
39 | ca20cf32 | Blue Swirl | #include "elf.h" |
40 | 2446333c | Blue Swirl | #include "blockdev.h" |
41 | 3475187d | bellard | |
42 | 9d926598 | blueswir1 | //#define DEBUG_IRQ
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43 | b430a225 | Blue Swirl | //#define DEBUG_EBUS
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44 | 8f4efc55 | Igor V. Kovalenko | //#define DEBUG_TIMER
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45 | 9d926598 | blueswir1 | |
46 | 9d926598 | blueswir1 | #ifdef DEBUG_IRQ
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47 | b430a225 | Blue Swirl | #define CPUIRQ_DPRINTF(fmt, ...) \
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48 | 001faf32 | Blue Swirl | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
49 | 9d926598 | blueswir1 | #else
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50 | b430a225 | Blue Swirl | #define CPUIRQ_DPRINTF(fmt, ...)
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51 | b430a225 | Blue Swirl | #endif
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52 | b430a225 | Blue Swirl | |
53 | b430a225 | Blue Swirl | #ifdef DEBUG_EBUS
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54 | b430a225 | Blue Swirl | #define EBUS_DPRINTF(fmt, ...) \
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55 | b430a225 | Blue Swirl | do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) |
56 | b430a225 | Blue Swirl | #else
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57 | b430a225 | Blue Swirl | #define EBUS_DPRINTF(fmt, ...)
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58 | 9d926598 | blueswir1 | #endif
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59 | 9d926598 | blueswir1 | |
60 | 8f4efc55 | Igor V. Kovalenko | #ifdef DEBUG_TIMER
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61 | 8f4efc55 | Igor V. Kovalenko | #define TIMER_DPRINTF(fmt, ...) \
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62 | 8f4efc55 | Igor V. Kovalenko | do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) |
63 | 8f4efc55 | Igor V. Kovalenko | #else
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64 | 8f4efc55 | Igor V. Kovalenko | #define TIMER_DPRINTF(fmt, ...)
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65 | 8f4efc55 | Igor V. Kovalenko | #endif
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66 | 8f4efc55 | Igor V. Kovalenko | |
67 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
68 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
69 | 83469015 | bellard | #define INITRD_LOAD_ADDR 0x00300000 |
70 | ac2e9d66 | blueswir1 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
71 | f930d07e | blueswir1 | #define PROM_VADDR 0x000ffd00000ULL |
72 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
73 | f930d07e | blueswir1 | #define APB_MEM_BASE 0x1ff00000000ULL |
74 | d63baf92 | Igor V. Kovalenko | #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) |
75 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc64" |
76 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
77 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
78 | 3cce6243 | blueswir1 | #define BIOS_CFG_IOPORT 0x510 |
79 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
80 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
81 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
82 | 3475187d | bellard | |
83 | 9d926598 | blueswir1 | #define MAX_PILS 16 |
84 | 9d926598 | blueswir1 | |
85 | 8fa211e8 | blueswir1 | #define TICK_MAX 0x7fffffffffffffffULL |
86 | 8fa211e8 | blueswir1 | |
87 | c7ba218d | blueswir1 | struct hwdef {
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88 | c7ba218d | blueswir1 | const char * const default_cpu_model; |
89 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
90 | e87231d4 | blueswir1 | uint64_t prom_addr; |
91 | e87231d4 | blueswir1 | uint64_t console_serial_base; |
92 | c7ba218d | blueswir1 | }; |
93 | c7ba218d | blueswir1 | |
94 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
95 | 3475187d | bellard | { |
96 | 3475187d | bellard | return 0; |
97 | 3475187d | bellard | } |
98 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
99 | 3475187d | bellard | { |
100 | 3475187d | bellard | return 0; |
101 | 3475187d | bellard | } |
102 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
103 | 3475187d | bellard | { |
104 | 3475187d | bellard | return 0; |
105 | 3475187d | bellard | } |
106 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
107 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
108 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
109 | 4556bd8b | Blue Swirl | |
110 | 4556bd8b | Blue Swirl | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
111 | 4556bd8b | Blue Swirl | { |
112 | 4556bd8b | Blue Swirl | } |
113 | 4556bd8b | Blue Swirl | |
114 | 3475187d | bellard | void DMA_register_channel (int nchan, |
115 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
116 | 3475187d | bellard | void *opaque)
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117 | 3475187d | bellard | { |
118 | 3475187d | bellard | } |
119 | 3475187d | bellard | |
120 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
121 | 81864572 | blueswir1 | { |
122 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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123 | 81864572 | blueswir1 | return 0; |
124 | 81864572 | blueswir1 | } |
125 | 81864572 | blueswir1 | |
126 | 43a34704 | Blue Swirl | static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size, |
127 | 43a34704 | Blue Swirl | const char *arch, ram_addr_t RAM_size, |
128 | 43a34704 | Blue Swirl | const char *boot_devices, |
129 | 43a34704 | Blue Swirl | uint32_t kernel_image, uint32_t kernel_size, |
130 | 43a34704 | Blue Swirl | const char *cmdline, |
131 | 43a34704 | Blue Swirl | uint32_t initrd_image, uint32_t initrd_size, |
132 | 43a34704 | Blue Swirl | uint32_t NVRAM_image, |
133 | 43a34704 | Blue Swirl | int width, int height, int depth, |
134 | 43a34704 | Blue Swirl | const uint8_t *macaddr)
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135 | 83469015 | bellard | { |
136 | 66508601 | blueswir1 | unsigned int i; |
137 | 66508601 | blueswir1 | uint32_t start, end; |
138 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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139 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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140 | d2c63fc1 | blueswir1 | |
141 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
142 | d2c63fc1 | blueswir1 | |
143 | 513f789f | blueswir1 | start = 0;
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144 | 83469015 | bellard | |
145 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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146 | 66508601 | blueswir1 | // Variable partition
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147 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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148 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
149 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
150 | 66508601 | blueswir1 | |
151 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
152 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
153 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
154 | d2c63fc1 | blueswir1 | |
155 | d2c63fc1 | blueswir1 | // End marker
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156 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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157 | 66508601 | blueswir1 | |
158 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
159 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
160 | 66508601 | blueswir1 | |
161 | 66508601 | blueswir1 | // free partition
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162 | 66508601 | blueswir1 | start = end; |
163 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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164 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
165 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
166 | 66508601 | blueswir1 | |
167 | 66508601 | blueswir1 | end = 0x1fd0;
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168 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
169 | d2c63fc1 | blueswir1 | |
170 | 0d31cb99 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
171 | 0d31cb99 | blueswir1 | |
172 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
173 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
174 | 66508601 | blueswir1 | |
175 | 83469015 | bellard | return 0; |
176 | 3475187d | bellard | } |
177 | 636aa70a | Blue Swirl | static unsigned long sun4u_load_kernel(const char *kernel_filename, |
178 | 636aa70a | Blue Swirl | const char *initrd_filename, |
179 | c227f099 | Anthony Liguori | ram_addr_t RAM_size, long *initrd_size)
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180 | 636aa70a | Blue Swirl | { |
181 | 636aa70a | Blue Swirl | int linux_boot;
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182 | 636aa70a | Blue Swirl | unsigned int i; |
183 | 636aa70a | Blue Swirl | long kernel_size;
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184 | 6908d9ce | Blue Swirl | uint8_t *ptr; |
185 | 636aa70a | Blue Swirl | |
186 | 636aa70a | Blue Swirl | linux_boot = (kernel_filename != NULL);
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187 | 636aa70a | Blue Swirl | |
188 | 636aa70a | Blue Swirl | kernel_size = 0;
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189 | 636aa70a | Blue Swirl | if (linux_boot) {
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190 | ca20cf32 | Blue Swirl | int bswap_needed;
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191 | ca20cf32 | Blue Swirl | |
192 | ca20cf32 | Blue Swirl | #ifdef BSWAP_NEEDED
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193 | ca20cf32 | Blue Swirl | bswap_needed = 1;
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194 | ca20cf32 | Blue Swirl | #else
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195 | ca20cf32 | Blue Swirl | bswap_needed = 0;
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196 | ca20cf32 | Blue Swirl | #endif
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197 | 409dbce5 | Aurelien Jarno | kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, |
198 | 409dbce5 | Aurelien Jarno | NULL, NULL, 1, ELF_MACHINE, 0); |
199 | 636aa70a | Blue Swirl | if (kernel_size < 0) |
200 | 636aa70a | Blue Swirl | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
201 | ca20cf32 | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
202 | ca20cf32 | Blue Swirl | TARGET_PAGE_SIZE); |
203 | 636aa70a | Blue Swirl | if (kernel_size < 0) |
204 | 636aa70a | Blue Swirl | kernel_size = load_image_targphys(kernel_filename, |
205 | 636aa70a | Blue Swirl | KERNEL_LOAD_ADDR, |
206 | 636aa70a | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR); |
207 | 636aa70a | Blue Swirl | if (kernel_size < 0) { |
208 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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209 | 636aa70a | Blue Swirl | kernel_filename); |
210 | 636aa70a | Blue Swirl | exit(1);
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211 | 636aa70a | Blue Swirl | } |
212 | 636aa70a | Blue Swirl | |
213 | 636aa70a | Blue Swirl | /* load initrd */
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214 | 636aa70a | Blue Swirl | *initrd_size = 0;
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215 | 636aa70a | Blue Swirl | if (initrd_filename) {
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216 | 636aa70a | Blue Swirl | *initrd_size = load_image_targphys(initrd_filename, |
217 | 636aa70a | Blue Swirl | INITRD_LOAD_ADDR, |
218 | 636aa70a | Blue Swirl | RAM_size - INITRD_LOAD_ADDR); |
219 | 636aa70a | Blue Swirl | if (*initrd_size < 0) { |
220 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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221 | 636aa70a | Blue Swirl | initrd_filename); |
222 | 636aa70a | Blue Swirl | exit(1);
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223 | 636aa70a | Blue Swirl | } |
224 | 636aa70a | Blue Swirl | } |
225 | 636aa70a | Blue Swirl | if (*initrd_size > 0) { |
226 | 636aa70a | Blue Swirl | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
227 | 6908d9ce | Blue Swirl | ptr = rom_ptr(KERNEL_LOAD_ADDR + i); |
228 | 6908d9ce | Blue Swirl | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
229 | 6908d9ce | Blue Swirl | stl_p(ptr + 24, INITRD_LOAD_ADDR + KERNEL_LOAD_ADDR - 0x4000); |
230 | 6908d9ce | Blue Swirl | stl_p(ptr + 28, *initrd_size);
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231 | 636aa70a | Blue Swirl | break;
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232 | 636aa70a | Blue Swirl | } |
233 | 636aa70a | Blue Swirl | } |
234 | 636aa70a | Blue Swirl | } |
235 | 636aa70a | Blue Swirl | } |
236 | 636aa70a | Blue Swirl | return kernel_size;
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237 | 636aa70a | Blue Swirl | } |
238 | 3475187d | bellard | |
239 | b4950060 | blueswir1 | void pic_info(Monitor *mon)
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240 | 3475187d | bellard | { |
241 | 3475187d | bellard | } |
242 | 3475187d | bellard | |
243 | b4950060 | blueswir1 | void irq_info(Monitor *mon)
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244 | 3475187d | bellard | { |
245 | 3475187d | bellard | } |
246 | 3475187d | bellard | |
247 | 9d926598 | blueswir1 | void cpu_check_irqs(CPUState *env)
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248 | 9d926598 | blueswir1 | { |
249 | d532b26c | Igor V. Kovalenko | uint32_t pil = env->pil_in | |
250 | d532b26c | Igor V. Kovalenko | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); |
251 | d532b26c | Igor V. Kovalenko | |
252 | d532b26c | Igor V. Kovalenko | /* check if TM or SM in SOFTINT are set
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253 | d532b26c | Igor V. Kovalenko | setting these also causes interrupt 14 */
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254 | d532b26c | Igor V. Kovalenko | if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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255 | d532b26c | Igor V. Kovalenko | pil |= 1 << 14; |
256 | d532b26c | Igor V. Kovalenko | } |
257 | d532b26c | Igor V. Kovalenko | |
258 | d532b26c | Igor V. Kovalenko | if (!pil) {
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259 | d532b26c | Igor V. Kovalenko | if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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260 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
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261 | d532b26c | Igor V. Kovalenko | env->interrupt_index); |
262 | d532b26c | Igor V. Kovalenko | env->interrupt_index = 0;
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263 | d532b26c | Igor V. Kovalenko | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
264 | d532b26c | Igor V. Kovalenko | } |
265 | d532b26c | Igor V. Kovalenko | return;
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266 | d532b26c | Igor V. Kovalenko | } |
267 | d532b26c | Igor V. Kovalenko | |
268 | d532b26c | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
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269 | 9d926598 | blueswir1 | |
270 | 9d926598 | blueswir1 | unsigned int i; |
271 | 9d926598 | blueswir1 | |
272 | d532b26c | Igor V. Kovalenko | for (i = 15; i > env->psrpil; i--) { |
273 | 9d926598 | blueswir1 | if (pil & (1 << i)) { |
274 | 9d926598 | blueswir1 | int old_interrupt = env->interrupt_index;
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275 | d532b26c | Igor V. Kovalenko | int new_interrupt = TT_EXTINT | i;
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276 | d532b26c | Igor V. Kovalenko | |
277 | d532b26c | Igor V. Kovalenko | if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) { |
278 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
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279 | d532b26c | Igor V. Kovalenko | "current %x >= pending %x\n",
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280 | d532b26c | Igor V. Kovalenko | env->tl, cpu_tsptr(env)->tt, new_interrupt); |
281 | d532b26c | Igor V. Kovalenko | } else if (old_interrupt != new_interrupt) { |
282 | d532b26c | Igor V. Kovalenko | env->interrupt_index = new_interrupt; |
283 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
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284 | d532b26c | Igor V. Kovalenko | old_interrupt, new_interrupt); |
285 | 9d926598 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
286 | 9d926598 | blueswir1 | } |
287 | 9d926598 | blueswir1 | break;
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288 | 9d926598 | blueswir1 | } |
289 | 9d926598 | blueswir1 | } |
290 | d532b26c | Igor V. Kovalenko | } else {
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291 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
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292 | d532b26c | Igor V. Kovalenko | "current interrupt %x\n",
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293 | d532b26c | Igor V. Kovalenko | pil, env->pil_in, env->softint, env->interrupt_index); |
294 | 9d926598 | blueswir1 | } |
295 | 9d926598 | blueswir1 | } |
296 | 9d926598 | blueswir1 | |
297 | 8f4efc55 | Igor V. Kovalenko | static void cpu_kick_irq(CPUState *env) |
298 | 8f4efc55 | Igor V. Kovalenko | { |
299 | 8f4efc55 | Igor V. Kovalenko | env->halted = 0;
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300 | 8f4efc55 | Igor V. Kovalenko | cpu_check_irqs(env); |
301 | 94ad5b00 | Paolo Bonzini | qemu_cpu_kick(env); |
302 | 8f4efc55 | Igor V. Kovalenko | } |
303 | 8f4efc55 | Igor V. Kovalenko | |
304 | 9d926598 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
305 | 9d926598 | blueswir1 | { |
306 | 9d926598 | blueswir1 | CPUState *env = opaque; |
307 | 9d926598 | blueswir1 | |
308 | 9d926598 | blueswir1 | if (level) {
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309 | b430a225 | Blue Swirl | CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
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310 | 9d926598 | blueswir1 | env->pil_in |= 1 << irq;
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311 | 94ad5b00 | Paolo Bonzini | cpu_kick_irq(env); |
312 | 9d926598 | blueswir1 | } else {
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313 | b430a225 | Blue Swirl | CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
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314 | 9d926598 | blueswir1 | env->pil_in &= ~(1 << irq);
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315 | 9d926598 | blueswir1 | cpu_check_irqs(env); |
316 | 9d926598 | blueswir1 | } |
317 | 9d926598 | blueswir1 | } |
318 | 9d926598 | blueswir1 | |
319 | e87231d4 | blueswir1 | typedef struct ResetData { |
320 | e87231d4 | blueswir1 | CPUState *env; |
321 | 44a99354 | Blue Swirl | uint64_t prom_addr; |
322 | e87231d4 | blueswir1 | } ResetData; |
323 | e87231d4 | blueswir1 | |
324 | 8f4efc55 | Igor V. Kovalenko | void cpu_put_timer(QEMUFile *f, CPUTimer *s)
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325 | 8f4efc55 | Igor V. Kovalenko | { |
326 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be32s(f, &s->frequency); |
327 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be32s(f, &s->disabled); |
328 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be64s(f, &s->disabled_mask); |
329 | 8f4efc55 | Igor V. Kovalenko | qemu_put_sbe64s(f, &s->clock_offset); |
330 | 8f4efc55 | Igor V. Kovalenko | |
331 | 8f4efc55 | Igor V. Kovalenko | qemu_put_timer(f, s->qtimer); |
332 | 8f4efc55 | Igor V. Kovalenko | } |
333 | 8f4efc55 | Igor V. Kovalenko | |
334 | 8f4efc55 | Igor V. Kovalenko | void cpu_get_timer(QEMUFile *f, CPUTimer *s)
|
335 | 8f4efc55 | Igor V. Kovalenko | { |
336 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be32s(f, &s->frequency); |
337 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be32s(f, &s->disabled); |
338 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be64s(f, &s->disabled_mask); |
339 | 8f4efc55 | Igor V. Kovalenko | qemu_get_sbe64s(f, &s->clock_offset); |
340 | 8f4efc55 | Igor V. Kovalenko | |
341 | 8f4efc55 | Igor V. Kovalenko | qemu_get_timer(f, s->qtimer); |
342 | 8f4efc55 | Igor V. Kovalenko | } |
343 | 8f4efc55 | Igor V. Kovalenko | |
344 | 8f4efc55 | Igor V. Kovalenko | static CPUTimer* cpu_timer_create(const char* name, CPUState *env, |
345 | 8f4efc55 | Igor V. Kovalenko | QEMUBHFunc *cb, uint32_t frequency, |
346 | 8f4efc55 | Igor V. Kovalenko | uint64_t disabled_mask) |
347 | 8f4efc55 | Igor V. Kovalenko | { |
348 | 8f4efc55 | Igor V. Kovalenko | CPUTimer *timer = qemu_mallocz(sizeof (CPUTimer));
|
349 | 8f4efc55 | Igor V. Kovalenko | |
350 | 8f4efc55 | Igor V. Kovalenko | timer->name = name; |
351 | 8f4efc55 | Igor V. Kovalenko | timer->frequency = frequency; |
352 | 8f4efc55 | Igor V. Kovalenko | timer->disabled_mask = disabled_mask; |
353 | 8f4efc55 | Igor V. Kovalenko | |
354 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = 1;
|
355 | 74475455 | Paolo Bonzini | timer->clock_offset = qemu_get_clock_ns(vm_clock); |
356 | 8f4efc55 | Igor V. Kovalenko | |
357 | 74475455 | Paolo Bonzini | timer->qtimer = qemu_new_timer_ns(vm_clock, cb, env); |
358 | 8f4efc55 | Igor V. Kovalenko | |
359 | 8f4efc55 | Igor V. Kovalenko | return timer;
|
360 | 8f4efc55 | Igor V. Kovalenko | } |
361 | 8f4efc55 | Igor V. Kovalenko | |
362 | 8f4efc55 | Igor V. Kovalenko | static void cpu_timer_reset(CPUTimer *timer) |
363 | 8f4efc55 | Igor V. Kovalenko | { |
364 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = 1;
|
365 | 74475455 | Paolo Bonzini | timer->clock_offset = qemu_get_clock_ns(vm_clock); |
366 | 8f4efc55 | Igor V. Kovalenko | |
367 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
368 | 8f4efc55 | Igor V. Kovalenko | } |
369 | 8f4efc55 | Igor V. Kovalenko | |
370 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
371 | c68ea704 | bellard | { |
372 | e87231d4 | blueswir1 | ResetData *s = (ResetData *)opaque; |
373 | e87231d4 | blueswir1 | CPUState *env = s->env; |
374 | 44a99354 | Blue Swirl | static unsigned int nr_resets; |
375 | 20c9f095 | blueswir1 | |
376 | c68ea704 | bellard | cpu_reset(env); |
377 | 8f4efc55 | Igor V. Kovalenko | |
378 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->tick); |
379 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->stick); |
380 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->hstick); |
381 | 8f4efc55 | Igor V. Kovalenko | |
382 | e87231d4 | blueswir1 | env->gregs[1] = 0; // Memory start |
383 | e87231d4 | blueswir1 | env->gregs[2] = ram_size; // Memory size |
384 | e87231d4 | blueswir1 | env->gregs[3] = 0; // Machine description XXX |
385 | 44a99354 | Blue Swirl | if (nr_resets++ == 0) { |
386 | 44a99354 | Blue Swirl | /* Power on reset */
|
387 | 44a99354 | Blue Swirl | env->pc = s->prom_addr + 0x20ULL;
|
388 | 44a99354 | Blue Swirl | } else {
|
389 | 44a99354 | Blue Swirl | env->pc = s->prom_addr + 0x40ULL;
|
390 | 44a99354 | Blue Swirl | } |
391 | e87231d4 | blueswir1 | env->npc = env->pc + 4;
|
392 | 20c9f095 | blueswir1 | } |
393 | 20c9f095 | blueswir1 | |
394 | 22548760 | blueswir1 | static void tick_irq(void *opaque) |
395 | 20c9f095 | blueswir1 | { |
396 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
397 | 20c9f095 | blueswir1 | |
398 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->tick; |
399 | 8f4efc55 | Igor V. Kovalenko | |
400 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
401 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
|
402 | 8f4efc55 | Igor V. Kovalenko | return;
|
403 | 8f4efc55 | Igor V. Kovalenko | } else {
|
404 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("tick: fire\n");
|
405 | 8fa211e8 | blueswir1 | } |
406 | 8f4efc55 | Igor V. Kovalenko | |
407 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_TIMER; |
408 | 8f4efc55 | Igor V. Kovalenko | cpu_kick_irq(env); |
409 | 20c9f095 | blueswir1 | } |
410 | 20c9f095 | blueswir1 | |
411 | 22548760 | blueswir1 | static void stick_irq(void *opaque) |
412 | 20c9f095 | blueswir1 | { |
413 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
414 | 20c9f095 | blueswir1 | |
415 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->stick; |
416 | 8f4efc55 | Igor V. Kovalenko | |
417 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
418 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
|
419 | 8f4efc55 | Igor V. Kovalenko | return;
|
420 | 8f4efc55 | Igor V. Kovalenko | } else {
|
421 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("stick: fire\n");
|
422 | 8fa211e8 | blueswir1 | } |
423 | 8f4efc55 | Igor V. Kovalenko | |
424 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_STIMER; |
425 | 8f4efc55 | Igor V. Kovalenko | cpu_kick_irq(env); |
426 | 20c9f095 | blueswir1 | } |
427 | 20c9f095 | blueswir1 | |
428 | 22548760 | blueswir1 | static void hstick_irq(void *opaque) |
429 | 20c9f095 | blueswir1 | { |
430 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
431 | 20c9f095 | blueswir1 | |
432 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->hstick; |
433 | 8f4efc55 | Igor V. Kovalenko | |
434 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
435 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
|
436 | 8f4efc55 | Igor V. Kovalenko | return;
|
437 | 8f4efc55 | Igor V. Kovalenko | } else {
|
438 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("hstick: fire\n");
|
439 | 8fa211e8 | blueswir1 | } |
440 | 8f4efc55 | Igor V. Kovalenko | |
441 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_STIMER; |
442 | 8f4efc55 | Igor V. Kovalenko | cpu_kick_irq(env); |
443 | 8f4efc55 | Igor V. Kovalenko | } |
444 | 8f4efc55 | Igor V. Kovalenko | |
445 | 8f4efc55 | Igor V. Kovalenko | static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
|
446 | 8f4efc55 | Igor V. Kovalenko | { |
447 | 8f4efc55 | Igor V. Kovalenko | return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
|
448 | 8f4efc55 | Igor V. Kovalenko | } |
449 | 8f4efc55 | Igor V. Kovalenko | |
450 | 8f4efc55 | Igor V. Kovalenko | static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
|
451 | 8f4efc55 | Igor V. Kovalenko | { |
452 | 8f4efc55 | Igor V. Kovalenko | return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
|
453 | c68ea704 | bellard | } |
454 | c68ea704 | bellard | |
455 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
|
456 | f4b1a842 | blueswir1 | { |
457 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_count = count & ~timer->disabled_mask; |
458 | 8f4efc55 | Igor V. Kovalenko | uint64_t disabled_bit = count & timer->disabled_mask; |
459 | 8f4efc55 | Igor V. Kovalenko | |
460 | 74475455 | Paolo Bonzini | int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) - |
461 | 8f4efc55 | Igor V. Kovalenko | cpu_to_timer_ticks(real_count, timer->frequency); |
462 | 8f4efc55 | Igor V. Kovalenko | |
463 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
|
464 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_count, |
465 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", timer); |
466 | 8f4efc55 | Igor V. Kovalenko | |
467 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = disabled_bit ? 1 : 0; |
468 | 8f4efc55 | Igor V. Kovalenko | timer->clock_offset = vm_clock_offset; |
469 | f4b1a842 | blueswir1 | } |
470 | f4b1a842 | blueswir1 | |
471 | 8f4efc55 | Igor V. Kovalenko | uint64_t cpu_tick_get_count(CPUTimer *timer) |
472 | f4b1a842 | blueswir1 | { |
473 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_count = timer_to_cpu_ticks( |
474 | 74475455 | Paolo Bonzini | qemu_get_clock_ns(vm_clock) - timer->clock_offset, |
475 | 8f4efc55 | Igor V. Kovalenko | timer->frequency); |
476 | 8f4efc55 | Igor V. Kovalenko | |
477 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
|
478 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_count, |
479 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", timer); |
480 | 8f4efc55 | Igor V. Kovalenko | |
481 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled)
|
482 | 8f4efc55 | Igor V. Kovalenko | real_count |= timer->disabled_mask; |
483 | 8f4efc55 | Igor V. Kovalenko | |
484 | 8f4efc55 | Igor V. Kovalenko | return real_count;
|
485 | f4b1a842 | blueswir1 | } |
486 | f4b1a842 | blueswir1 | |
487 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
|
488 | f4b1a842 | blueswir1 | { |
489 | 74475455 | Paolo Bonzini | int64_t now = qemu_get_clock_ns(vm_clock); |
490 | 8f4efc55 | Igor V. Kovalenko | |
491 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_limit = limit & ~timer->disabled_mask; |
492 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; |
493 | 8f4efc55 | Igor V. Kovalenko | |
494 | 8f4efc55 | Igor V. Kovalenko | int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + |
495 | 8f4efc55 | Igor V. Kovalenko | timer->clock_offset; |
496 | 8f4efc55 | Igor V. Kovalenko | |
497 | 8f4efc55 | Igor V. Kovalenko | if (expires < now) {
|
498 | 8f4efc55 | Igor V. Kovalenko | expires = now + 1;
|
499 | 8f4efc55 | Igor V. Kovalenko | } |
500 | 8f4efc55 | Igor V. Kovalenko | |
501 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
|
502 | 8f4efc55 | Igor V. Kovalenko | "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
|
503 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_limit, |
504 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", |
505 | 8f4efc55 | Igor V. Kovalenko | timer, limit, |
506 | 8f4efc55 | Igor V. Kovalenko | timer_to_cpu_ticks(now - timer->clock_offset, |
507 | 8f4efc55 | Igor V. Kovalenko | timer->frequency), |
508 | 8f4efc55 | Igor V. Kovalenko | timer_to_cpu_ticks(expires - now, timer->frequency)); |
509 | 8f4efc55 | Igor V. Kovalenko | |
510 | 8f4efc55 | Igor V. Kovalenko | if (!real_limit) {
|
511 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
|
512 | 8f4efc55 | Igor V. Kovalenko | timer->name); |
513 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
514 | 8f4efc55 | Igor V. Kovalenko | } else if (timer->disabled) { |
515 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
516 | 8f4efc55 | Igor V. Kovalenko | } else {
|
517 | 8f4efc55 | Igor V. Kovalenko | qemu_mod_timer(timer->qtimer, expires); |
518 | 8f4efc55 | Igor V. Kovalenko | } |
519 | f4b1a842 | blueswir1 | } |
520 | f4b1a842 | blueswir1 | |
521 | c190ea07 | blueswir1 | static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
522 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
523 | c190ea07 | blueswir1 | { |
524 | b430a225 | Blue Swirl | EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n", |
525 | b430a225 | Blue Swirl | region_num, addr); |
526 | c190ea07 | blueswir1 | switch (region_num) {
|
527 | c190ea07 | blueswir1 | case 0: |
528 | 968d683c | Alexander Graf | isa_mmio_init(addr, 0x1000000);
|
529 | c190ea07 | blueswir1 | break;
|
530 | c190ea07 | blueswir1 | case 1: |
531 | 968d683c | Alexander Graf | isa_mmio_init(addr, 0x800000);
|
532 | c190ea07 | blueswir1 | break;
|
533 | c190ea07 | blueswir1 | } |
534 | c190ea07 | blueswir1 | } |
535 | c190ea07 | blueswir1 | |
536 | 1387fe4a | Blue Swirl | static void dummy_isa_irq_handler(void *opaque, int n, int level) |
537 | 1387fe4a | Blue Swirl | { |
538 | 1387fe4a | Blue Swirl | } |
539 | 1387fe4a | Blue Swirl | |
540 | c190ea07 | blueswir1 | /* EBUS (Eight bit bus) bridge */
|
541 | c190ea07 | blueswir1 | static void |
542 | c190ea07 | blueswir1 | pci_ebus_init(PCIBus *bus, int devfn)
|
543 | c190ea07 | blueswir1 | { |
544 | 1387fe4a | Blue Swirl | qemu_irq *isa_irq; |
545 | 1387fe4a | Blue Swirl | |
546 | 53e3c4f9 | Blue Swirl | pci_create_simple(bus, devfn, "ebus");
|
547 | 1387fe4a | Blue Swirl | isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16); |
548 | 1387fe4a | Blue Swirl | isa_bus_irqs(isa_irq); |
549 | 53e3c4f9 | Blue Swirl | } |
550 | c190ea07 | blueswir1 | |
551 | 81a322d4 | Gerd Hoffmann | static int |
552 | 53e3c4f9 | Blue Swirl | pci_ebus_init1(PCIDevice *s) |
553 | 53e3c4f9 | Blue Swirl | { |
554 | 0c5b8d83 | Blue Swirl | isa_bus_new(&s->qdev); |
555 | 0c5b8d83 | Blue Swirl | |
556 | deb54399 | aliguori | pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); |
557 | deb54399 | aliguori | pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS); |
558 | c190ea07 | blueswir1 | s->config[0x04] = 0x06; // command = bus master, pci mem |
559 | c190ea07 | blueswir1 | s->config[0x05] = 0x00; |
560 | c190ea07 | blueswir1 | s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
561 | c190ea07 | blueswir1 | s->config[0x07] = 0x03; // status = medium devsel |
562 | c190ea07 | blueswir1 | s->config[0x08] = 0x01; // revision |
563 | c190ea07 | blueswir1 | s->config[0x09] = 0x00; // programming i/f |
564 | 173a543b | blueswir1 | pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); |
565 | c190ea07 | blueswir1 | s->config[0x0D] = 0x0a; // latency_timer |
566 | c190ea07 | blueswir1 | |
567 | 0392a017 | Isaku Yamahata | pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY, |
568 | c190ea07 | blueswir1 | ebus_mmio_mapfunc); |
569 | 0392a017 | Isaku Yamahata | pci_register_bar(s, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_MEMORY, |
570 | c190ea07 | blueswir1 | ebus_mmio_mapfunc); |
571 | 81a322d4 | Gerd Hoffmann | return 0; |
572 | c190ea07 | blueswir1 | } |
573 | c190ea07 | blueswir1 | |
574 | 53e3c4f9 | Blue Swirl | static PCIDeviceInfo ebus_info = {
|
575 | 53e3c4f9 | Blue Swirl | .qdev.name = "ebus",
|
576 | 53e3c4f9 | Blue Swirl | .qdev.size = sizeof(PCIDevice),
|
577 | 53e3c4f9 | Blue Swirl | .init = pci_ebus_init1, |
578 | 53e3c4f9 | Blue Swirl | }; |
579 | 53e3c4f9 | Blue Swirl | |
580 | 53e3c4f9 | Blue Swirl | static void pci_ebus_register(void) |
581 | 53e3c4f9 | Blue Swirl | { |
582 | 53e3c4f9 | Blue Swirl | pci_qdev_register(&ebus_info); |
583 | 53e3c4f9 | Blue Swirl | } |
584 | 53e3c4f9 | Blue Swirl | |
585 | 53e3c4f9 | Blue Swirl | device_init(pci_ebus_register); |
586 | 53e3c4f9 | Blue Swirl | |
587 | 409dbce5 | Aurelien Jarno | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
588 | 409dbce5 | Aurelien Jarno | { |
589 | 409dbce5 | Aurelien Jarno | target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque; |
590 | 409dbce5 | Aurelien Jarno | return addr + *base_addr - PROM_VADDR;
|
591 | 409dbce5 | Aurelien Jarno | } |
592 | 409dbce5 | Aurelien Jarno | |
593 | 1baffa46 | Blue Swirl | /* Boot PROM (OpenBIOS) */
|
594 | c227f099 | Anthony Liguori | static void prom_init(target_phys_addr_t addr, const char *bios_name) |
595 | 1baffa46 | Blue Swirl | { |
596 | 1baffa46 | Blue Swirl | DeviceState *dev; |
597 | 1baffa46 | Blue Swirl | SysBusDevice *s; |
598 | 1baffa46 | Blue Swirl | char *filename;
|
599 | 1baffa46 | Blue Swirl | int ret;
|
600 | 1baffa46 | Blue Swirl | |
601 | 1baffa46 | Blue Swirl | dev = qdev_create(NULL, "openprom"); |
602 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
603 | 1baffa46 | Blue Swirl | s = sysbus_from_qdev(dev); |
604 | 1baffa46 | Blue Swirl | |
605 | 1baffa46 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
606 | 1baffa46 | Blue Swirl | |
607 | 1baffa46 | Blue Swirl | /* load boot prom */
|
608 | 1baffa46 | Blue Swirl | if (bios_name == NULL) { |
609 | 1baffa46 | Blue Swirl | bios_name = PROM_FILENAME; |
610 | 1baffa46 | Blue Swirl | } |
611 | 1baffa46 | Blue Swirl | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
612 | 1baffa46 | Blue Swirl | if (filename) {
|
613 | 409dbce5 | Aurelien Jarno | ret = load_elf(filename, translate_prom_address, &addr, |
614 | 409dbce5 | Aurelien Jarno | NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
615 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
616 | 1baffa46 | Blue Swirl | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
617 | 1baffa46 | Blue Swirl | } |
618 | 1baffa46 | Blue Swirl | qemu_free(filename); |
619 | 1baffa46 | Blue Swirl | } else {
|
620 | 1baffa46 | Blue Swirl | ret = -1;
|
621 | 1baffa46 | Blue Swirl | } |
622 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
623 | 1baffa46 | Blue Swirl | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
624 | 1baffa46 | Blue Swirl | exit(1);
|
625 | 1baffa46 | Blue Swirl | } |
626 | 1baffa46 | Blue Swirl | } |
627 | 1baffa46 | Blue Swirl | |
628 | 81a322d4 | Gerd Hoffmann | static int prom_init1(SysBusDevice *dev) |
629 | 1baffa46 | Blue Swirl | { |
630 | c227f099 | Anthony Liguori | ram_addr_t prom_offset; |
631 | 1baffa46 | Blue Swirl | |
632 | 1724f049 | Alex Williamson | prom_offset = qemu_ram_alloc(NULL, "sun4u.prom", PROM_SIZE_MAX); |
633 | 1baffa46 | Blue Swirl | sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); |
634 | 81a322d4 | Gerd Hoffmann | return 0; |
635 | 1baffa46 | Blue Swirl | } |
636 | 1baffa46 | Blue Swirl | |
637 | 1baffa46 | Blue Swirl | static SysBusDeviceInfo prom_info = {
|
638 | 1baffa46 | Blue Swirl | .init = prom_init1, |
639 | 1baffa46 | Blue Swirl | .qdev.name = "openprom",
|
640 | 1baffa46 | Blue Swirl | .qdev.size = sizeof(SysBusDevice),
|
641 | 1baffa46 | Blue Swirl | .qdev.props = (Property[]) { |
642 | 1baffa46 | Blue Swirl | {/* end of property list */}
|
643 | 1baffa46 | Blue Swirl | } |
644 | 1baffa46 | Blue Swirl | }; |
645 | 1baffa46 | Blue Swirl | |
646 | 1baffa46 | Blue Swirl | static void prom_register_devices(void) |
647 | 1baffa46 | Blue Swirl | { |
648 | 1baffa46 | Blue Swirl | sysbus_register_withprop(&prom_info); |
649 | 1baffa46 | Blue Swirl | } |
650 | 1baffa46 | Blue Swirl | |
651 | 1baffa46 | Blue Swirl | device_init(prom_register_devices); |
652 | 1baffa46 | Blue Swirl | |
653 | bda42033 | Blue Swirl | |
654 | bda42033 | Blue Swirl | typedef struct RamDevice |
655 | bda42033 | Blue Swirl | { |
656 | bda42033 | Blue Swirl | SysBusDevice busdev; |
657 | 04843626 | Blue Swirl | uint64_t size; |
658 | bda42033 | Blue Swirl | } RamDevice; |
659 | bda42033 | Blue Swirl | |
660 | bda42033 | Blue Swirl | /* System RAM */
|
661 | 81a322d4 | Gerd Hoffmann | static int ram_init1(SysBusDevice *dev) |
662 | bda42033 | Blue Swirl | { |
663 | c227f099 | Anthony Liguori | ram_addr_t RAM_size, ram_offset; |
664 | bda42033 | Blue Swirl | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
665 | bda42033 | Blue Swirl | |
666 | bda42033 | Blue Swirl | RAM_size = d->size; |
667 | bda42033 | Blue Swirl | |
668 | 1724f049 | Alex Williamson | ram_offset = qemu_ram_alloc(NULL, "sun4u.ram", RAM_size); |
669 | bda42033 | Blue Swirl | sysbus_init_mmio(dev, RAM_size, ram_offset); |
670 | 81a322d4 | Gerd Hoffmann | return 0; |
671 | bda42033 | Blue Swirl | } |
672 | bda42033 | Blue Swirl | |
673 | c227f099 | Anthony Liguori | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) |
674 | bda42033 | Blue Swirl | { |
675 | bda42033 | Blue Swirl | DeviceState *dev; |
676 | bda42033 | Blue Swirl | SysBusDevice *s; |
677 | bda42033 | Blue Swirl | RamDevice *d; |
678 | bda42033 | Blue Swirl | |
679 | bda42033 | Blue Swirl | /* allocate RAM */
|
680 | bda42033 | Blue Swirl | dev = qdev_create(NULL, "memory"); |
681 | bda42033 | Blue Swirl | s = sysbus_from_qdev(dev); |
682 | bda42033 | Blue Swirl | |
683 | bda42033 | Blue Swirl | d = FROM_SYSBUS(RamDevice, s); |
684 | bda42033 | Blue Swirl | d->size = RAM_size; |
685 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
686 | bda42033 | Blue Swirl | |
687 | bda42033 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
688 | bda42033 | Blue Swirl | } |
689 | bda42033 | Blue Swirl | |
690 | bda42033 | Blue Swirl | static SysBusDeviceInfo ram_info = {
|
691 | bda42033 | Blue Swirl | .init = ram_init1, |
692 | bda42033 | Blue Swirl | .qdev.name = "memory",
|
693 | bda42033 | Blue Swirl | .qdev.size = sizeof(RamDevice),
|
694 | bda42033 | Blue Swirl | .qdev.props = (Property[]) { |
695 | 32a7ee98 | Gerd Hoffmann | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
696 | 32a7ee98 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
697 | bda42033 | Blue Swirl | } |
698 | bda42033 | Blue Swirl | }; |
699 | bda42033 | Blue Swirl | |
700 | bda42033 | Blue Swirl | static void ram_register_devices(void) |
701 | bda42033 | Blue Swirl | { |
702 | bda42033 | Blue Swirl | sysbus_register_withprop(&ram_info); |
703 | bda42033 | Blue Swirl | } |
704 | bda42033 | Blue Swirl | |
705 | bda42033 | Blue Swirl | device_init(ram_register_devices); |
706 | bda42033 | Blue Swirl | |
707 | 7b833f5b | Blue Swirl | static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
708 | 3475187d | bellard | { |
709 | c68ea704 | bellard | CPUState *env; |
710 | e87231d4 | blueswir1 | ResetData *reset_info; |
711 | 3475187d | bellard | |
712 | 8f4efc55 | Igor V. Kovalenko | uint32_t tick_frequency = 100*1000000; |
713 | 8f4efc55 | Igor V. Kovalenko | uint32_t stick_frequency = 100*1000000; |
714 | 8f4efc55 | Igor V. Kovalenko | uint32_t hstick_frequency = 100*1000000; |
715 | 8f4efc55 | Igor V. Kovalenko | |
716 | c7ba218d | blueswir1 | if (!cpu_model)
|
717 | c7ba218d | blueswir1 | cpu_model = hwdef->default_cpu_model; |
718 | aaed909a | bellard | env = cpu_init(cpu_model); |
719 | aaed909a | bellard | if (!env) {
|
720 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
721 | 62724a37 | blueswir1 | exit(1);
|
722 | 62724a37 | blueswir1 | } |
723 | 20c9f095 | blueswir1 | |
724 | 8f4efc55 | Igor V. Kovalenko | env->tick = cpu_timer_create("tick", env, tick_irq,
|
725 | 8f4efc55 | Igor V. Kovalenko | tick_frequency, TICK_NPT_MASK); |
726 | 8f4efc55 | Igor V. Kovalenko | |
727 | 8f4efc55 | Igor V. Kovalenko | env->stick = cpu_timer_create("stick", env, stick_irq,
|
728 | 8f4efc55 | Igor V. Kovalenko | stick_frequency, TICK_INT_DIS); |
729 | 20c9f095 | blueswir1 | |
730 | 8f4efc55 | Igor V. Kovalenko | env->hstick = cpu_timer_create("hstick", env, hstick_irq,
|
731 | 8f4efc55 | Igor V. Kovalenko | hstick_frequency, TICK_INT_DIS); |
732 | e87231d4 | blueswir1 | |
733 | e87231d4 | blueswir1 | reset_info = qemu_mallocz(sizeof(ResetData));
|
734 | e87231d4 | blueswir1 | reset_info->env = env; |
735 | 44a99354 | Blue Swirl | reset_info->prom_addr = hwdef->prom_addr; |
736 | a08d4367 | Jan Kiszka | qemu_register_reset(main_cpu_reset, reset_info); |
737 | c68ea704 | bellard | |
738 | 7b833f5b | Blue Swirl | return env;
|
739 | 7b833f5b | Blue Swirl | } |
740 | 7b833f5b | Blue Swirl | |
741 | c227f099 | Anthony Liguori | static void sun4uv_init(ram_addr_t RAM_size, |
742 | 7b833f5b | Blue Swirl | const char *boot_devices, |
743 | 7b833f5b | Blue Swirl | const char *kernel_filename, const char *kernel_cmdline, |
744 | 7b833f5b | Blue Swirl | const char *initrd_filename, const char *cpu_model, |
745 | 7b833f5b | Blue Swirl | const struct hwdef *hwdef) |
746 | 7b833f5b | Blue Swirl | { |
747 | 7b833f5b | Blue Swirl | CPUState *env; |
748 | 43a34704 | Blue Swirl | M48t59State *nvram; |
749 | 7b833f5b | Blue Swirl | unsigned int i; |
750 | 7b833f5b | Blue Swirl | long initrd_size, kernel_size;
|
751 | 7b833f5b | Blue Swirl | PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
752 | 7b833f5b | Blue Swirl | qemu_irq *irq; |
753 | f455e98c | Gerd Hoffmann | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
754 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
755 | 7b833f5b | Blue Swirl | void *fw_cfg;
|
756 | 7b833f5b | Blue Swirl | |
757 | 7b833f5b | Blue Swirl | /* init CPUs */
|
758 | 7b833f5b | Blue Swirl | env = cpu_devinit(cpu_model, hwdef); |
759 | 7b833f5b | Blue Swirl | |
760 | bda42033 | Blue Swirl | /* set up devices */
|
761 | bda42033 | Blue Swirl | ram_init(0, RAM_size);
|
762 | 3475187d | bellard | |
763 | 1baffa46 | Blue Swirl | prom_init(hwdef->prom_addr, bios_name); |
764 | 3475187d | bellard | |
765 | 7d55273f | Igor Kovalenko | |
766 | 7d55273f | Igor Kovalenko | irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
767 | 7d55273f | Igor Kovalenko | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2, |
768 | c190ea07 | blueswir1 | &pci_bus3); |
769 | d63baf92 | Igor V. Kovalenko | isa_mem_base = APB_PCI_IO_BASE; |
770 | 78895427 | Gerd Hoffmann | pci_vga_init(pci_bus); |
771 | 83469015 | bellard | |
772 | c190ea07 | blueswir1 | // XXX Should be pci_bus3
|
773 | c190ea07 | blueswir1 | pci_ebus_init(pci_bus, -1);
|
774 | c190ea07 | blueswir1 | |
775 | e87231d4 | blueswir1 | i = 0;
|
776 | e87231d4 | blueswir1 | if (hwdef->console_serial_base) {
|
777 | e87231d4 | blueswir1 | serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, |
778 | 2d48377a | Blue Swirl | serial_hds[i], 1, 1); |
779 | e87231d4 | blueswir1 | i++; |
780 | e87231d4 | blueswir1 | } |
781 | e87231d4 | blueswir1 | for(; i < MAX_SERIAL_PORTS; i++) {
|
782 | 83469015 | bellard | if (serial_hds[i]) {
|
783 | ac0be998 | Gerd Hoffmann | serial_isa_init(i, serial_hds[i]); |
784 | 83469015 | bellard | } |
785 | 83469015 | bellard | } |
786 | 83469015 | bellard | |
787 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
788 | 83469015 | bellard | if (parallel_hds[i]) {
|
789 | 021f0674 | Gerd Hoffmann | parallel_init(i, parallel_hds[i]); |
790 | 83469015 | bellard | } |
791 | 83469015 | bellard | } |
792 | 83469015 | bellard | |
793 | cb457d76 | aliguori | for(i = 0; i < nb_nics; i++) |
794 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
795 | 83469015 | bellard | |
796 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
797 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
798 | e4bcb14c | ths | exit(1);
|
799 | e4bcb14c | ths | } |
800 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
801 | f455e98c | Gerd Hoffmann | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, |
802 | 751c6a17 | Gerd Hoffmann | i % MAX_IDE_DEVS); |
803 | e4bcb14c | ths | } |
804 | e4bcb14c | ths | |
805 | 3b898dda | blueswir1 | pci_cmd646_ide_init(pci_bus, hd, 1);
|
806 | 3b898dda | blueswir1 | |
807 | 2e15e23b | Gerd Hoffmann | isa_create_simple("i8042");
|
808 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
809 | fd8014e1 | Gerd Hoffmann | fd[i] = drive_get(IF_FLOPPY, 0, i);
|
810 | e4bcb14c | ths | } |
811 | 86c86157 | Gerd Hoffmann | fdctrl_init_isa(fd); |
812 | f80237d4 | Blue Swirl | nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59); |
813 | 636aa70a | Blue Swirl | |
814 | 636aa70a | Blue Swirl | initrd_size = 0;
|
815 | 636aa70a | Blue Swirl | kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, |
816 | 636aa70a | Blue Swirl | ram_size, &initrd_size); |
817 | 636aa70a | Blue Swirl | |
818 | 22548760 | blueswir1 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
819 | 0d31cb99 | blueswir1 | KERNEL_LOAD_ADDR, kernel_size, |
820 | 0d31cb99 | blueswir1 | kernel_cmdline, |
821 | 0d31cb99 | blueswir1 | INITRD_LOAD_ADDR, initrd_size, |
822 | 0d31cb99 | blueswir1 | /* XXX: need an option to load a NVRAM image */
|
823 | 0d31cb99 | blueswir1 | 0,
|
824 | 0d31cb99 | blueswir1 | graphic_width, graphic_height, graphic_depth, |
825 | 0d31cb99 | blueswir1 | (uint8_t *)&nd_table[0].macaddr);
|
826 | 83469015 | bellard | |
827 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
828 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
829 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
830 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
831 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
832 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
833 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
834 | 9c9b0512 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
835 | 9c9b0512 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
836 | 6bb4ca57 | Blue Swirl | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
837 | 6bb4ca57 | Blue Swirl | (uint8_t*)strdup(kernel_cmdline), |
838 | 6bb4ca57 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
839 | 513f789f | blueswir1 | } else {
|
840 | 9c9b0512 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
841 | 513f789f | blueswir1 | } |
842 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
843 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
844 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
|
845 | 7589690c | Blue Swirl | |
846 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); |
847 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); |
848 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); |
849 | 7589690c | Blue Swirl | |
850 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
851 | 3475187d | bellard | } |
852 | 3475187d | bellard | |
853 | 905fdcb5 | blueswir1 | enum {
|
854 | 905fdcb5 | blueswir1 | sun4u_id = 0,
|
855 | 905fdcb5 | blueswir1 | sun4v_id = 64,
|
856 | e87231d4 | blueswir1 | niagara_id, |
857 | 905fdcb5 | blueswir1 | }; |
858 | 905fdcb5 | blueswir1 | |
859 | c7ba218d | blueswir1 | static const struct hwdef hwdefs[] = { |
860 | c7ba218d | blueswir1 | /* Sun4u generic PC-like machine */
|
861 | c7ba218d | blueswir1 | { |
862 | 5910b047 | Igor V. Kovalenko | .default_cpu_model = "TI UltraSparc IIi",
|
863 | 905fdcb5 | blueswir1 | .machine_id = sun4u_id, |
864 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
865 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
866 | c7ba218d | blueswir1 | }, |
867 | c7ba218d | blueswir1 | /* Sun4v generic PC-like machine */
|
868 | c7ba218d | blueswir1 | { |
869 | c7ba218d | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
870 | 905fdcb5 | blueswir1 | .machine_id = sun4v_id, |
871 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
872 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
873 | e87231d4 | blueswir1 | }, |
874 | e87231d4 | blueswir1 | /* Sun4v generic Niagara machine */
|
875 | e87231d4 | blueswir1 | { |
876 | e87231d4 | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
877 | e87231d4 | blueswir1 | .machine_id = niagara_id, |
878 | e87231d4 | blueswir1 | .prom_addr = 0xfff0000000ULL,
|
879 | e87231d4 | blueswir1 | .console_serial_base = 0xfff0c2c000ULL,
|
880 | c7ba218d | blueswir1 | }, |
881 | c7ba218d | blueswir1 | }; |
882 | c7ba218d | blueswir1 | |
883 | c7ba218d | blueswir1 | /* Sun4u hardware initialisation */
|
884 | c227f099 | Anthony Liguori | static void sun4u_init(ram_addr_t RAM_size, |
885 | 3023f332 | aliguori | const char *boot_devices, |
886 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
887 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
888 | c7ba218d | blueswir1 | { |
889 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
890 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
891 | c7ba218d | blueswir1 | } |
892 | c7ba218d | blueswir1 | |
893 | c7ba218d | blueswir1 | /* Sun4v hardware initialisation */
|
894 | c227f099 | Anthony Liguori | static void sun4v_init(ram_addr_t RAM_size, |
895 | 3023f332 | aliguori | const char *boot_devices, |
896 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
897 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
898 | c7ba218d | blueswir1 | { |
899 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
900 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
901 | c7ba218d | blueswir1 | } |
902 | c7ba218d | blueswir1 | |
903 | e87231d4 | blueswir1 | /* Niagara hardware initialisation */
|
904 | c227f099 | Anthony Liguori | static void niagara_init(ram_addr_t RAM_size, |
905 | 3023f332 | aliguori | const char *boot_devices, |
906 | e87231d4 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
907 | e87231d4 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
908 | e87231d4 | blueswir1 | { |
909 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
910 | e87231d4 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
911 | e87231d4 | blueswir1 | } |
912 | e87231d4 | blueswir1 | |
913 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4u_machine = {
|
914 | 66de733b | blueswir1 | .name = "sun4u",
|
915 | 66de733b | blueswir1 | .desc = "Sun4u platform",
|
916 | 66de733b | blueswir1 | .init = sun4u_init, |
917 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
918 | 0c257437 | Anthony Liguori | .is_default = 1,
|
919 | 3475187d | bellard | }; |
920 | c7ba218d | blueswir1 | |
921 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4v_machine = {
|
922 | 66de733b | blueswir1 | .name = "sun4v",
|
923 | 66de733b | blueswir1 | .desc = "Sun4v platform",
|
924 | 66de733b | blueswir1 | .init = sun4v_init, |
925 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
926 | c7ba218d | blueswir1 | }; |
927 | e87231d4 | blueswir1 | |
928 | f80f9ec9 | Anthony Liguori | static QEMUMachine niagara_machine = {
|
929 | e87231d4 | blueswir1 | .name = "Niagara",
|
930 | e87231d4 | blueswir1 | .desc = "Sun4v platform, Niagara",
|
931 | e87231d4 | blueswir1 | .init = niagara_init, |
932 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
933 | e87231d4 | blueswir1 | }; |
934 | f80f9ec9 | Anthony Liguori | |
935 | f80f9ec9 | Anthony Liguori | static void sun4u_machine_init(void) |
936 | f80f9ec9 | Anthony Liguori | { |
937 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4u_machine); |
938 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4v_machine); |
939 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&niagara_machine); |
940 | f80f9ec9 | Anthony Liguori | } |
941 | f80f9ec9 | Anthony Liguori | |
942 | f80f9ec9 | Anthony Liguori | machine_init(sun4u_machine_init); |