root / hw / ppc_oldworld.c @ 475dc65f
History | View | Annotate | Download (12.7 kB)
1 | 3cbee15b | j_mayer | /*
|
---|---|---|---|
2 | 3cbee15b | j_mayer | * QEMU OldWorld PowerMac (currently ~G3 B&W) hardware System Emulator
|
3 | 3cbee15b | j_mayer | *
|
4 | 3cbee15b | j_mayer | * Copyright (c) 2004-2007 Fabrice Bellard
|
5 | 3cbee15b | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
|
6 | 3cbee15b | j_mayer | *
|
7 | 3cbee15b | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
8 | 3cbee15b | j_mayer | * of this software and associated documentation files (the "Software"), to deal
|
9 | 3cbee15b | j_mayer | * in the Software without restriction, including without limitation the rights
|
10 | 3cbee15b | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
11 | 3cbee15b | j_mayer | * copies of the Software, and to permit persons to whom the Software is
|
12 | 3cbee15b | j_mayer | * furnished to do so, subject to the following conditions:
|
13 | 3cbee15b | j_mayer | *
|
14 | 3cbee15b | j_mayer | * The above copyright notice and this permission notice shall be included in
|
15 | 3cbee15b | j_mayer | * all copies or substantial portions of the Software.
|
16 | 3cbee15b | j_mayer | *
|
17 | 3cbee15b | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
18 | 3cbee15b | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
19 | 3cbee15b | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
20 | 3cbee15b | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
21 | 3cbee15b | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
22 | 3cbee15b | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
23 | 3cbee15b | j_mayer | * THE SOFTWARE.
|
24 | 3cbee15b | j_mayer | */
|
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "ppc.h" |
27 | 3cbee15b | j_mayer | #include "ppc_mac.h" |
28 | 87ecb68b | pbrook | #include "nvram.h" |
29 | 87ecb68b | pbrook | #include "pc.h" |
30 | 87ecb68b | pbrook | #include "sysemu.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "isa.h" |
33 | 87ecb68b | pbrook | #include "pci.h" |
34 | 87ecb68b | pbrook | #include "boards.h" |
35 | 3cbee15b | j_mayer | |
36 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
37 | e4bcb14c | ths | |
38 | 3cbee15b | j_mayer | /* temporary frame buffer OSI calls for the video.x driver. The right
|
39 | 3cbee15b | j_mayer | solution is to modify the driver to use VGA PCI I/Os */
|
40 | 3cbee15b | j_mayer | /* XXX: to be removed. This is no way related to emulation */
|
41 | 3cbee15b | j_mayer | static int vga_osi_call (CPUState *env) |
42 | 3cbee15b | j_mayer | { |
43 | 3cbee15b | j_mayer | static int vga_vbl_enabled; |
44 | 3cbee15b | j_mayer | int linesize;
|
45 | 3cbee15b | j_mayer | |
46 | aae9366a | j_mayer | // printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
|
47 | 3cbee15b | j_mayer | |
48 | 3cbee15b | j_mayer | /* same handler as PearPC, coming from the original MOL video
|
49 | 3cbee15b | j_mayer | driver. */
|
50 | 3cbee15b | j_mayer | switch(env->gpr[5]) { |
51 | 3cbee15b | j_mayer | case 4: |
52 | 3cbee15b | j_mayer | break;
|
53 | 3cbee15b | j_mayer | case 28: /* set_vmode */ |
54 | 3cbee15b | j_mayer | if (env->gpr[6] != 1 || env->gpr[7] != 0) |
55 | 3cbee15b | j_mayer | env->gpr[3] = 1; |
56 | 3cbee15b | j_mayer | else
|
57 | 3cbee15b | j_mayer | env->gpr[3] = 0; |
58 | 3cbee15b | j_mayer | break;
|
59 | 3cbee15b | j_mayer | case 29: /* get_vmode_info */ |
60 | 3cbee15b | j_mayer | if (env->gpr[6] != 0) { |
61 | 3cbee15b | j_mayer | if (env->gpr[6] != 1 || env->gpr[7] != 0) { |
62 | 3cbee15b | j_mayer | env->gpr[3] = 1; |
63 | 3cbee15b | j_mayer | break;
|
64 | 3cbee15b | j_mayer | } |
65 | 3cbee15b | j_mayer | } |
66 | 3cbee15b | j_mayer | env->gpr[3] = 0; |
67 | 3cbee15b | j_mayer | env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */ |
68 | 3cbee15b | j_mayer | env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */ |
69 | 3cbee15b | j_mayer | env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */ |
70 | 3cbee15b | j_mayer | env->gpr[7] = 85 << 16; /* refresh rate */ |
71 | 3cbee15b | j_mayer | env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */ |
72 | 3cbee15b | j_mayer | linesize = ((graphic_depth + 7) >> 3) * graphic_width; |
73 | 3cbee15b | j_mayer | linesize = (linesize + 3) & ~3; |
74 | 3cbee15b | j_mayer | env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */ |
75 | 3cbee15b | j_mayer | break;
|
76 | 3cbee15b | j_mayer | case 31: /* set_video power */ |
77 | 3cbee15b | j_mayer | env->gpr[3] = 0; |
78 | 3cbee15b | j_mayer | break;
|
79 | 3cbee15b | j_mayer | case 39: /* video_ctrl */ |
80 | 3cbee15b | j_mayer | if (env->gpr[6] == 0 || env->gpr[6] == 1) |
81 | 3cbee15b | j_mayer | vga_vbl_enabled = env->gpr[6];
|
82 | 3cbee15b | j_mayer | env->gpr[3] = 0; |
83 | 3cbee15b | j_mayer | break;
|
84 | 3cbee15b | j_mayer | case 47: |
85 | 3cbee15b | j_mayer | break;
|
86 | 3cbee15b | j_mayer | case 59: /* set_color */ |
87 | 3cbee15b | j_mayer | /* R6 = index, R7 = RGB */
|
88 | 3cbee15b | j_mayer | env->gpr[3] = 0; |
89 | 3cbee15b | j_mayer | break;
|
90 | 3cbee15b | j_mayer | case 64: /* get color */ |
91 | 3cbee15b | j_mayer | /* R6 = index */
|
92 | 3cbee15b | j_mayer | env->gpr[3] = 0; |
93 | 3cbee15b | j_mayer | break;
|
94 | 3cbee15b | j_mayer | case 116: /* set hwcursor */ |
95 | 3cbee15b | j_mayer | /* R6 = x, R7 = y, R8 = visible, R9 = data */
|
96 | 3cbee15b | j_mayer | break;
|
97 | 3cbee15b | j_mayer | default:
|
98 | aae9366a | j_mayer | fprintf(stderr, "unsupported OSI call R5=" REGX "\n", |
99 | aae9366a | j_mayer | ppc_dump_gpr(env, 5));
|
100 | 3cbee15b | j_mayer | break;
|
101 | 3cbee15b | j_mayer | } |
102 | 3cbee15b | j_mayer | |
103 | 3cbee15b | j_mayer | return 1; /* osi_call handled */ |
104 | 3cbee15b | j_mayer | } |
105 | 3cbee15b | j_mayer | |
106 | 00f82b8a | aurel32 | static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size, |
107 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
108 | 3cbee15b | j_mayer | const char *kernel_filename, |
109 | 3cbee15b | j_mayer | const char *kernel_cmdline, |
110 | 3cbee15b | j_mayer | const char *initrd_filename, |
111 | 3cbee15b | j_mayer | const char *cpu_model) |
112 | 3cbee15b | j_mayer | { |
113 | aaed909a | bellard | CPUState *env = NULL, *envs[MAX_CPUS];
|
114 | 3cbee15b | j_mayer | char buf[1024]; |
115 | 3cbee15b | j_mayer | qemu_irq *pic, **heathrow_irqs; |
116 | 3cbee15b | j_mayer | nvram_t nvram; |
117 | 3cbee15b | j_mayer | m48t59_t *m48t59; |
118 | 3cbee15b | j_mayer | int linux_boot, i;
|
119 | 3cbee15b | j_mayer | unsigned long bios_offset, vga_bios_offset; |
120 | 3cbee15b | j_mayer | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
121 | 3cbee15b | j_mayer | PCIBus *pci_bus; |
122 | 3cbee15b | j_mayer | MacIONVRAMState *nvr; |
123 | 3cbee15b | j_mayer | int vga_bios_size, bios_size;
|
124 | 3cbee15b | j_mayer | qemu_irq *dummy_irq; |
125 | 3cbee15b | j_mayer | int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
|
126 | 0d913fdb | j_mayer | int ide_mem_index[2]; |
127 | 28c5af54 | j_mayer | int ppc_boot_device;
|
128 | e4bcb14c | ths | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
129 | e4bcb14c | ths | int index;
|
130 | 3cbee15b | j_mayer | |
131 | 3cbee15b | j_mayer | linux_boot = (kernel_filename != NULL);
|
132 | 3cbee15b | j_mayer | |
133 | 3cbee15b | j_mayer | /* init CPUs */
|
134 | 3cbee15b | j_mayer | if (cpu_model == NULL) |
135 | 3cbee15b | j_mayer | cpu_model = "default";
|
136 | 3cbee15b | j_mayer | for (i = 0; i < smp_cpus; i++) { |
137 | aaed909a | bellard | env = cpu_init(cpu_model); |
138 | aaed909a | bellard | if (!env) {
|
139 | aaed909a | bellard | fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
140 | aaed909a | bellard | exit(1);
|
141 | aaed909a | bellard | } |
142 | 3cbee15b | j_mayer | /* Set time-base frequency to 100 Mhz */
|
143 | 3cbee15b | j_mayer | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
144 | 3cbee15b | j_mayer | env->osi_call = vga_osi_call; |
145 | 3cbee15b | j_mayer | qemu_register_reset(&cpu_ppc_reset, env); |
146 | 3cbee15b | j_mayer | envs[i] = env; |
147 | 3cbee15b | j_mayer | } |
148 | 4c823cff | j_mayer | if (env->nip < 0xFFF80000) { |
149 | 4c823cff | j_mayer | /* Special test for PowerPC 601:
|
150 | 4c823cff | j_mayer | * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
|
151 | 4c823cff | j_mayer | * But the NVRAM is located at 0xFFF04000...
|
152 | 4c823cff | j_mayer | */
|
153 | 4c823cff | j_mayer | cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
|
154 | 4c823cff | j_mayer | } |
155 | 3cbee15b | j_mayer | |
156 | 3cbee15b | j_mayer | /* allocate RAM */
|
157 | 3cbee15b | j_mayer | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
158 | 3cbee15b | j_mayer | |
159 | 3cbee15b | j_mayer | /* allocate and load BIOS */
|
160 | 3cbee15b | j_mayer | bios_offset = ram_size + vga_ram_size; |
161 | 3cbee15b | j_mayer | if (bios_name == NULL) |
162 | 3cbee15b | j_mayer | bios_name = BIOS_FILENAME; |
163 | 3cbee15b | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
164 | 3cbee15b | j_mayer | bios_size = load_image(buf, phys_ram_base + bios_offset); |
165 | 3cbee15b | j_mayer | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
166 | 3cbee15b | j_mayer | cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
|
167 | 3cbee15b | j_mayer | exit(1);
|
168 | 3cbee15b | j_mayer | } |
169 | 3cbee15b | j_mayer | bios_size = (bios_size + 0xfff) & ~0xfff; |
170 | 4c823cff | j_mayer | if (bios_size > 0x00080000) { |
171 | 4c823cff | j_mayer | /* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
|
172 | 4c823cff | j_mayer | cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
|
173 | 4c823cff | j_mayer | } |
174 | 3cbee15b | j_mayer | cpu_register_physical_memory((uint32_t)(-bios_size), |
175 | 3cbee15b | j_mayer | bios_size, bios_offset | IO_MEM_ROM); |
176 | 3cbee15b | j_mayer | |
177 | 3cbee15b | j_mayer | /* allocate and load VGA BIOS */
|
178 | 3cbee15b | j_mayer | vga_bios_offset = bios_offset + bios_size; |
179 | 3cbee15b | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
180 | 3cbee15b | j_mayer | vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
|
181 | 3cbee15b | j_mayer | if (vga_bios_size < 0) { |
182 | 3cbee15b | j_mayer | /* if no bios is present, we can still work */
|
183 | 3cbee15b | j_mayer | fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
|
184 | 3cbee15b | j_mayer | vga_bios_size = 0;
|
185 | 3cbee15b | j_mayer | } else {
|
186 | 3cbee15b | j_mayer | /* set a specific header (XXX: find real Apple format for NDRV
|
187 | 3cbee15b | j_mayer | drivers) */
|
188 | 3cbee15b | j_mayer | phys_ram_base[vga_bios_offset] = 'N';
|
189 | 3cbee15b | j_mayer | phys_ram_base[vga_bios_offset + 1] = 'D'; |
190 | 3cbee15b | j_mayer | phys_ram_base[vga_bios_offset + 2] = 'R'; |
191 | 3cbee15b | j_mayer | phys_ram_base[vga_bios_offset + 3] = 'V'; |
192 | 3cbee15b | j_mayer | cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
|
193 | 3cbee15b | j_mayer | vga_bios_size); |
194 | 3cbee15b | j_mayer | vga_bios_size += 8;
|
195 | 3cbee15b | j_mayer | } |
196 | 3cbee15b | j_mayer | vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff; |
197 | 3cbee15b | j_mayer | |
198 | 3cbee15b | j_mayer | if (linux_boot) {
|
199 | 3cbee15b | j_mayer | kernel_base = KERNEL_LOAD_ADDR; |
200 | 3cbee15b | j_mayer | /* now we can load the kernel */
|
201 | 3cbee15b | j_mayer | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
202 | 3cbee15b | j_mayer | if (kernel_size < 0) { |
203 | 3cbee15b | j_mayer | cpu_abort(env, "qemu: could not load kernel '%s'\n",
|
204 | 3cbee15b | j_mayer | kernel_filename); |
205 | 3cbee15b | j_mayer | exit(1);
|
206 | 3cbee15b | j_mayer | } |
207 | 3cbee15b | j_mayer | /* load initrd */
|
208 | 3cbee15b | j_mayer | if (initrd_filename) {
|
209 | 3cbee15b | j_mayer | initrd_base = INITRD_LOAD_ADDR; |
210 | 3cbee15b | j_mayer | initrd_size = load_image(initrd_filename, |
211 | 3cbee15b | j_mayer | phys_ram_base + initrd_base); |
212 | 3cbee15b | j_mayer | if (initrd_size < 0) { |
213 | 3cbee15b | j_mayer | cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
|
214 | 3cbee15b | j_mayer | initrd_filename); |
215 | 3cbee15b | j_mayer | exit(1);
|
216 | 3cbee15b | j_mayer | } |
217 | 3cbee15b | j_mayer | } else {
|
218 | 3cbee15b | j_mayer | initrd_base = 0;
|
219 | 3cbee15b | j_mayer | initrd_size = 0;
|
220 | 3cbee15b | j_mayer | } |
221 | 6ac0e82d | balrog | ppc_boot_device = 'm';
|
222 | 3cbee15b | j_mayer | } else {
|
223 | 3cbee15b | j_mayer | kernel_base = 0;
|
224 | 3cbee15b | j_mayer | kernel_size = 0;
|
225 | 3cbee15b | j_mayer | initrd_base = 0;
|
226 | 3cbee15b | j_mayer | initrd_size = 0;
|
227 | 28c5af54 | j_mayer | ppc_boot_device = '\0';
|
228 | 0d913fdb | j_mayer | for (i = 0; boot_device[i] != '\0'; i++) { |
229 | 28c5af54 | j_mayer | /* TOFIX: for now, the second IDE channel is not properly
|
230 | 0d913fdb | j_mayer | * used by OHW. The Mac floppy disk are not emulated.
|
231 | 28c5af54 | j_mayer | * For now, OHW cannot boot from the network.
|
232 | 28c5af54 | j_mayer | */
|
233 | 28c5af54 | j_mayer | #if 0
|
234 | 0d913fdb | j_mayer | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
|
235 | 0d913fdb | j_mayer | ppc_boot_device = boot_device[i];
|
236 | 28c5af54 | j_mayer | break;
|
237 | 0d913fdb | j_mayer | }
|
238 | 28c5af54 | j_mayer | #else
|
239 | 0d913fdb | j_mayer | if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { |
240 | 0d913fdb | j_mayer | ppc_boot_device = boot_device[i]; |
241 | 28c5af54 | j_mayer | break;
|
242 | 0d913fdb | j_mayer | } |
243 | 28c5af54 | j_mayer | #endif
|
244 | 28c5af54 | j_mayer | } |
245 | 28c5af54 | j_mayer | if (ppc_boot_device == '\0') { |
246 | 28c5af54 | j_mayer | fprintf(stderr, "No valid boot device for Mac99 machine\n");
|
247 | 28c5af54 | j_mayer | exit(1);
|
248 | 28c5af54 | j_mayer | } |
249 | 3cbee15b | j_mayer | } |
250 | 3cbee15b | j_mayer | |
251 | 3cbee15b | j_mayer | isa_mem_base = 0x80000000;
|
252 | aae9366a | j_mayer | |
253 | 3cbee15b | j_mayer | /* Register 2 MB of ISA IO space */
|
254 | 3cbee15b | j_mayer | isa_mmio_init(0xfe000000, 0x00200000); |
255 | 3cbee15b | j_mayer | |
256 | 3cbee15b | j_mayer | /* XXX: we register only 1 output pin for heathrow PIC */
|
257 | 3cbee15b | j_mayer | heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
|
258 | 3cbee15b | j_mayer | heathrow_irqs[0] =
|
259 | 3cbee15b | j_mayer | qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1); |
260 | 3cbee15b | j_mayer | /* Connect the heathrow PIC outputs to the 6xx bus */
|
261 | 3cbee15b | j_mayer | for (i = 0; i < smp_cpus; i++) { |
262 | 3cbee15b | j_mayer | switch (PPC_INPUT(env)) {
|
263 | 3cbee15b | j_mayer | case PPC_FLAGS_INPUT_6xx:
|
264 | 3cbee15b | j_mayer | heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); |
265 | 3cbee15b | j_mayer | heathrow_irqs[i][0] =
|
266 | 3cbee15b | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; |
267 | 3cbee15b | j_mayer | break;
|
268 | 3cbee15b | j_mayer | default:
|
269 | 3cbee15b | j_mayer | cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
|
270 | 3cbee15b | j_mayer | exit(1);
|
271 | 3cbee15b | j_mayer | } |
272 | 3cbee15b | j_mayer | } |
273 | 3cbee15b | j_mayer | |
274 | 3cbee15b | j_mayer | /* init basic PC hardware */
|
275 | 3cbee15b | j_mayer | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
|
276 | 3cbee15b | j_mayer | cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
|
277 | 3cbee15b | j_mayer | exit(1);
|
278 | 3cbee15b | j_mayer | } |
279 | 3cbee15b | j_mayer | pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
|
280 | 3cbee15b | j_mayer | pci_bus = pci_grackle_init(0xfec00000, pic);
|
281 | 3cbee15b | j_mayer | pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, |
282 | 3cbee15b | j_mayer | ram_size, vga_ram_size, |
283 | 3cbee15b | j_mayer | vga_bios_offset, vga_bios_size); |
284 | aae9366a | j_mayer | |
285 | 3cbee15b | j_mayer | /* XXX: suppress that */
|
286 | 3cbee15b | j_mayer | dummy_irq = i8259_init(NULL);
|
287 | 3cbee15b | j_mayer | |
288 | 3cbee15b | j_mayer | /* XXX: use Mac Serial port */
|
289 | b6cd0ea1 | aurel32 | serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]); |
290 | aae9366a | j_mayer | |
291 | 3cbee15b | j_mayer | for(i = 0; i < nb_nics; i++) { |
292 | 3cbee15b | j_mayer | if (!nd_table[i].model)
|
293 | 3cbee15b | j_mayer | nd_table[i].model = "ne2k_pci";
|
294 | 3cbee15b | j_mayer | pci_nic_init(pci_bus, &nd_table[i], -1);
|
295 | 3cbee15b | j_mayer | } |
296 | 0d913fdb | j_mayer | |
297 | 0d913fdb | j_mayer | /* First IDE channel is a CMD646 on the PCI bus */
|
298 | e4bcb14c | ths | |
299 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
300 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
301 | e4bcb14c | ths | exit(1);
|
302 | e4bcb14c | ths | } |
303 | e4bcb14c | ths | index = drive_get_index(IF_IDE, 0, 0); |
304 | e4bcb14c | ths | if (index == -1) |
305 | e4bcb14c | ths | hd[0] = NULL; |
306 | e4bcb14c | ths | else
|
307 | e4bcb14c | ths | hd[0] = drives_table[index].bdrv;
|
308 | e4bcb14c | ths | index = drive_get_index(IF_IDE, 0, 1); |
309 | e4bcb14c | ths | if (index == -1) |
310 | e4bcb14c | ths | hd[1] = NULL; |
311 | e4bcb14c | ths | else
|
312 | e4bcb14c | ths | hd[1] = drives_table[index].bdrv;
|
313 | e4bcb14c | ths | hd[3] = hd[2] = NULL; |
314 | e4bcb14c | ths | pci_cmd646_ide_init(pci_bus, hd, 0);
|
315 | e4bcb14c | ths | |
316 | 0d913fdb | j_mayer | /* Second IDE channel is a MAC IDE on the MacIO bus */
|
317 | e4bcb14c | ths | index = drive_get_index(IF_IDE, 1, 0); |
318 | e4bcb14c | ths | if (index == -1) |
319 | e4bcb14c | ths | hd[0] = NULL; |
320 | e4bcb14c | ths | else
|
321 | e4bcb14c | ths | hd[0] = drives_table[index].bdrv;
|
322 | e4bcb14c | ths | index = drive_get_index(IF_IDE, 1, 1); |
323 | e4bcb14c | ths | if (index == -1) |
324 | e4bcb14c | ths | hd[1] = NULL; |
325 | e4bcb14c | ths | else
|
326 | e4bcb14c | ths | hd[1] = drives_table[index].bdrv;
|
327 | 0d913fdb | j_mayer | ide_mem_index[0] = -1; |
328 | e4bcb14c | ths | ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D]); |
329 | 3cbee15b | j_mayer | |
330 | 3cbee15b | j_mayer | /* cuda also initialize ADB */
|
331 | 3cbee15b | j_mayer | cuda_init(&cuda_mem_index, pic[0x12]);
|
332 | 3cbee15b | j_mayer | |
333 | 3cbee15b | j_mayer | adb_kbd_init(&adb_bus); |
334 | 3cbee15b | j_mayer | adb_mouse_init(&adb_bus); |
335 | aae9366a | j_mayer | |
336 | 74e91155 | j_mayer | nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
|
337 | 3cbee15b | j_mayer | pmac_format_nvram_partition(nvr, 0x2000);
|
338 | 3cbee15b | j_mayer | |
339 | 3cbee15b | j_mayer | dbdma_init(&dbdma_mem_index); |
340 | 28c5af54 | j_mayer | |
341 | 3cbee15b | j_mayer | macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index, |
342 | 0d913fdb | j_mayer | cuda_mem_index, nvr, 2, ide_mem_index);
|
343 | 3cbee15b | j_mayer | |
344 | 3cbee15b | j_mayer | if (usb_enabled) {
|
345 | 3cbee15b | j_mayer | usb_ohci_init_pci(pci_bus, 3, -1); |
346 | 3cbee15b | j_mayer | } |
347 | 3cbee15b | j_mayer | |
348 | 3cbee15b | j_mayer | if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) |
349 | 3cbee15b | j_mayer | graphic_depth = 15;
|
350 | 3cbee15b | j_mayer | |
351 | 3cbee15b | j_mayer | m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59); |
352 | 3cbee15b | j_mayer | nvram.opaque = m48t59; |
353 | 3cbee15b | j_mayer | nvram.read_fn = &m48t59_read; |
354 | 3cbee15b | j_mayer | nvram.write_fn = &m48t59_write; |
355 | 6ac0e82d | balrog | PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
|
356 | 6ac0e82d | balrog | ppc_boot_device, kernel_base, kernel_size, |
357 | 3cbee15b | j_mayer | kernel_cmdline, |
358 | 3cbee15b | j_mayer | initrd_base, initrd_size, |
359 | 3cbee15b | j_mayer | /* XXX: need an option to load a NVRAM image */
|
360 | 3cbee15b | j_mayer | 0,
|
361 | 3cbee15b | j_mayer | graphic_width, graphic_height, graphic_depth); |
362 | 3cbee15b | j_mayer | /* No PCI init: the BIOS will do it */
|
363 | 3cbee15b | j_mayer | |
364 | 3cbee15b | j_mayer | /* Special port to get debug messages from Open-Firmware */
|
365 | 3cbee15b | j_mayer | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
366 | 3cbee15b | j_mayer | } |
367 | 3cbee15b | j_mayer | |
368 | 3cbee15b | j_mayer | QEMUMachine heathrow_machine = { |
369 | 4b32e168 | aliguori | .name = "g3bw",
|
370 | 4b32e168 | aliguori | .desc = "Heathrow based PowerMAC",
|
371 | 4b32e168 | aliguori | .init = ppc_heathrow_init, |
372 | 4b32e168 | aliguori | .ram_require = BIOS_SIZE + VGA_RAM_SIZE, |
373 | 3d878caa | balrog | .max_cpus = MAX_CPUS, |
374 | 3cbee15b | j_mayer | }; |