root / hw / block / pflash_cfi01.c @ 4b6fedca
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/*
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* CFI parallel flash with Intel command set emulation
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*
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* Copyright (c) 2006 Thorsten Zitterell
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* Copyright (c) 2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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* Supported commands/modes are:
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* - flash read
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* - flash write
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* - flash ID read
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* - sector erase
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* - CFI queries
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*
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* It does not support timings
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* It does not support flash interleaving
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* It does not implement software data protection as found in many real chips
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* It does not implement erase suspend/resume commands
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* It does not implement multiple sectors erase
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*
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* It does not implement much more ...
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*/
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#include "hw/hw.h" |
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#include "hw/block/flash.h" |
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#include "block/block.h" |
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#include "qemu/timer.h" |
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#include "exec/address-spaces.h" |
44 |
#include "qemu/host-utils.h" |
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#include "hw/sysbus.h" |
46 |
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#define PFLASH_BUG(fmt, ...) \
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do { \
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fprintf(stderr, "PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \ |
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exit(1); \
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} while(0) |
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|
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/* #define PFLASH_DEBUG */
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#ifdef PFLASH_DEBUG
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#define DPRINTF(fmt, ...) \
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do { \
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fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \ |
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} while (0) |
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#else
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#define DPRINTF(fmt, ...) do { } while (0) |
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#endif
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|
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#define TYPE_CFI_PFLASH01 "cfi.pflash01" |
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#define CFI_PFLASH01(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH01)
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|
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struct pflash_t {
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/*< private >*/
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SysBusDevice parent_obj; |
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/*< public >*/
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|
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BlockDriverState *bs; |
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uint32_t nb_blocs; |
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uint64_t sector_len; |
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uint8_t bank_width; |
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uint8_t be; |
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uint8_t wcycle; /* if 0, the flash is read normally */
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int ro;
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uint8_t cmd; |
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uint8_t status; |
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uint16_t ident0; |
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uint16_t ident1; |
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uint16_t ident2; |
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uint16_t ident3; |
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uint8_t cfi_len; |
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uint8_t cfi_table[0x52];
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uint64_t counter; |
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unsigned int writeblock_size; |
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QEMUTimer *timer; |
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MemoryRegion mem; |
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char *name;
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void *storage;
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}; |
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static const VMStateDescription vmstate_pflash = { |
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.name = "pflash_cfi01",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) { |
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VMSTATE_UINT8(wcycle, pflash_t), |
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VMSTATE_UINT8(cmd, pflash_t), |
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VMSTATE_UINT8(status, pflash_t), |
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VMSTATE_UINT64(counter, pflash_t), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
106 |
|
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static void pflash_timer (void *opaque) |
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{ |
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pflash_t *pfl = opaque; |
110 |
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DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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/* Reset flash */
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pfl->status ^= 0x80;
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memory_region_rom_device_set_romd(&pfl->mem, true);
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pfl->wcycle = 0;
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pfl->cmd = 0;
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} |
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static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
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int width, int be) |
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{ |
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hwaddr boff; |
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uint32_t ret; |
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uint8_t *p; |
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|
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ret = -1;
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boff = offset & 0xFF; /* why this here ?? */ |
128 |
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if (pfl->bank_width == 2) { |
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boff = boff >> 1;
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} else if (pfl->bank_width == 4) { |
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boff = boff >> 2;
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} |
134 |
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#if 0
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DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
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__func__, offset, pfl->cmd, width);
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#endif
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switch (pfl->cmd) {
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default:
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/* This should never happen : reset state & treat it as a read */
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DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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pfl->wcycle = 0;
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pfl->cmd = 0;
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/* fall through to read code */
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case 0x00: |
147 |
/* Flash area read */
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p = pfl->storage; |
149 |
switch (width) {
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case 1: |
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ret = p[offset]; |
152 |
DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n", |
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__func__, offset, ret); |
154 |
break;
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case 2: |
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if (be) {
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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} else {
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ret = p[offset]; |
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ret |= p[offset + 1] << 8; |
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} |
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DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n", |
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__func__, offset, ret); |
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break;
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case 4: |
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if (be) {
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16; |
170 |
ret |= p[offset + 2] << 8; |
171 |
ret |= p[offset + 3];
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} else {
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ret = p[offset]; |
174 |
ret |= p[offset + 1] << 8; |
175 |
ret |= p[offset + 2] << 16; |
176 |
ret |= p[offset + 3] << 24; |
177 |
} |
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DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n", |
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__func__, offset, ret); |
180 |
break;
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default:
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DPRINTF("BUG in %s\n", __func__);
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} |
184 |
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break;
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186 |
case 0x10: /* Single byte program */ |
187 |
case 0x20: /* Block erase */ |
188 |
case 0x28: /* Block erase */ |
189 |
case 0x40: /* single byte program */ |
190 |
case 0x50: /* Clear status register */ |
191 |
case 0x60: /* Block /un)lock */ |
192 |
case 0x70: /* Status Register */ |
193 |
case 0xe8: /* Write block */ |
194 |
/* Status register read */
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ret = pfl->status; |
196 |
if (width > 2) { |
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ret |= pfl->status << 16;
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} |
199 |
DPRINTF("%s: status %x\n", __func__, ret);
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break;
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case 0x90: |
202 |
switch (boff) {
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case 0: |
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ret = pfl->ident0 << 8 | pfl->ident1;
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DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret);
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break;
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case 1: |
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ret = pfl->ident2 << 8 | pfl->ident3;
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DPRINTF("%s: Device ID Code %04x\n", __func__, ret);
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break;
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default:
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DPRINTF("%s: Read Device Information boff=%x\n", __func__,
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(unsigned)boff);
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ret = 0;
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break;
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216 |
} |
217 |
break;
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case 0x98: /* Query mode */ |
219 |
if (boff > pfl->cfi_len)
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ret = 0;
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else
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ret = pfl->cfi_table[boff]; |
223 |
break;
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} |
225 |
return ret;
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} |
227 |
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/* update flash content on disk */
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static void pflash_update(pflash_t *pfl, int offset, |
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int size)
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{ |
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int offset_end;
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if (pfl->bs) {
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offset_end = offset + size; |
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/* round to sectors */
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offset = offset >> 9;
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offset_end = (offset_end + 511) >> 9; |
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bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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offset_end - offset); |
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} |
241 |
} |
242 |
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static inline void pflash_data_write(pflash_t *pfl, hwaddr offset, |
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uint32_t value, int width, int be) |
245 |
{ |
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uint8_t *p = pfl->storage; |
247 |
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DPRINTF("%s: block write offset " TARGET_FMT_plx
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" value %x counter %016" PRIx64 "\n", |
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__func__, offset, value, pfl->counter); |
251 |
switch (width) {
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case 1: |
253 |
p[offset] = value; |
254 |
break;
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255 |
case 2: |
256 |
if (be) {
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p[offset] = value >> 8;
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p[offset + 1] = value;
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} else {
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p[offset] = value; |
261 |
p[offset + 1] = value >> 8; |
262 |
} |
263 |
break;
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case 4: |
265 |
if (be) {
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p[offset] = value >> 24;
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p[offset + 1] = value >> 16; |
268 |
p[offset + 2] = value >> 8; |
269 |
p[offset + 3] = value;
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} else {
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p[offset] = value; |
272 |
p[offset + 1] = value >> 8; |
273 |
p[offset + 2] = value >> 16; |
274 |
p[offset + 3] = value >> 24; |
275 |
} |
276 |
break;
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277 |
} |
278 |
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279 |
} |
280 |
|
281 |
static void pflash_write(pflash_t *pfl, hwaddr offset, |
282 |
uint32_t value, int width, int be) |
283 |
{ |
284 |
uint8_t *p; |
285 |
uint8_t cmd; |
286 |
|
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cmd = value; |
288 |
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DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n", |
290 |
__func__, offset, value, width, pfl->wcycle); |
291 |
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292 |
if (!pfl->wcycle) {
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293 |
/* Set the device in I/O access mode */
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memory_region_rom_device_set_romd(&pfl->mem, false);
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295 |
} |
296 |
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297 |
switch (pfl->wcycle) {
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case 0: |
299 |
/* read mode */
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300 |
switch (cmd) {
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case 0x00: /* ??? */ |
302 |
goto reset_flash;
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303 |
case 0x10: /* Single Byte Program */ |
304 |
case 0x40: /* Single Byte Program */ |
305 |
DPRINTF("%s: Single Byte Program\n", __func__);
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306 |
break;
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307 |
case 0x20: /* Block erase */ |
308 |
p = pfl->storage; |
309 |
offset &= ~(pfl->sector_len - 1);
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310 |
|
311 |
DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n", |
312 |
__func__, offset, (unsigned)pfl->sector_len);
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313 |
|
314 |
if (!pfl->ro) {
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315 |
memset(p + offset, 0xff, pfl->sector_len);
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316 |
pflash_update(pfl, offset, pfl->sector_len); |
317 |
} else {
|
318 |
pfl->status |= 0x20; /* Block erase error */ |
319 |
} |
320 |
pfl->status |= 0x80; /* Ready! */ |
321 |
break;
|
322 |
case 0x50: /* Clear status bits */ |
323 |
DPRINTF("%s: Clear status bits\n", __func__);
|
324 |
pfl->status = 0x0;
|
325 |
goto reset_flash;
|
326 |
case 0x60: /* Block (un)lock */ |
327 |
DPRINTF("%s: Block unlock\n", __func__);
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328 |
break;
|
329 |
case 0x70: /* Status Register */ |
330 |
DPRINTF("%s: Read status register\n", __func__);
|
331 |
pfl->cmd = cmd; |
332 |
return;
|
333 |
case 0x90: /* Read Device ID */ |
334 |
DPRINTF("%s: Read Device information\n", __func__);
|
335 |
pfl->cmd = cmd; |
336 |
return;
|
337 |
case 0x98: /* CFI query */ |
338 |
DPRINTF("%s: CFI query\n", __func__);
|
339 |
break;
|
340 |
case 0xe8: /* Write to buffer */ |
341 |
DPRINTF("%s: Write to buffer\n", __func__);
|
342 |
pfl->status |= 0x80; /* Ready! */ |
343 |
break;
|
344 |
case 0xf0: /* Probe for AMD flash */ |
345 |
DPRINTF("%s: Probe for AMD flash\n", __func__);
|
346 |
goto reset_flash;
|
347 |
case 0xff: /* Read array mode */ |
348 |
DPRINTF("%s: Read array mode\n", __func__);
|
349 |
goto reset_flash;
|
350 |
default:
|
351 |
goto error_flash;
|
352 |
} |
353 |
pfl->wcycle++; |
354 |
pfl->cmd = cmd; |
355 |
break;
|
356 |
case 1: |
357 |
switch (pfl->cmd) {
|
358 |
case 0x10: /* Single Byte Program */ |
359 |
case 0x40: /* Single Byte Program */ |
360 |
DPRINTF("%s: Single Byte Program\n", __func__);
|
361 |
if (!pfl->ro) {
|
362 |
pflash_data_write(pfl, offset, value, width, be); |
363 |
pflash_update(pfl, offset, width); |
364 |
} else {
|
365 |
pfl->status |= 0x10; /* Programming error */ |
366 |
} |
367 |
pfl->status |= 0x80; /* Ready! */ |
368 |
pfl->wcycle = 0;
|
369 |
break;
|
370 |
case 0x20: /* Block erase */ |
371 |
case 0x28: |
372 |
if (cmd == 0xd0) { /* confirm */ |
373 |
pfl->wcycle = 0;
|
374 |
pfl->status |= 0x80;
|
375 |
} else if (cmd == 0xff) { /* read array mode */ |
376 |
goto reset_flash;
|
377 |
} else
|
378 |
goto error_flash;
|
379 |
|
380 |
break;
|
381 |
case 0xe8: |
382 |
DPRINTF("%s: block write of %x bytes\n", __func__, value);
|
383 |
pfl->counter = value; |
384 |
pfl->wcycle++; |
385 |
break;
|
386 |
case 0x60: |
387 |
if (cmd == 0xd0) { |
388 |
pfl->wcycle = 0;
|
389 |
pfl->status |= 0x80;
|
390 |
} else if (cmd == 0x01) { |
391 |
pfl->wcycle = 0;
|
392 |
pfl->status |= 0x80;
|
393 |
} else if (cmd == 0xff) { |
394 |
goto reset_flash;
|
395 |
} else {
|
396 |
DPRINTF("%s: Unknown (un)locking command\n", __func__);
|
397 |
goto reset_flash;
|
398 |
} |
399 |
break;
|
400 |
case 0x98: |
401 |
if (cmd == 0xff) { |
402 |
goto reset_flash;
|
403 |
} else {
|
404 |
DPRINTF("%s: leaving query mode\n", __func__);
|
405 |
} |
406 |
break;
|
407 |
default:
|
408 |
goto error_flash;
|
409 |
} |
410 |
break;
|
411 |
case 2: |
412 |
switch (pfl->cmd) {
|
413 |
case 0xe8: /* Block write */ |
414 |
if (!pfl->ro) {
|
415 |
pflash_data_write(pfl, offset, value, width, be); |
416 |
} else {
|
417 |
pfl->status |= 0x10; /* Programming error */ |
418 |
} |
419 |
|
420 |
pfl->status |= 0x80;
|
421 |
|
422 |
if (!pfl->counter) {
|
423 |
hwaddr mask = pfl->writeblock_size - 1;
|
424 |
mask = ~mask; |
425 |
|
426 |
DPRINTF("%s: block write finished\n", __func__);
|
427 |
pfl->wcycle++; |
428 |
if (!pfl->ro) {
|
429 |
/* Flush the entire write buffer onto backing storage. */
|
430 |
pflash_update(pfl, offset & mask, pfl->writeblock_size); |
431 |
} else {
|
432 |
pfl->status |= 0x10; /* Programming error */ |
433 |
} |
434 |
} |
435 |
|
436 |
pfl->counter--; |
437 |
break;
|
438 |
default:
|
439 |
goto error_flash;
|
440 |
} |
441 |
break;
|
442 |
case 3: /* Confirm mode */ |
443 |
switch (pfl->cmd) {
|
444 |
case 0xe8: /* Block write */ |
445 |
if (cmd == 0xd0) { |
446 |
pfl->wcycle = 0;
|
447 |
pfl->status |= 0x80;
|
448 |
} else {
|
449 |
DPRINTF("%s: unknown command for \"write block\"\n", __func__);
|
450 |
PFLASH_BUG("Write block confirm");
|
451 |
goto reset_flash;
|
452 |
} |
453 |
break;
|
454 |
default:
|
455 |
goto error_flash;
|
456 |
} |
457 |
break;
|
458 |
default:
|
459 |
/* Should never happen */
|
460 |
DPRINTF("%s: invalid write state\n", __func__);
|
461 |
goto reset_flash;
|
462 |
} |
463 |
return;
|
464 |
|
465 |
error_flash:
|
466 |
qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence "
|
467 |
"(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)" |
468 |
"\n", __func__, offset, pfl->wcycle, pfl->cmd, value);
|
469 |
|
470 |
reset_flash:
|
471 |
memory_region_rom_device_set_romd(&pfl->mem, true);
|
472 |
|
473 |
pfl->wcycle = 0;
|
474 |
pfl->cmd = 0;
|
475 |
} |
476 |
|
477 |
|
478 |
static uint32_t pflash_readb_be(void *opaque, hwaddr addr) |
479 |
{ |
480 |
return pflash_read(opaque, addr, 1, 1); |
481 |
} |
482 |
|
483 |
static uint32_t pflash_readb_le(void *opaque, hwaddr addr) |
484 |
{ |
485 |
return pflash_read(opaque, addr, 1, 0); |
486 |
} |
487 |
|
488 |
static uint32_t pflash_readw_be(void *opaque, hwaddr addr) |
489 |
{ |
490 |
pflash_t *pfl = opaque; |
491 |
|
492 |
return pflash_read(pfl, addr, 2, 1); |
493 |
} |
494 |
|
495 |
static uint32_t pflash_readw_le(void *opaque, hwaddr addr) |
496 |
{ |
497 |
pflash_t *pfl = opaque; |
498 |
|
499 |
return pflash_read(pfl, addr, 2, 0); |
500 |
} |
501 |
|
502 |
static uint32_t pflash_readl_be(void *opaque, hwaddr addr) |
503 |
{ |
504 |
pflash_t *pfl = opaque; |
505 |
|
506 |
return pflash_read(pfl, addr, 4, 1); |
507 |
} |
508 |
|
509 |
static uint32_t pflash_readl_le(void *opaque, hwaddr addr) |
510 |
{ |
511 |
pflash_t *pfl = opaque; |
512 |
|
513 |
return pflash_read(pfl, addr, 4, 0); |
514 |
} |
515 |
|
516 |
static void pflash_writeb_be(void *opaque, hwaddr addr, |
517 |
uint32_t value) |
518 |
{ |
519 |
pflash_write(opaque, addr, value, 1, 1); |
520 |
} |
521 |
|
522 |
static void pflash_writeb_le(void *opaque, hwaddr addr, |
523 |
uint32_t value) |
524 |
{ |
525 |
pflash_write(opaque, addr, value, 1, 0); |
526 |
} |
527 |
|
528 |
static void pflash_writew_be(void *opaque, hwaddr addr, |
529 |
uint32_t value) |
530 |
{ |
531 |
pflash_t *pfl = opaque; |
532 |
|
533 |
pflash_write(pfl, addr, value, 2, 1); |
534 |
} |
535 |
|
536 |
static void pflash_writew_le(void *opaque, hwaddr addr, |
537 |
uint32_t value) |
538 |
{ |
539 |
pflash_t *pfl = opaque; |
540 |
|
541 |
pflash_write(pfl, addr, value, 2, 0); |
542 |
} |
543 |
|
544 |
static void pflash_writel_be(void *opaque, hwaddr addr, |
545 |
uint32_t value) |
546 |
{ |
547 |
pflash_t *pfl = opaque; |
548 |
|
549 |
pflash_write(pfl, addr, value, 4, 1); |
550 |
} |
551 |
|
552 |
static void pflash_writel_le(void *opaque, hwaddr addr, |
553 |
uint32_t value) |
554 |
{ |
555 |
pflash_t *pfl = opaque; |
556 |
|
557 |
pflash_write(pfl, addr, value, 4, 0); |
558 |
} |
559 |
|
560 |
static const MemoryRegionOps pflash_cfi01_ops_be = { |
561 |
.old_mmio = { |
562 |
.read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, |
563 |
.write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, |
564 |
}, |
565 |
.endianness = DEVICE_NATIVE_ENDIAN, |
566 |
}; |
567 |
|
568 |
static const MemoryRegionOps pflash_cfi01_ops_le = { |
569 |
.old_mmio = { |
570 |
.read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, |
571 |
.write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, |
572 |
}, |
573 |
.endianness = DEVICE_NATIVE_ENDIAN, |
574 |
}; |
575 |
|
576 |
static void pflash_cfi01_realize(DeviceState *dev, Error **errp) |
577 |
{ |
578 |
pflash_t *pfl = CFI_PFLASH01(dev); |
579 |
uint64_t total_len; |
580 |
int ret;
|
581 |
|
582 |
total_len = pfl->sector_len * pfl->nb_blocs; |
583 |
|
584 |
/* XXX: to be fixed */
|
585 |
#if 0
|
586 |
if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
587 |
total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
588 |
return NULL;
|
589 |
#endif
|
590 |
|
591 |
memory_region_init_rom_device( |
592 |
&pfl->mem, OBJECT(dev), |
593 |
pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl, |
594 |
pfl->name, total_len); |
595 |
vmstate_register_ram(&pfl->mem, DEVICE(pfl)); |
596 |
pfl->storage = memory_region_get_ram_ptr(&pfl->mem); |
597 |
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); |
598 |
|
599 |
if (pfl->bs) {
|
600 |
/* read the initial flash content */
|
601 |
ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
602 |
|
603 |
if (ret < 0) { |
604 |
vmstate_unregister_ram(&pfl->mem, DEVICE(pfl)); |
605 |
memory_region_destroy(&pfl->mem); |
606 |
error_setg(errp, "failed to read the initial flash content");
|
607 |
return;
|
608 |
} |
609 |
} |
610 |
|
611 |
if (pfl->bs) {
|
612 |
pfl->ro = bdrv_is_read_only(pfl->bs); |
613 |
} else {
|
614 |
pfl->ro = 0;
|
615 |
} |
616 |
|
617 |
pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); |
618 |
pfl->wcycle = 0;
|
619 |
pfl->cmd = 0;
|
620 |
pfl->status = 0;
|
621 |
/* Hardcoded CFI table */
|
622 |
pfl->cfi_len = 0x52;
|
623 |
/* Standard "QRY" string */
|
624 |
pfl->cfi_table[0x10] = 'Q'; |
625 |
pfl->cfi_table[0x11] = 'R'; |
626 |
pfl->cfi_table[0x12] = 'Y'; |
627 |
/* Command set (Intel) */
|
628 |
pfl->cfi_table[0x13] = 0x01; |
629 |
pfl->cfi_table[0x14] = 0x00; |
630 |
/* Primary extended table address (none) */
|
631 |
pfl->cfi_table[0x15] = 0x31; |
632 |
pfl->cfi_table[0x16] = 0x00; |
633 |
/* Alternate command set (none) */
|
634 |
pfl->cfi_table[0x17] = 0x00; |
635 |
pfl->cfi_table[0x18] = 0x00; |
636 |
/* Alternate extended table (none) */
|
637 |
pfl->cfi_table[0x19] = 0x00; |
638 |
pfl->cfi_table[0x1A] = 0x00; |
639 |
/* Vcc min */
|
640 |
pfl->cfi_table[0x1B] = 0x45; |
641 |
/* Vcc max */
|
642 |
pfl->cfi_table[0x1C] = 0x55; |
643 |
/* Vpp min (no Vpp pin) */
|
644 |
pfl->cfi_table[0x1D] = 0x00; |
645 |
/* Vpp max (no Vpp pin) */
|
646 |
pfl->cfi_table[0x1E] = 0x00; |
647 |
/* Reserved */
|
648 |
pfl->cfi_table[0x1F] = 0x07; |
649 |
/* Timeout for min size buffer write */
|
650 |
pfl->cfi_table[0x20] = 0x07; |
651 |
/* Typical timeout for block erase */
|
652 |
pfl->cfi_table[0x21] = 0x0a; |
653 |
/* Typical timeout for full chip erase (4096 ms) */
|
654 |
pfl->cfi_table[0x22] = 0x00; |
655 |
/* Reserved */
|
656 |
pfl->cfi_table[0x23] = 0x04; |
657 |
/* Max timeout for buffer write */
|
658 |
pfl->cfi_table[0x24] = 0x04; |
659 |
/* Max timeout for block erase */
|
660 |
pfl->cfi_table[0x25] = 0x04; |
661 |
/* Max timeout for chip erase */
|
662 |
pfl->cfi_table[0x26] = 0x00; |
663 |
/* Device size */
|
664 |
pfl->cfi_table[0x27] = ctz32(total_len); // + 1; |
665 |
/* Flash device interface (8 & 16 bits) */
|
666 |
pfl->cfi_table[0x28] = 0x02; |
667 |
pfl->cfi_table[0x29] = 0x00; |
668 |
/* Max number of bytes in multi-bytes write */
|
669 |
if (pfl->bank_width == 1) { |
670 |
pfl->cfi_table[0x2A] = 0x08; |
671 |
} else {
|
672 |
pfl->cfi_table[0x2A] = 0x0B; |
673 |
} |
674 |
pfl->writeblock_size = 1 << pfl->cfi_table[0x2A]; |
675 |
|
676 |
pfl->cfi_table[0x2B] = 0x00; |
677 |
/* Number of erase block regions (uniform) */
|
678 |
pfl->cfi_table[0x2C] = 0x01; |
679 |
/* Erase block region 1 */
|
680 |
pfl->cfi_table[0x2D] = pfl->nb_blocs - 1; |
681 |
pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8; |
682 |
pfl->cfi_table[0x2F] = pfl->sector_len >> 8; |
683 |
pfl->cfi_table[0x30] = pfl->sector_len >> 16; |
684 |
|
685 |
/* Extended */
|
686 |
pfl->cfi_table[0x31] = 'P'; |
687 |
pfl->cfi_table[0x32] = 'R'; |
688 |
pfl->cfi_table[0x33] = 'I'; |
689 |
|
690 |
pfl->cfi_table[0x34] = '1'; |
691 |
pfl->cfi_table[0x35] = '0'; |
692 |
|
693 |
pfl->cfi_table[0x36] = 0x00; |
694 |
pfl->cfi_table[0x37] = 0x00; |
695 |
pfl->cfi_table[0x38] = 0x00; |
696 |
pfl->cfi_table[0x39] = 0x00; |
697 |
|
698 |
pfl->cfi_table[0x3a] = 0x00; |
699 |
|
700 |
pfl->cfi_table[0x3b] = 0x00; |
701 |
pfl->cfi_table[0x3c] = 0x00; |
702 |
|
703 |
pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */ |
704 |
} |
705 |
|
706 |
static Property pflash_cfi01_properties[] = {
|
707 |
DEFINE_PROP_DRIVE("drive", struct pflash_t, bs), |
708 |
DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), |
709 |
DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0), |
710 |
DEFINE_PROP_UINT8("width", struct pflash_t, bank_width, 0), |
711 |
DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0), |
712 |
DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), |
713 |
DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0), |
714 |
DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0), |
715 |
DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0), |
716 |
DEFINE_PROP_STRING("name", struct pflash_t, name), |
717 |
DEFINE_PROP_END_OF_LIST(), |
718 |
}; |
719 |
|
720 |
static void pflash_cfi01_class_init(ObjectClass *klass, void *data) |
721 |
{ |
722 |
DeviceClass *dc = DEVICE_CLASS(klass); |
723 |
|
724 |
dc->realize = pflash_cfi01_realize; |
725 |
dc->props = pflash_cfi01_properties; |
726 |
dc->vmsd = &vmstate_pflash; |
727 |
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
728 |
} |
729 |
|
730 |
|
731 |
static const TypeInfo pflash_cfi01_info = { |
732 |
.name = TYPE_CFI_PFLASH01, |
733 |
.parent = TYPE_SYS_BUS_DEVICE, |
734 |
.instance_size = sizeof(struct pflash_t), |
735 |
.class_init = pflash_cfi01_class_init, |
736 |
}; |
737 |
|
738 |
static void pflash_cfi01_register_types(void) |
739 |
{ |
740 |
type_register_static(&pflash_cfi01_info); |
741 |
} |
742 |
|
743 |
type_init(pflash_cfi01_register_types) |
744 |
|
745 |
pflash_t *pflash_cfi01_register(hwaddr base, |
746 |
DeviceState *qdev, const char *name, |
747 |
hwaddr size, |
748 |
BlockDriverState *bs, |
749 |
uint32_t sector_len, int nb_blocs,
|
750 |
int bank_width, uint16_t id0, uint16_t id1,
|
751 |
uint16_t id2, uint16_t id3, int be)
|
752 |
{ |
753 |
DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH01);
|
754 |
|
755 |
if (bs && qdev_prop_set_drive(dev, "drive", bs)) { |
756 |
abort(); |
757 |
} |
758 |
qdev_prop_set_uint32(dev, "num-blocks", nb_blocs);
|
759 |
qdev_prop_set_uint64(dev, "sector-length", sector_len);
|
760 |
qdev_prop_set_uint8(dev, "width", bank_width);
|
761 |
qdev_prop_set_uint8(dev, "big-endian", !!be);
|
762 |
qdev_prop_set_uint16(dev, "id0", id0);
|
763 |
qdev_prop_set_uint16(dev, "id1", id1);
|
764 |
qdev_prop_set_uint16(dev, "id2", id2);
|
765 |
qdev_prop_set_uint16(dev, "id3", id3);
|
766 |
qdev_prop_set_string(dev, "name", name);
|
767 |
qdev_init_nofail(dev); |
768 |
|
769 |
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
|
770 |
return CFI_PFLASH01(dev);
|
771 |
} |
772 |
|
773 |
MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl) |
774 |
{ |
775 |
return &fl->mem;
|
776 |
} |