root / hw / block / pflash_cfi01.c @ 4b6fedca
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1 | 05ee37eb | balrog | /*
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2 | 05ee37eb | balrog | * CFI parallel flash with Intel command set emulation
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3 | 05ee37eb | balrog | *
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4 | 05ee37eb | balrog | * Copyright (c) 2006 Thorsten Zitterell
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5 | 05ee37eb | balrog | * Copyright (c) 2005 Jocelyn Mayer
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6 | 05ee37eb | balrog | *
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7 | 05ee37eb | balrog | * This library is free software; you can redistribute it and/or
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8 | 05ee37eb | balrog | * modify it under the terms of the GNU Lesser General Public
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9 | 05ee37eb | balrog | * License as published by the Free Software Foundation; either
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10 | 05ee37eb | balrog | * version 2 of the License, or (at your option) any later version.
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11 | 05ee37eb | balrog | *
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12 | 05ee37eb | balrog | * This library is distributed in the hope that it will be useful,
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13 | 05ee37eb | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 05ee37eb | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 05ee37eb | balrog | * Lesser General Public License for more details.
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16 | 05ee37eb | balrog | *
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17 | 05ee37eb | balrog | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 05ee37eb | balrog | */
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20 | 05ee37eb | balrog | |
21 | 05ee37eb | balrog | /*
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22 | 05ee37eb | balrog | * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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23 | 05ee37eb | balrog | * Supported commands/modes are:
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24 | 05ee37eb | balrog | * - flash read
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25 | 05ee37eb | balrog | * - flash write
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26 | 05ee37eb | balrog | * - flash ID read
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27 | 05ee37eb | balrog | * - sector erase
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28 | 05ee37eb | balrog | * - CFI queries
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29 | 05ee37eb | balrog | *
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30 | 05ee37eb | balrog | * It does not support timings
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31 | 05ee37eb | balrog | * It does not support flash interleaving
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32 | 05ee37eb | balrog | * It does not implement software data protection as found in many real chips
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33 | 05ee37eb | balrog | * It does not implement erase suspend/resume commands
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34 | 05ee37eb | balrog | * It does not implement multiple sectors erase
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35 | 05ee37eb | balrog | *
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36 | 05ee37eb | balrog | * It does not implement much more ...
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37 | 05ee37eb | balrog | */
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38 | 05ee37eb | balrog | |
39 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
40 | 0d09e41a | Paolo Bonzini | #include "hw/block/flash.h" |
41 | 737e150e | Paolo Bonzini | #include "block/block.h" |
42 | 1de7afc9 | Paolo Bonzini | #include "qemu/timer.h" |
43 | 022c62cb | Paolo Bonzini | #include "exec/address-spaces.h" |
44 | 1de7afc9 | Paolo Bonzini | #include "qemu/host-utils.h" |
45 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
46 | 05ee37eb | balrog | |
47 | 001faf32 | Blue Swirl | #define PFLASH_BUG(fmt, ...) \
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48 | 05ee37eb | balrog | do { \
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49 | ec9ea489 | Peter Crosthwaite | fprintf(stderr, "PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \ |
50 | 05ee37eb | balrog | exit(1); \
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51 | 05ee37eb | balrog | } while(0) |
52 | 05ee37eb | balrog | |
53 | 05ee37eb | balrog | /* #define PFLASH_DEBUG */
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54 | 05ee37eb | balrog | #ifdef PFLASH_DEBUG
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55 | ec9ea489 | Peter Crosthwaite | #define DPRINTF(fmt, ...) \
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56 | ec9ea489 | Peter Crosthwaite | do { \
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57 | ec9ea489 | Peter Crosthwaite | fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \ |
58 | 05ee37eb | balrog | } while (0) |
59 | 05ee37eb | balrog | #else
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60 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do { } while (0) |
61 | 05ee37eb | balrog | #endif
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62 | 05ee37eb | balrog | |
63 | f1b44f0e | Hu Tao | #define TYPE_CFI_PFLASH01 "cfi.pflash01" |
64 | f1b44f0e | Hu Tao | #define CFI_PFLASH01(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH01)
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65 | f1b44f0e | Hu Tao | |
66 | c227f099 | Anthony Liguori | struct pflash_t {
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67 | f1b44f0e | Hu Tao | /*< private >*/
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68 | f1b44f0e | Hu Tao | SysBusDevice parent_obj; |
69 | f1b44f0e | Hu Tao | /*< public >*/
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70 | f1b44f0e | Hu Tao | |
71 | 05ee37eb | balrog | BlockDriverState *bs; |
72 | 368a354f | Peter Crosthwaite | uint32_t nb_blocs; |
73 | 368a354f | Peter Crosthwaite | uint64_t sector_len; |
74 | 4b6fedca | Roy Franz | uint8_t bank_width; |
75 | 368a354f | Peter Crosthwaite | uint8_t be; |
76 | d8d24fb7 | Peter Maydell | uint8_t wcycle; /* if 0, the flash is read normally */
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77 | 05ee37eb | balrog | int ro;
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78 | 05ee37eb | balrog | uint8_t cmd; |
79 | 05ee37eb | balrog | uint8_t status; |
80 | 368a354f | Peter Crosthwaite | uint16_t ident0; |
81 | 368a354f | Peter Crosthwaite | uint16_t ident1; |
82 | 368a354f | Peter Crosthwaite | uint16_t ident2; |
83 | 368a354f | Peter Crosthwaite | uint16_t ident3; |
84 | 05ee37eb | balrog | uint8_t cfi_len; |
85 | 05ee37eb | balrog | uint8_t cfi_table[0x52];
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86 | d8d24fb7 | Peter Maydell | uint64_t counter; |
87 | b4bf0a9a | Edgar E. Iglesias | unsigned int writeblock_size; |
88 | 05ee37eb | balrog | QEMUTimer *timer; |
89 | cfe5f011 | Avi Kivity | MemoryRegion mem; |
90 | 368a354f | Peter Crosthwaite | char *name;
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91 | 05ee37eb | balrog | void *storage;
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92 | 05ee37eb | balrog | }; |
93 | 05ee37eb | balrog | |
94 | d8d24fb7 | Peter Maydell | static const VMStateDescription vmstate_pflash = { |
95 | d8d24fb7 | Peter Maydell | .name = "pflash_cfi01",
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96 | d8d24fb7 | Peter Maydell | .version_id = 1,
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97 | d8d24fb7 | Peter Maydell | .minimum_version_id = 1,
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98 | d8d24fb7 | Peter Maydell | .fields = (VMStateField[]) { |
99 | d8d24fb7 | Peter Maydell | VMSTATE_UINT8(wcycle, pflash_t), |
100 | d8d24fb7 | Peter Maydell | VMSTATE_UINT8(cmd, pflash_t), |
101 | d8d24fb7 | Peter Maydell | VMSTATE_UINT8(status, pflash_t), |
102 | d8d24fb7 | Peter Maydell | VMSTATE_UINT64(counter, pflash_t), |
103 | d8d24fb7 | Peter Maydell | VMSTATE_END_OF_LIST() |
104 | d8d24fb7 | Peter Maydell | } |
105 | d8d24fb7 | Peter Maydell | }; |
106 | d8d24fb7 | Peter Maydell | |
107 | 05ee37eb | balrog | static void pflash_timer (void *opaque) |
108 | 05ee37eb | balrog | { |
109 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
110 | 05ee37eb | balrog | |
111 | 05ee37eb | balrog | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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112 | 05ee37eb | balrog | /* Reset flash */
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113 | 05ee37eb | balrog | pfl->status ^= 0x80;
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114 | 5f9a5ea1 | Jan Kiszka | memory_region_rom_device_set_romd(&pfl->mem, true);
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115 | 5d79b80b | Peter Maydell | pfl->wcycle = 0;
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116 | 05ee37eb | balrog | pfl->cmd = 0;
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117 | 05ee37eb | balrog | } |
118 | 05ee37eb | balrog | |
119 | a8170e5e | Avi Kivity | static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
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120 | 3d08ff69 | Blue Swirl | int width, int be) |
121 | 05ee37eb | balrog | { |
122 | a8170e5e | Avi Kivity | hwaddr boff; |
123 | 05ee37eb | balrog | uint32_t ret; |
124 | 05ee37eb | balrog | uint8_t *p; |
125 | 05ee37eb | balrog | |
126 | 05ee37eb | balrog | ret = -1;
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127 | 05ee37eb | balrog | boff = offset & 0xFF; /* why this here ?? */ |
128 | 05ee37eb | balrog | |
129 | 4b6fedca | Roy Franz | if (pfl->bank_width == 2) { |
130 | 05ee37eb | balrog | boff = boff >> 1;
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131 | 4b6fedca | Roy Franz | } else if (pfl->bank_width == 4) { |
132 | 05ee37eb | balrog | boff = boff >> 2;
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133 | 4b6fedca | Roy Franz | } |
134 | 05ee37eb | balrog | |
135 | fad8c772 | Edgar E. Iglesias | #if 0
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136 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
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137 | 06adb549 | balrog | __func__, offset, pfl->cmd, width);
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138 | fad8c772 | Edgar E. Iglesias | #endif
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139 | 05ee37eb | balrog | switch (pfl->cmd) {
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140 | 1be97bf2 | Peter Maydell | default:
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141 | 1be97bf2 | Peter Maydell | /* This should never happen : reset state & treat it as a read */
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142 | 1be97bf2 | Peter Maydell | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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143 | 1be97bf2 | Peter Maydell | pfl->wcycle = 0;
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144 | 1be97bf2 | Peter Maydell | pfl->cmd = 0;
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145 | 1be97bf2 | Peter Maydell | /* fall through to read code */
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146 | 05ee37eb | balrog | case 0x00: |
147 | 05ee37eb | balrog | /* Flash area read */
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148 | 05ee37eb | balrog | p = pfl->storage; |
149 | 05ee37eb | balrog | switch (width) {
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150 | 05ee37eb | balrog | case 1: |
151 | 05ee37eb | balrog | ret = p[offset]; |
152 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n", |
153 | c8b153d7 | ths | __func__, offset, ret); |
154 | 05ee37eb | balrog | break;
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155 | 05ee37eb | balrog | case 2: |
156 | 3d08ff69 | Blue Swirl | if (be) {
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157 | 3d08ff69 | Blue Swirl | ret = p[offset] << 8;
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158 | 3d08ff69 | Blue Swirl | ret |= p[offset + 1];
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159 | 3d08ff69 | Blue Swirl | } else {
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160 | 3d08ff69 | Blue Swirl | ret = p[offset]; |
161 | 3d08ff69 | Blue Swirl | ret |= p[offset + 1] << 8; |
162 | 3d08ff69 | Blue Swirl | } |
163 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n", |
164 | c8b153d7 | ths | __func__, offset, ret); |
165 | 05ee37eb | balrog | break;
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166 | 05ee37eb | balrog | case 4: |
167 | 3d08ff69 | Blue Swirl | if (be) {
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168 | 3d08ff69 | Blue Swirl | ret = p[offset] << 24;
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169 | 3d08ff69 | Blue Swirl | ret |= p[offset + 1] << 16; |
170 | 3d08ff69 | Blue Swirl | ret |= p[offset + 2] << 8; |
171 | 3d08ff69 | Blue Swirl | ret |= p[offset + 3];
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172 | 3d08ff69 | Blue Swirl | } else {
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173 | 3d08ff69 | Blue Swirl | ret = p[offset]; |
174 | 3d08ff69 | Blue Swirl | ret |= p[offset + 1] << 8; |
175 | 3d08ff69 | Blue Swirl | ret |= p[offset + 2] << 16; |
176 | 3d08ff69 | Blue Swirl | ret |= p[offset + 3] << 24; |
177 | 3d08ff69 | Blue Swirl | } |
178 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n", |
179 | c8b153d7 | ths | __func__, offset, ret); |
180 | 05ee37eb | balrog | break;
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181 | 05ee37eb | balrog | default:
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182 | 05ee37eb | balrog | DPRINTF("BUG in %s\n", __func__);
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183 | 05ee37eb | balrog | } |
184 | 05ee37eb | balrog | |
185 | 05ee37eb | balrog | break;
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186 | 6e392787 | Peter Maydell | case 0x10: /* Single byte program */ |
187 | 05ee37eb | balrog | case 0x20: /* Block erase */ |
188 | 6e392787 | Peter Maydell | case 0x28: /* Block erase */ |
189 | 6e392787 | Peter Maydell | case 0x40: /* single byte program */ |
190 | 05ee37eb | balrog | case 0x50: /* Clear status register */ |
191 | 05ee37eb | balrog | case 0x60: /* Block /un)lock */ |
192 | 05ee37eb | balrog | case 0x70: /* Status Register */ |
193 | 05ee37eb | balrog | case 0xe8: /* Write block */ |
194 | 05ee37eb | balrog | /* Status register read */
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195 | 05ee37eb | balrog | ret = pfl->status; |
196 | ea0a4f34 | Paul Burton | if (width > 2) { |
197 | ea0a4f34 | Paul Burton | ret |= pfl->status << 16;
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198 | ea0a4f34 | Paul Burton | } |
199 | 05ee37eb | balrog | DPRINTF("%s: status %x\n", __func__, ret);
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200 | 05ee37eb | balrog | break;
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201 | 0b2ec6fc | Michael Walle | case 0x90: |
202 | 0b2ec6fc | Michael Walle | switch (boff) {
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203 | 0b2ec6fc | Michael Walle | case 0: |
204 | 368a354f | Peter Crosthwaite | ret = pfl->ident0 << 8 | pfl->ident1;
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205 | 0b2ec6fc | Michael Walle | DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret);
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206 | 0b2ec6fc | Michael Walle | break;
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207 | 0b2ec6fc | Michael Walle | case 1: |
208 | 368a354f | Peter Crosthwaite | ret = pfl->ident2 << 8 | pfl->ident3;
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209 | 0b2ec6fc | Michael Walle | DPRINTF("%s: Device ID Code %04x\n", __func__, ret);
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210 | 0b2ec6fc | Michael Walle | break;
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211 | 0b2ec6fc | Michael Walle | default:
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212 | fc5b64d0 | Peter Crosthwaite | DPRINTF("%s: Read Device Information boff=%x\n", __func__,
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213 | fc5b64d0 | Peter Crosthwaite | (unsigned)boff);
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214 | 0b2ec6fc | Michael Walle | ret = 0;
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215 | 0b2ec6fc | Michael Walle | break;
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216 | 0b2ec6fc | Michael Walle | } |
217 | 0b2ec6fc | Michael Walle | break;
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218 | 05ee37eb | balrog | case 0x98: /* Query mode */ |
219 | 05ee37eb | balrog | if (boff > pfl->cfi_len)
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220 | 05ee37eb | balrog | ret = 0;
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221 | 05ee37eb | balrog | else
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222 | 05ee37eb | balrog | ret = pfl->cfi_table[boff]; |
223 | 05ee37eb | balrog | break;
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224 | 05ee37eb | balrog | } |
225 | 05ee37eb | balrog | return ret;
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226 | 05ee37eb | balrog | } |
227 | 05ee37eb | balrog | |
228 | 05ee37eb | balrog | /* update flash content on disk */
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229 | c227f099 | Anthony Liguori | static void pflash_update(pflash_t *pfl, int offset, |
230 | 05ee37eb | balrog | int size)
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231 | 05ee37eb | balrog | { |
232 | 05ee37eb | balrog | int offset_end;
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233 | 05ee37eb | balrog | if (pfl->bs) {
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234 | 05ee37eb | balrog | offset_end = offset + size; |
235 | 05ee37eb | balrog | /* round to sectors */
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236 | 05ee37eb | balrog | offset = offset >> 9;
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237 | 05ee37eb | balrog | offset_end = (offset_end + 511) >> 9; |
238 | 05ee37eb | balrog | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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239 | 05ee37eb | balrog | offset_end - offset); |
240 | 05ee37eb | balrog | } |
241 | 05ee37eb | balrog | } |
242 | 05ee37eb | balrog | |
243 | a8170e5e | Avi Kivity | static inline void pflash_data_write(pflash_t *pfl, hwaddr offset, |
244 | 3d08ff69 | Blue Swirl | uint32_t value, int width, int be) |
245 | d361be25 | balrog | { |
246 | d361be25 | balrog | uint8_t *p = pfl->storage; |
247 | d361be25 | balrog | |
248 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: block write offset " TARGET_FMT_plx
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249 | d8d24fb7 | Peter Maydell | " value %x counter %016" PRIx64 "\n", |
250 | d361be25 | balrog | __func__, offset, value, pfl->counter); |
251 | d361be25 | balrog | switch (width) {
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252 | d361be25 | balrog | case 1: |
253 | d361be25 | balrog | p[offset] = value; |
254 | d361be25 | balrog | break;
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255 | d361be25 | balrog | case 2: |
256 | 3d08ff69 | Blue Swirl | if (be) {
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257 | 3d08ff69 | Blue Swirl | p[offset] = value >> 8;
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258 | 3d08ff69 | Blue Swirl | p[offset + 1] = value;
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259 | 3d08ff69 | Blue Swirl | } else {
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260 | 3d08ff69 | Blue Swirl | p[offset] = value; |
261 | 3d08ff69 | Blue Swirl | p[offset + 1] = value >> 8; |
262 | 3d08ff69 | Blue Swirl | } |
263 | d361be25 | balrog | break;
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264 | d361be25 | balrog | case 4: |
265 | 3d08ff69 | Blue Swirl | if (be) {
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266 | 3d08ff69 | Blue Swirl | p[offset] = value >> 24;
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267 | 3d08ff69 | Blue Swirl | p[offset + 1] = value >> 16; |
268 | 3d08ff69 | Blue Swirl | p[offset + 2] = value >> 8; |
269 | 3d08ff69 | Blue Swirl | p[offset + 3] = value;
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270 | 3d08ff69 | Blue Swirl | } else {
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271 | 3d08ff69 | Blue Swirl | p[offset] = value; |
272 | 3d08ff69 | Blue Swirl | p[offset + 1] = value >> 8; |
273 | 3d08ff69 | Blue Swirl | p[offset + 2] = value >> 16; |
274 | 3d08ff69 | Blue Swirl | p[offset + 3] = value >> 24; |
275 | 3d08ff69 | Blue Swirl | } |
276 | d361be25 | balrog | break;
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277 | d361be25 | balrog | } |
278 | d361be25 | balrog | |
279 | d361be25 | balrog | } |
280 | d361be25 | balrog | |
281 | a8170e5e | Avi Kivity | static void pflash_write(pflash_t *pfl, hwaddr offset, |
282 | 3d08ff69 | Blue Swirl | uint32_t value, int width, int be) |
283 | 05ee37eb | balrog | { |
284 | 05ee37eb | balrog | uint8_t *p; |
285 | 05ee37eb | balrog | uint8_t cmd; |
286 | 05ee37eb | balrog | |
287 | 05ee37eb | balrog | cmd = value; |
288 | 05ee37eb | balrog | |
289 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n", |
290 | c8b153d7 | ths | __func__, offset, value, width, pfl->wcycle); |
291 | 05ee37eb | balrog | |
292 | e9cbbcac | Edgar E. Iglesias | if (!pfl->wcycle) {
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293 | e9cbbcac | Edgar E. Iglesias | /* Set the device in I/O access mode */
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294 | 5f9a5ea1 | Jan Kiszka | memory_region_rom_device_set_romd(&pfl->mem, false);
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295 | e9cbbcac | Edgar E. Iglesias | } |
296 | 05ee37eb | balrog | |
297 | 05ee37eb | balrog | switch (pfl->wcycle) {
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298 | 05ee37eb | balrog | case 0: |
299 | 05ee37eb | balrog | /* read mode */
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300 | 05ee37eb | balrog | switch (cmd) {
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301 | 05ee37eb | balrog | case 0x00: /* ??? */ |
302 | 05ee37eb | balrog | goto reset_flash;
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303 | d361be25 | balrog | case 0x10: /* Single Byte Program */ |
304 | d361be25 | balrog | case 0x40: /* Single Byte Program */ |
305 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: Single Byte Program\n", __func__);
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306 | d361be25 | balrog | break;
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307 | 05ee37eb | balrog | case 0x20: /* Block erase */ |
308 | 05ee37eb | balrog | p = pfl->storage; |
309 | 05ee37eb | balrog | offset &= ~(pfl->sector_len - 1);
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310 | 05ee37eb | balrog | |
311 | 368a354f | Peter Crosthwaite | DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n", |
312 | 368a354f | Peter Crosthwaite | __func__, offset, (unsigned)pfl->sector_len);
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313 | 05ee37eb | balrog | |
314 | de8efe8f | Jordan Justen | if (!pfl->ro) {
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315 | de8efe8f | Jordan Justen | memset(p + offset, 0xff, pfl->sector_len);
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316 | de8efe8f | Jordan Justen | pflash_update(pfl, offset, pfl->sector_len); |
317 | de8efe8f | Jordan Justen | } else {
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318 | de8efe8f | Jordan Justen | pfl->status |= 0x20; /* Block erase error */ |
319 | de8efe8f | Jordan Justen | } |
320 | 05ee37eb | balrog | pfl->status |= 0x80; /* Ready! */ |
321 | 05ee37eb | balrog | break;
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322 | 05ee37eb | balrog | case 0x50: /* Clear status bits */ |
323 | 05ee37eb | balrog | DPRINTF("%s: Clear status bits\n", __func__);
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324 | 05ee37eb | balrog | pfl->status = 0x0;
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325 | 05ee37eb | balrog | goto reset_flash;
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326 | 05ee37eb | balrog | case 0x60: /* Block (un)lock */ |
327 | 05ee37eb | balrog | DPRINTF("%s: Block unlock\n", __func__);
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328 | 05ee37eb | balrog | break;
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329 | 05ee37eb | balrog | case 0x70: /* Status Register */ |
330 | 05ee37eb | balrog | DPRINTF("%s: Read status register\n", __func__);
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331 | 05ee37eb | balrog | pfl->cmd = cmd; |
332 | 05ee37eb | balrog | return;
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333 | 0b2ec6fc | Michael Walle | case 0x90: /* Read Device ID */ |
334 | 0b2ec6fc | Michael Walle | DPRINTF("%s: Read Device information\n", __func__);
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335 | 0b2ec6fc | Michael Walle | pfl->cmd = cmd; |
336 | 0b2ec6fc | Michael Walle | return;
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337 | 05ee37eb | balrog | case 0x98: /* CFI query */ |
338 | 05ee37eb | balrog | DPRINTF("%s: CFI query\n", __func__);
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339 | 05ee37eb | balrog | break;
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340 | 05ee37eb | balrog | case 0xe8: /* Write to buffer */ |
341 | 05ee37eb | balrog | DPRINTF("%s: Write to buffer\n", __func__);
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342 | 05ee37eb | balrog | pfl->status |= 0x80; /* Ready! */ |
343 | 05ee37eb | balrog | break;
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344 | 5928023c | Stefan Weil | case 0xf0: /* Probe for AMD flash */ |
345 | 5928023c | Stefan Weil | DPRINTF("%s: Probe for AMD flash\n", __func__);
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346 | 5928023c | Stefan Weil | goto reset_flash;
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347 | 05ee37eb | balrog | case 0xff: /* Read array mode */ |
348 | 05ee37eb | balrog | DPRINTF("%s: Read array mode\n", __func__);
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349 | 05ee37eb | balrog | goto reset_flash;
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350 | 05ee37eb | balrog | default:
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351 | 05ee37eb | balrog | goto error_flash;
|
352 | 05ee37eb | balrog | } |
353 | 05ee37eb | balrog | pfl->wcycle++; |
354 | 05ee37eb | balrog | pfl->cmd = cmd; |
355 | 12dabc79 | Stefan Weil | break;
|
356 | 05ee37eb | balrog | case 1: |
357 | 05ee37eb | balrog | switch (pfl->cmd) {
|
358 | d361be25 | balrog | case 0x10: /* Single Byte Program */ |
359 | d361be25 | balrog | case 0x40: /* Single Byte Program */ |
360 | d361be25 | balrog | DPRINTF("%s: Single Byte Program\n", __func__);
|
361 | de8efe8f | Jordan Justen | if (!pfl->ro) {
|
362 | de8efe8f | Jordan Justen | pflash_data_write(pfl, offset, value, width, be); |
363 | de8efe8f | Jordan Justen | pflash_update(pfl, offset, width); |
364 | de8efe8f | Jordan Justen | } else {
|
365 | de8efe8f | Jordan Justen | pfl->status |= 0x10; /* Programming error */ |
366 | de8efe8f | Jordan Justen | } |
367 | d361be25 | balrog | pfl->status |= 0x80; /* Ready! */ |
368 | d361be25 | balrog | pfl->wcycle = 0;
|
369 | d361be25 | balrog | break;
|
370 | 05ee37eb | balrog | case 0x20: /* Block erase */ |
371 | 05ee37eb | balrog | case 0x28: |
372 | 05ee37eb | balrog | if (cmd == 0xd0) { /* confirm */ |
373 | 3656744c | balrog | pfl->wcycle = 0;
|
374 | 05ee37eb | balrog | pfl->status |= 0x80;
|
375 | 9248f413 | aurel32 | } else if (cmd == 0xff) { /* read array mode */ |
376 | 05ee37eb | balrog | goto reset_flash;
|
377 | 05ee37eb | balrog | } else
|
378 | 05ee37eb | balrog | goto error_flash;
|
379 | 05ee37eb | balrog | |
380 | 05ee37eb | balrog | break;
|
381 | 05ee37eb | balrog | case 0xe8: |
382 | 71fb2348 | balrog | DPRINTF("%s: block write of %x bytes\n", __func__, value);
|
383 | 71fb2348 | balrog | pfl->counter = value; |
384 | 05ee37eb | balrog | pfl->wcycle++; |
385 | 05ee37eb | balrog | break;
|
386 | 05ee37eb | balrog | case 0x60: |
387 | 05ee37eb | balrog | if (cmd == 0xd0) { |
388 | 05ee37eb | balrog | pfl->wcycle = 0;
|
389 | 05ee37eb | balrog | pfl->status |= 0x80;
|
390 | 05ee37eb | balrog | } else if (cmd == 0x01) { |
391 | 05ee37eb | balrog | pfl->wcycle = 0;
|
392 | 05ee37eb | balrog | pfl->status |= 0x80;
|
393 | 05ee37eb | balrog | } else if (cmd == 0xff) { |
394 | 05ee37eb | balrog | goto reset_flash;
|
395 | 05ee37eb | balrog | } else {
|
396 | 05ee37eb | balrog | DPRINTF("%s: Unknown (un)locking command\n", __func__);
|
397 | 05ee37eb | balrog | goto reset_flash;
|
398 | 05ee37eb | balrog | } |
399 | 05ee37eb | balrog | break;
|
400 | 05ee37eb | balrog | case 0x98: |
401 | 05ee37eb | balrog | if (cmd == 0xff) { |
402 | 05ee37eb | balrog | goto reset_flash;
|
403 | 05ee37eb | balrog | } else {
|
404 | 05ee37eb | balrog | DPRINTF("%s: leaving query mode\n", __func__);
|
405 | 05ee37eb | balrog | } |
406 | 05ee37eb | balrog | break;
|
407 | 05ee37eb | balrog | default:
|
408 | 05ee37eb | balrog | goto error_flash;
|
409 | 05ee37eb | balrog | } |
410 | 12dabc79 | Stefan Weil | break;
|
411 | 05ee37eb | balrog | case 2: |
412 | 05ee37eb | balrog | switch (pfl->cmd) {
|
413 | 05ee37eb | balrog | case 0xe8: /* Block write */ |
414 | de8efe8f | Jordan Justen | if (!pfl->ro) {
|
415 | de8efe8f | Jordan Justen | pflash_data_write(pfl, offset, value, width, be); |
416 | de8efe8f | Jordan Justen | } else {
|
417 | de8efe8f | Jordan Justen | pfl->status |= 0x10; /* Programming error */ |
418 | de8efe8f | Jordan Justen | } |
419 | 05ee37eb | balrog | |
420 | 05ee37eb | balrog | pfl->status |= 0x80;
|
421 | 05ee37eb | balrog | |
422 | 05ee37eb | balrog | if (!pfl->counter) {
|
423 | a8170e5e | Avi Kivity | hwaddr mask = pfl->writeblock_size - 1;
|
424 | b4bf0a9a | Edgar E. Iglesias | mask = ~mask; |
425 | b4bf0a9a | Edgar E. Iglesias | |
426 | 05ee37eb | balrog | DPRINTF("%s: block write finished\n", __func__);
|
427 | 05ee37eb | balrog | pfl->wcycle++; |
428 | de8efe8f | Jordan Justen | if (!pfl->ro) {
|
429 | de8efe8f | Jordan Justen | /* Flush the entire write buffer onto backing storage. */
|
430 | de8efe8f | Jordan Justen | pflash_update(pfl, offset & mask, pfl->writeblock_size); |
431 | de8efe8f | Jordan Justen | } else {
|
432 | de8efe8f | Jordan Justen | pfl->status |= 0x10; /* Programming error */ |
433 | de8efe8f | Jordan Justen | } |
434 | 05ee37eb | balrog | } |
435 | 05ee37eb | balrog | |
436 | 05ee37eb | balrog | pfl->counter--; |
437 | 05ee37eb | balrog | break;
|
438 | 7317b8ca | balrog | default:
|
439 | 7317b8ca | balrog | goto error_flash;
|
440 | 05ee37eb | balrog | } |
441 | 12dabc79 | Stefan Weil | break;
|
442 | 05ee37eb | balrog | case 3: /* Confirm mode */ |
443 | 05ee37eb | balrog | switch (pfl->cmd) {
|
444 | 05ee37eb | balrog | case 0xe8: /* Block write */ |
445 | 05ee37eb | balrog | if (cmd == 0xd0) { |
446 | 05ee37eb | balrog | pfl->wcycle = 0;
|
447 | 05ee37eb | balrog | pfl->status |= 0x80;
|
448 | 05ee37eb | balrog | } else {
|
449 | 05ee37eb | balrog | DPRINTF("%s: unknown command for \"write block\"\n", __func__);
|
450 | 05ee37eb | balrog | PFLASH_BUG("Write block confirm");
|
451 | 7317b8ca | balrog | goto reset_flash;
|
452 | 05ee37eb | balrog | } |
453 | 7317b8ca | balrog | break;
|
454 | 7317b8ca | balrog | default:
|
455 | 7317b8ca | balrog | goto error_flash;
|
456 | 05ee37eb | balrog | } |
457 | 12dabc79 | Stefan Weil | break;
|
458 | 05ee37eb | balrog | default:
|
459 | 05ee37eb | balrog | /* Should never happen */
|
460 | 05ee37eb | balrog | DPRINTF("%s: invalid write state\n", __func__);
|
461 | 05ee37eb | balrog | goto reset_flash;
|
462 | 05ee37eb | balrog | } |
463 | 05ee37eb | balrog | return;
|
464 | 05ee37eb | balrog | |
465 | 05ee37eb | balrog | error_flash:
|
466 | d96fc51c | Peter Crosthwaite | qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence "
|
467 | d96fc51c | Peter Crosthwaite | "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)" |
468 | d96fc51c | Peter Crosthwaite | "\n", __func__, offset, pfl->wcycle, pfl->cmd, value);
|
469 | 05ee37eb | balrog | |
470 | 05ee37eb | balrog | reset_flash:
|
471 | 5f9a5ea1 | Jan Kiszka | memory_region_rom_device_set_romd(&pfl->mem, true);
|
472 | 05ee37eb | balrog | |
473 | 05ee37eb | balrog | pfl->wcycle = 0;
|
474 | 05ee37eb | balrog | pfl->cmd = 0;
|
475 | 05ee37eb | balrog | } |
476 | 05ee37eb | balrog | |
477 | 05ee37eb | balrog | |
478 | a8170e5e | Avi Kivity | static uint32_t pflash_readb_be(void *opaque, hwaddr addr) |
479 | 3d08ff69 | Blue Swirl | { |
480 | 3d08ff69 | Blue Swirl | return pflash_read(opaque, addr, 1, 1); |
481 | 3d08ff69 | Blue Swirl | } |
482 | 3d08ff69 | Blue Swirl | |
483 | a8170e5e | Avi Kivity | static uint32_t pflash_readb_le(void *opaque, hwaddr addr) |
484 | 3d08ff69 | Blue Swirl | { |
485 | 3d08ff69 | Blue Swirl | return pflash_read(opaque, addr, 1, 0); |
486 | 3d08ff69 | Blue Swirl | } |
487 | 3d08ff69 | Blue Swirl | |
488 | a8170e5e | Avi Kivity | static uint32_t pflash_readw_be(void *opaque, hwaddr addr) |
489 | 3d08ff69 | Blue Swirl | { |
490 | 3d08ff69 | Blue Swirl | pflash_t *pfl = opaque; |
491 | 3d08ff69 | Blue Swirl | |
492 | 3d08ff69 | Blue Swirl | return pflash_read(pfl, addr, 2, 1); |
493 | 3d08ff69 | Blue Swirl | } |
494 | 3d08ff69 | Blue Swirl | |
495 | a8170e5e | Avi Kivity | static uint32_t pflash_readw_le(void *opaque, hwaddr addr) |
496 | 05ee37eb | balrog | { |
497 | 3d08ff69 | Blue Swirl | pflash_t *pfl = opaque; |
498 | 3d08ff69 | Blue Swirl | |
499 | 3d08ff69 | Blue Swirl | return pflash_read(pfl, addr, 2, 0); |
500 | 05ee37eb | balrog | } |
501 | 05ee37eb | balrog | |
502 | a8170e5e | Avi Kivity | static uint32_t pflash_readl_be(void *opaque, hwaddr addr) |
503 | 05ee37eb | balrog | { |
504 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
505 | 05ee37eb | balrog | |
506 | 3d08ff69 | Blue Swirl | return pflash_read(pfl, addr, 4, 1); |
507 | 05ee37eb | balrog | } |
508 | 05ee37eb | balrog | |
509 | a8170e5e | Avi Kivity | static uint32_t pflash_readl_le(void *opaque, hwaddr addr) |
510 | 05ee37eb | balrog | { |
511 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
512 | 05ee37eb | balrog | |
513 | 3d08ff69 | Blue Swirl | return pflash_read(pfl, addr, 4, 0); |
514 | 05ee37eb | balrog | } |
515 | 05ee37eb | balrog | |
516 | a8170e5e | Avi Kivity | static void pflash_writeb_be(void *opaque, hwaddr addr, |
517 | 3d08ff69 | Blue Swirl | uint32_t value) |
518 | 05ee37eb | balrog | { |
519 | 3d08ff69 | Blue Swirl | pflash_write(opaque, addr, value, 1, 1); |
520 | 05ee37eb | balrog | } |
521 | 05ee37eb | balrog | |
522 | a8170e5e | Avi Kivity | static void pflash_writeb_le(void *opaque, hwaddr addr, |
523 | 3d08ff69 | Blue Swirl | uint32_t value) |
524 | 3d08ff69 | Blue Swirl | { |
525 | 3d08ff69 | Blue Swirl | pflash_write(opaque, addr, value, 1, 0); |
526 | 3d08ff69 | Blue Swirl | } |
527 | 3d08ff69 | Blue Swirl | |
528 | a8170e5e | Avi Kivity | static void pflash_writew_be(void *opaque, hwaddr addr, |
529 | 3d08ff69 | Blue Swirl | uint32_t value) |
530 | 05ee37eb | balrog | { |
531 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
532 | 05ee37eb | balrog | |
533 | 3d08ff69 | Blue Swirl | pflash_write(pfl, addr, value, 2, 1); |
534 | 05ee37eb | balrog | } |
535 | 05ee37eb | balrog | |
536 | a8170e5e | Avi Kivity | static void pflash_writew_le(void *opaque, hwaddr addr, |
537 | 3d08ff69 | Blue Swirl | uint32_t value) |
538 | 05ee37eb | balrog | { |
539 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
540 | 05ee37eb | balrog | |
541 | 3d08ff69 | Blue Swirl | pflash_write(pfl, addr, value, 2, 0); |
542 | 05ee37eb | balrog | } |
543 | 05ee37eb | balrog | |
544 | a8170e5e | Avi Kivity | static void pflash_writel_be(void *opaque, hwaddr addr, |
545 | 3d08ff69 | Blue Swirl | uint32_t value) |
546 | 3d08ff69 | Blue Swirl | { |
547 | 3d08ff69 | Blue Swirl | pflash_t *pfl = opaque; |
548 | 3d08ff69 | Blue Swirl | |
549 | 3d08ff69 | Blue Swirl | pflash_write(pfl, addr, value, 4, 1); |
550 | 3d08ff69 | Blue Swirl | } |
551 | 3d08ff69 | Blue Swirl | |
552 | a8170e5e | Avi Kivity | static void pflash_writel_le(void *opaque, hwaddr addr, |
553 | 3d08ff69 | Blue Swirl | uint32_t value) |
554 | 3d08ff69 | Blue Swirl | { |
555 | 3d08ff69 | Blue Swirl | pflash_t *pfl = opaque; |
556 | 3d08ff69 | Blue Swirl | |
557 | 3d08ff69 | Blue Swirl | pflash_write(pfl, addr, value, 4, 0); |
558 | 3d08ff69 | Blue Swirl | } |
559 | 3d08ff69 | Blue Swirl | |
560 | cfe5f011 | Avi Kivity | static const MemoryRegionOps pflash_cfi01_ops_be = { |
561 | cfe5f011 | Avi Kivity | .old_mmio = { |
562 | cfe5f011 | Avi Kivity | .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, |
563 | cfe5f011 | Avi Kivity | .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, |
564 | cfe5f011 | Avi Kivity | }, |
565 | cfe5f011 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
566 | 05ee37eb | balrog | }; |
567 | 05ee37eb | balrog | |
568 | cfe5f011 | Avi Kivity | static const MemoryRegionOps pflash_cfi01_ops_le = { |
569 | cfe5f011 | Avi Kivity | .old_mmio = { |
570 | cfe5f011 | Avi Kivity | .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, |
571 | cfe5f011 | Avi Kivity | .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, |
572 | cfe5f011 | Avi Kivity | }, |
573 | cfe5f011 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
574 | 05ee37eb | balrog | }; |
575 | 05ee37eb | balrog | |
576 | e40b5f3e | Hu Tao | static void pflash_cfi01_realize(DeviceState *dev, Error **errp) |
577 | 05ee37eb | balrog | { |
578 | f1b44f0e | Hu Tao | pflash_t *pfl = CFI_PFLASH01(dev); |
579 | 368a354f | Peter Crosthwaite | uint64_t total_len; |
580 | d0e7605e | Vijay Kumar | int ret;
|
581 | 05ee37eb | balrog | |
582 | 368a354f | Peter Crosthwaite | total_len = pfl->sector_len * pfl->nb_blocs; |
583 | 05ee37eb | balrog | |
584 | 05ee37eb | balrog | /* XXX: to be fixed */
|
585 | c8b153d7 | ths | #if 0
|
586 | 05ee37eb | balrog | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
587 | 05ee37eb | balrog | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
588 | 05ee37eb | balrog | return NULL;
|
589 | c8b153d7 | ths | #endif
|
590 | 05ee37eb | balrog | |
591 | cfe5f011 | Avi Kivity | memory_region_init_rom_device( |
592 | 2d256e6f | Paolo Bonzini | &pfl->mem, OBJECT(dev), |
593 | 2c9b15ca | Paolo Bonzini | pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl, |
594 | 368a354f | Peter Crosthwaite | pfl->name, total_len); |
595 | 368a354f | Peter Crosthwaite | vmstate_register_ram(&pfl->mem, DEVICE(pfl)); |
596 | cfe5f011 | Avi Kivity | pfl->storage = memory_region_get_ram_ptr(&pfl->mem); |
597 | e40b5f3e | Hu Tao | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); |
598 | 05ee37eb | balrog | |
599 | 05ee37eb | balrog | if (pfl->bs) {
|
600 | 05ee37eb | balrog | /* read the initial flash content */
|
601 | d0e7605e | Vijay Kumar | ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
602 | 368a354f | Peter Crosthwaite | |
603 | d0e7605e | Vijay Kumar | if (ret < 0) { |
604 | 368a354f | Peter Crosthwaite | vmstate_unregister_ram(&pfl->mem, DEVICE(pfl)); |
605 | cfe5f011 | Avi Kivity | memory_region_destroy(&pfl->mem); |
606 | e40b5f3e | Hu Tao | error_setg(errp, "failed to read the initial flash content");
|
607 | e40b5f3e | Hu Tao | return;
|
608 | d0e7605e | Vijay Kumar | } |
609 | 05ee37eb | balrog | } |
610 | de8efe8f | Jordan Justen | |
611 | de8efe8f | Jordan Justen | if (pfl->bs) {
|
612 | de8efe8f | Jordan Justen | pfl->ro = bdrv_is_read_only(pfl->bs); |
613 | de8efe8f | Jordan Justen | } else {
|
614 | de8efe8f | Jordan Justen | pfl->ro = 0;
|
615 | de8efe8f | Jordan Justen | } |
616 | de8efe8f | Jordan Justen | |
617 | bc72ad67 | Alex Bligh | pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); |
618 | 05ee37eb | balrog | pfl->wcycle = 0;
|
619 | 05ee37eb | balrog | pfl->cmd = 0;
|
620 | 05ee37eb | balrog | pfl->status = 0;
|
621 | 05ee37eb | balrog | /* Hardcoded CFI table */
|
622 | 05ee37eb | balrog | pfl->cfi_len = 0x52;
|
623 | 05ee37eb | balrog | /* Standard "QRY" string */
|
624 | 05ee37eb | balrog | pfl->cfi_table[0x10] = 'Q'; |
625 | 05ee37eb | balrog | pfl->cfi_table[0x11] = 'R'; |
626 | 05ee37eb | balrog | pfl->cfi_table[0x12] = 'Y'; |
627 | 05ee37eb | balrog | /* Command set (Intel) */
|
628 | 05ee37eb | balrog | pfl->cfi_table[0x13] = 0x01; |
629 | 05ee37eb | balrog | pfl->cfi_table[0x14] = 0x00; |
630 | 05ee37eb | balrog | /* Primary extended table address (none) */
|
631 | 05ee37eb | balrog | pfl->cfi_table[0x15] = 0x31; |
632 | 05ee37eb | balrog | pfl->cfi_table[0x16] = 0x00; |
633 | 05ee37eb | balrog | /* Alternate command set (none) */
|
634 | 05ee37eb | balrog | pfl->cfi_table[0x17] = 0x00; |
635 | 05ee37eb | balrog | pfl->cfi_table[0x18] = 0x00; |
636 | 05ee37eb | balrog | /* Alternate extended table (none) */
|
637 | 05ee37eb | balrog | pfl->cfi_table[0x19] = 0x00; |
638 | 05ee37eb | balrog | pfl->cfi_table[0x1A] = 0x00; |
639 | 05ee37eb | balrog | /* Vcc min */
|
640 | 05ee37eb | balrog | pfl->cfi_table[0x1B] = 0x45; |
641 | 05ee37eb | balrog | /* Vcc max */
|
642 | 05ee37eb | balrog | pfl->cfi_table[0x1C] = 0x55; |
643 | 05ee37eb | balrog | /* Vpp min (no Vpp pin) */
|
644 | 05ee37eb | balrog | pfl->cfi_table[0x1D] = 0x00; |
645 | 05ee37eb | balrog | /* Vpp max (no Vpp pin) */
|
646 | 05ee37eb | balrog | pfl->cfi_table[0x1E] = 0x00; |
647 | 05ee37eb | balrog | /* Reserved */
|
648 | 05ee37eb | balrog | pfl->cfi_table[0x1F] = 0x07; |
649 | 05ee37eb | balrog | /* Timeout for min size buffer write */
|
650 | 05ee37eb | balrog | pfl->cfi_table[0x20] = 0x07; |
651 | 05ee37eb | balrog | /* Typical timeout for block erase */
|
652 | 05ee37eb | balrog | pfl->cfi_table[0x21] = 0x0a; |
653 | 05ee37eb | balrog | /* Typical timeout for full chip erase (4096 ms) */
|
654 | 05ee37eb | balrog | pfl->cfi_table[0x22] = 0x00; |
655 | 05ee37eb | balrog | /* Reserved */
|
656 | 05ee37eb | balrog | pfl->cfi_table[0x23] = 0x04; |
657 | 05ee37eb | balrog | /* Max timeout for buffer write */
|
658 | 05ee37eb | balrog | pfl->cfi_table[0x24] = 0x04; |
659 | 05ee37eb | balrog | /* Max timeout for block erase */
|
660 | 05ee37eb | balrog | pfl->cfi_table[0x25] = 0x04; |
661 | 05ee37eb | balrog | /* Max timeout for chip erase */
|
662 | 05ee37eb | balrog | pfl->cfi_table[0x26] = 0x00; |
663 | 05ee37eb | balrog | /* Device size */
|
664 | 05ee37eb | balrog | pfl->cfi_table[0x27] = ctz32(total_len); // + 1; |
665 | 05ee37eb | balrog | /* Flash device interface (8 & 16 bits) */
|
666 | 05ee37eb | balrog | pfl->cfi_table[0x28] = 0x02; |
667 | 05ee37eb | balrog | pfl->cfi_table[0x29] = 0x00; |
668 | 05ee37eb | balrog | /* Max number of bytes in multi-bytes write */
|
669 | 4b6fedca | Roy Franz | if (pfl->bank_width == 1) { |
670 | 4737fa26 | Edgar E. Iglesias | pfl->cfi_table[0x2A] = 0x08; |
671 | 4737fa26 | Edgar E. Iglesias | } else {
|
672 | 4737fa26 | Edgar E. Iglesias | pfl->cfi_table[0x2A] = 0x0B; |
673 | 4737fa26 | Edgar E. Iglesias | } |
674 | b4bf0a9a | Edgar E. Iglesias | pfl->writeblock_size = 1 << pfl->cfi_table[0x2A]; |
675 | b4bf0a9a | Edgar E. Iglesias | |
676 | 05ee37eb | balrog | pfl->cfi_table[0x2B] = 0x00; |
677 | 05ee37eb | balrog | /* Number of erase block regions (uniform) */
|
678 | 05ee37eb | balrog | pfl->cfi_table[0x2C] = 0x01; |
679 | 05ee37eb | balrog | /* Erase block region 1 */
|
680 | 368a354f | Peter Crosthwaite | pfl->cfi_table[0x2D] = pfl->nb_blocs - 1; |
681 | 368a354f | Peter Crosthwaite | pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8; |
682 | 368a354f | Peter Crosthwaite | pfl->cfi_table[0x2F] = pfl->sector_len >> 8; |
683 | 368a354f | Peter Crosthwaite | pfl->cfi_table[0x30] = pfl->sector_len >> 16; |
684 | 05ee37eb | balrog | |
685 | 05ee37eb | balrog | /* Extended */
|
686 | 05ee37eb | balrog | pfl->cfi_table[0x31] = 'P'; |
687 | 05ee37eb | balrog | pfl->cfi_table[0x32] = 'R'; |
688 | 05ee37eb | balrog | pfl->cfi_table[0x33] = 'I'; |
689 | 05ee37eb | balrog | |
690 | 05ee37eb | balrog | pfl->cfi_table[0x34] = '1'; |
691 | 262e1eaa | Aurelien Jarno | pfl->cfi_table[0x35] = '0'; |
692 | 05ee37eb | balrog | |
693 | 05ee37eb | balrog | pfl->cfi_table[0x36] = 0x00; |
694 | 05ee37eb | balrog | pfl->cfi_table[0x37] = 0x00; |
695 | 05ee37eb | balrog | pfl->cfi_table[0x38] = 0x00; |
696 | 05ee37eb | balrog | pfl->cfi_table[0x39] = 0x00; |
697 | 05ee37eb | balrog | |
698 | 05ee37eb | balrog | pfl->cfi_table[0x3a] = 0x00; |
699 | 05ee37eb | balrog | |
700 | 05ee37eb | balrog | pfl->cfi_table[0x3b] = 0x00; |
701 | 05ee37eb | balrog | pfl->cfi_table[0x3c] = 0x00; |
702 | 05ee37eb | balrog | |
703 | 262e1eaa | Aurelien Jarno | pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */ |
704 | 368a354f | Peter Crosthwaite | } |
705 | 368a354f | Peter Crosthwaite | |
706 | 368a354f | Peter Crosthwaite | static Property pflash_cfi01_properties[] = {
|
707 | 368a354f | Peter Crosthwaite | DEFINE_PROP_DRIVE("drive", struct pflash_t, bs), |
708 | 368a354f | Peter Crosthwaite | DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), |
709 | 368a354f | Peter Crosthwaite | DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0), |
710 | 4b6fedca | Roy Franz | DEFINE_PROP_UINT8("width", struct pflash_t, bank_width, 0), |
711 | 368a354f | Peter Crosthwaite | DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0), |
712 | 368a354f | Peter Crosthwaite | DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), |
713 | 368a354f | Peter Crosthwaite | DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0), |
714 | 368a354f | Peter Crosthwaite | DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0), |
715 | 368a354f | Peter Crosthwaite | DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0), |
716 | 368a354f | Peter Crosthwaite | DEFINE_PROP_STRING("name", struct pflash_t, name), |
717 | 368a354f | Peter Crosthwaite | DEFINE_PROP_END_OF_LIST(), |
718 | 368a354f | Peter Crosthwaite | }; |
719 | 368a354f | Peter Crosthwaite | |
720 | 368a354f | Peter Crosthwaite | static void pflash_cfi01_class_init(ObjectClass *klass, void *data) |
721 | 368a354f | Peter Crosthwaite | { |
722 | 368a354f | Peter Crosthwaite | DeviceClass *dc = DEVICE_CLASS(klass); |
723 | 368a354f | Peter Crosthwaite | |
724 | e40b5f3e | Hu Tao | dc->realize = pflash_cfi01_realize; |
725 | 368a354f | Peter Crosthwaite | dc->props = pflash_cfi01_properties; |
726 | d8d24fb7 | Peter Maydell | dc->vmsd = &vmstate_pflash; |
727 | 125ee0ed | Marcel Apfelbaum | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
728 | 368a354f | Peter Crosthwaite | } |
729 | 368a354f | Peter Crosthwaite | |
730 | 368a354f | Peter Crosthwaite | |
731 | 368a354f | Peter Crosthwaite | static const TypeInfo pflash_cfi01_info = { |
732 | f1b44f0e | Hu Tao | .name = TYPE_CFI_PFLASH01, |
733 | 368a354f | Peter Crosthwaite | .parent = TYPE_SYS_BUS_DEVICE, |
734 | 368a354f | Peter Crosthwaite | .instance_size = sizeof(struct pflash_t), |
735 | 368a354f | Peter Crosthwaite | .class_init = pflash_cfi01_class_init, |
736 | 368a354f | Peter Crosthwaite | }; |
737 | 368a354f | Peter Crosthwaite | |
738 | 368a354f | Peter Crosthwaite | static void pflash_cfi01_register_types(void) |
739 | 368a354f | Peter Crosthwaite | { |
740 | 368a354f | Peter Crosthwaite | type_register_static(&pflash_cfi01_info); |
741 | 368a354f | Peter Crosthwaite | } |
742 | 368a354f | Peter Crosthwaite | |
743 | 368a354f | Peter Crosthwaite | type_init(pflash_cfi01_register_types) |
744 | 368a354f | Peter Crosthwaite | |
745 | 368a354f | Peter Crosthwaite | pflash_t *pflash_cfi01_register(hwaddr base, |
746 | 368a354f | Peter Crosthwaite | DeviceState *qdev, const char *name, |
747 | 368a354f | Peter Crosthwaite | hwaddr size, |
748 | 368a354f | Peter Crosthwaite | BlockDriverState *bs, |
749 | 4b6fedca | Roy Franz | uint32_t sector_len, int nb_blocs,
|
750 | 4b6fedca | Roy Franz | int bank_width, uint16_t id0, uint16_t id1,
|
751 | 368a354f | Peter Crosthwaite | uint16_t id2, uint16_t id3, int be)
|
752 | 368a354f | Peter Crosthwaite | { |
753 | f1b44f0e | Hu Tao | DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH01);
|
754 | 368a354f | Peter Crosthwaite | |
755 | 368a354f | Peter Crosthwaite | if (bs && qdev_prop_set_drive(dev, "drive", bs)) { |
756 | 368a354f | Peter Crosthwaite | abort(); |
757 | 368a354f | Peter Crosthwaite | } |
758 | 368a354f | Peter Crosthwaite | qdev_prop_set_uint32(dev, "num-blocks", nb_blocs);
|
759 | 368a354f | Peter Crosthwaite | qdev_prop_set_uint64(dev, "sector-length", sector_len);
|
760 | 4b6fedca | Roy Franz | qdev_prop_set_uint8(dev, "width", bank_width);
|
761 | 368a354f | Peter Crosthwaite | qdev_prop_set_uint8(dev, "big-endian", !!be);
|
762 | 368a354f | Peter Crosthwaite | qdev_prop_set_uint16(dev, "id0", id0);
|
763 | 368a354f | Peter Crosthwaite | qdev_prop_set_uint16(dev, "id1", id1);
|
764 | 368a354f | Peter Crosthwaite | qdev_prop_set_uint16(dev, "id2", id2);
|
765 | 368a354f | Peter Crosthwaite | qdev_prop_set_uint16(dev, "id3", id3);
|
766 | 368a354f | Peter Crosthwaite | qdev_prop_set_string(dev, "name", name);
|
767 | 368a354f | Peter Crosthwaite | qdev_init_nofail(dev); |
768 | 368a354f | Peter Crosthwaite | |
769 | f1b44f0e | Hu Tao | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
|
770 | f1b44f0e | Hu Tao | return CFI_PFLASH01(dev);
|
771 | 05ee37eb | balrog | } |
772 | cfe5f011 | Avi Kivity | |
773 | cfe5f011 | Avi Kivity | MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl) |
774 | cfe5f011 | Avi Kivity | { |
775 | cfe5f011 | Avi Kivity | return &fl->mem;
|
776 | cfe5f011 | Avi Kivity | } |