root / hw / arm_gic.c @ 4b8f1c88
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1 | 5fafdf24 | ths | /*
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2 | 9ee6e8bb | pbrook | * ARM Generic/Distributed Interrupt Controller
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3 | e69954b9 | pbrook | *
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4 | 9ee6e8bb | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | e69954b9 | pbrook | * Written by Paul Brook
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6 | e69954b9 | pbrook | *
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7 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
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8 | e69954b9 | pbrook | */
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9 | e69954b9 | pbrook | |
10 | 9ee6e8bb | pbrook | /* This file contains implementation code for the RealView EB interrupt
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11 | 9ee6e8bb | pbrook | controller, MPCore distributed interrupt controller and ARMv7-M
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12 | 9ee6e8bb | pbrook | Nested Vectored Interrupt Controller. */
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13 | e69954b9 | pbrook | |
14 | a32134aa | Mark Langsdorf | /* Maximum number of possible interrupts, determined by the GIC architecture */
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15 | a32134aa | Mark Langsdorf | #define GIC_MAXIRQ 1020 |
16 | 69253800 | Rusty Russell | /* First 32 are private to each CPU (SGIs and PPIs). */
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17 | 69253800 | Rusty Russell | #define GIC_INTERNAL 32 |
18 | e69954b9 | pbrook | //#define DEBUG_GIC
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19 | e69954b9 | pbrook | |
20 | e69954b9 | pbrook | #ifdef DEBUG_GIC
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21 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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22 | 001faf32 | Blue Swirl | do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0) |
23 | e69954b9 | pbrook | #else
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24 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do {} while(0) |
25 | e69954b9 | pbrook | #endif
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26 | e69954b9 | pbrook | |
27 | 9ee6e8bb | pbrook | #ifdef NVIC
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28 | 9ee6e8bb | pbrook | static const uint8_t gic_id[] = |
29 | 9ee6e8bb | pbrook | { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 }; |
30 | 9ee6e8bb | pbrook | /* The NVIC has 16 internal vectors. However these are not exposed
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31 | 9ee6e8bb | pbrook | through the normal GIC interface. */
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32 | 9ee6e8bb | pbrook | #define GIC_BASE_IRQ 32 |
33 | 9ee6e8bb | pbrook | #else
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34 | e69954b9 | pbrook | static const uint8_t gic_id[] = |
35 | e69954b9 | pbrook | { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
36 | 9ee6e8bb | pbrook | #define GIC_BASE_IRQ 0 |
37 | 9ee6e8bb | pbrook | #endif
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38 | e69954b9 | pbrook | |
39 | fe7e8758 | Paul Brook | #define FROM_SYSBUSGIC(type, dev) \
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40 | fe7e8758 | Paul Brook | DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev)) |
41 | fe7e8758 | Paul Brook | |
42 | e69954b9 | pbrook | typedef struct gic_irq_state |
43 | e69954b9 | pbrook | { |
44 | 41bf234d | Rabin Vincent | /* The enable bits are only banked for per-cpu interrupts. */
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45 | 41bf234d | Rabin Vincent | unsigned enabled:NCPU;
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46 | 9ee6e8bb | pbrook | unsigned pending:NCPU;
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47 | 9ee6e8bb | pbrook | unsigned active:NCPU;
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48 | a45db6c6 | aurel32 | unsigned level:NCPU;
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49 | 9ee6e8bb | pbrook | unsigned model:1; /* 0 = N:N, 1 = 1:N */ |
50 | e69954b9 | pbrook | unsigned trigger:1; /* nonzero = edge triggered. */ |
51 | e69954b9 | pbrook | } gic_irq_state; |
52 | e69954b9 | pbrook | |
53 | 9ee6e8bb | pbrook | #define ALL_CPU_MASK ((1 << NCPU) - 1) |
54 | c988bfad | Paul Brook | #if NCPU > 1 |
55 | c988bfad | Paul Brook | #define NUM_CPU(s) ((s)->num_cpu)
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56 | c988bfad | Paul Brook | #else
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57 | c988bfad | Paul Brook | #define NUM_CPU(s) 1 |
58 | c988bfad | Paul Brook | #endif
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59 | 9ee6e8bb | pbrook | |
60 | 41bf234d | Rabin Vincent | #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
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61 | 41bf234d | Rabin Vincent | #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
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62 | 41bf234d | Rabin Vincent | #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0) |
63 | 9ee6e8bb | pbrook | #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
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64 | 9ee6e8bb | pbrook | #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
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65 | 9ee6e8bb | pbrook | #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0) |
66 | 9ee6e8bb | pbrook | #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
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67 | 9ee6e8bb | pbrook | #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
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68 | 9ee6e8bb | pbrook | #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) |
69 | e69954b9 | pbrook | #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 |
70 | e69954b9 | pbrook | #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 |
71 | e69954b9 | pbrook | #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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72 | 9ee6e8bb | pbrook | #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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73 | 9ee6e8bb | pbrook | #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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74 | 57d69a91 | balrog | #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) |
75 | e69954b9 | pbrook | #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 |
76 | e69954b9 | pbrook | #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 |
77 | e69954b9 | pbrook | #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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78 | 69253800 | Rusty Russell | #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
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79 | 69253800 | Rusty Russell | s->priority1[irq][cpu] : \ |
80 | 69253800 | Rusty Russell | s->priority2[(irq) - GIC_INTERNAL]) |
81 | 9ee6e8bb | pbrook | #ifdef NVIC
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82 | 9ee6e8bb | pbrook | #define GIC_TARGET(irq) 1 |
83 | 9ee6e8bb | pbrook | #else
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84 | 9ee6e8bb | pbrook | #define GIC_TARGET(irq) s->irq_target[irq]
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85 | 9ee6e8bb | pbrook | #endif
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86 | e69954b9 | pbrook | |
87 | e69954b9 | pbrook | typedef struct gic_state |
88 | e69954b9 | pbrook | { |
89 | fe7e8758 | Paul Brook | SysBusDevice busdev; |
90 | 9ee6e8bb | pbrook | qemu_irq parent_irq[NCPU]; |
91 | e69954b9 | pbrook | int enabled;
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92 | 9ee6e8bb | pbrook | int cpu_enabled[NCPU];
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93 | e69954b9 | pbrook | |
94 | a32134aa | Mark Langsdorf | gic_irq_state irq_state[GIC_MAXIRQ]; |
95 | 9ee6e8bb | pbrook | #ifndef NVIC
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96 | a32134aa | Mark Langsdorf | int irq_target[GIC_MAXIRQ];
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97 | 9ee6e8bb | pbrook | #endif
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98 | 69253800 | Rusty Russell | int priority1[GIC_INTERNAL][NCPU];
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99 | 69253800 | Rusty Russell | int priority2[GIC_MAXIRQ - GIC_INTERNAL];
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100 | a32134aa | Mark Langsdorf | int last_active[GIC_MAXIRQ][NCPU];
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101 | 9ee6e8bb | pbrook | |
102 | 9ee6e8bb | pbrook | int priority_mask[NCPU];
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103 | 9ee6e8bb | pbrook | int running_irq[NCPU];
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104 | 9ee6e8bb | pbrook | int running_priority[NCPU];
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105 | 9ee6e8bb | pbrook | int current_pending[NCPU];
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106 | 9ee6e8bb | pbrook | |
107 | c988bfad | Paul Brook | #if NCPU > 1 |
108 | c988bfad | Paul Brook | int num_cpu;
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109 | c988bfad | Paul Brook | #endif
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110 | c988bfad | Paul Brook | |
111 | e2c56465 | Peter Maydell | MemoryRegion iomem; /* Distributor */
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112 | e2c56465 | Peter Maydell | #ifndef NVIC
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113 | e2c56465 | Peter Maydell | /* This is just so we can have an opaque pointer which identifies
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114 | e2c56465 | Peter Maydell | * both this GIC and which CPU interface we should be accessing.
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115 | e2c56465 | Peter Maydell | */
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116 | e2c56465 | Peter Maydell | struct gic_state *backref[NCPU];
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117 | e2c56465 | Peter Maydell | MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */ |
118 | e2c56465 | Peter Maydell | #endif
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119 | a32134aa | Mark Langsdorf | uint32_t num_irq; |
120 | e69954b9 | pbrook | } gic_state; |
121 | e69954b9 | pbrook | |
122 | e69954b9 | pbrook | /* TODO: Many places that call this routine could be optimized. */
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123 | e69954b9 | pbrook | /* Update interrupt status after enabled or pending bits have been changed. */
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124 | e69954b9 | pbrook | static void gic_update(gic_state *s) |
125 | e69954b9 | pbrook | { |
126 | e69954b9 | pbrook | int best_irq;
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127 | e69954b9 | pbrook | int best_prio;
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128 | e69954b9 | pbrook | int irq;
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129 | 9ee6e8bb | pbrook | int level;
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130 | 9ee6e8bb | pbrook | int cpu;
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131 | 9ee6e8bb | pbrook | int cm;
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132 | 9ee6e8bb | pbrook | |
133 | c988bfad | Paul Brook | for (cpu = 0; cpu < NUM_CPU(s); cpu++) { |
134 | 9ee6e8bb | pbrook | cm = 1 << cpu;
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135 | 9ee6e8bb | pbrook | s->current_pending[cpu] = 1023;
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136 | 9ee6e8bb | pbrook | if (!s->enabled || !s->cpu_enabled[cpu]) {
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137 | 9ee6e8bb | pbrook | qemu_irq_lower(s->parent_irq[cpu]); |
138 | 9ee6e8bb | pbrook | return;
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139 | 9ee6e8bb | pbrook | } |
140 | 9ee6e8bb | pbrook | best_prio = 0x100;
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141 | 9ee6e8bb | pbrook | best_irq = 1023;
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142 | a32134aa | Mark Langsdorf | for (irq = 0; irq < s->num_irq; irq++) { |
143 | 41bf234d | Rabin Vincent | if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) {
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144 | 9ee6e8bb | pbrook | if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
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145 | 9ee6e8bb | pbrook | best_prio = GIC_GET_PRIORITY(irq, cpu); |
146 | 9ee6e8bb | pbrook | best_irq = irq; |
147 | 9ee6e8bb | pbrook | } |
148 | e69954b9 | pbrook | } |
149 | e69954b9 | pbrook | } |
150 | 9ee6e8bb | pbrook | level = 0;
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151 | 9ee6e8bb | pbrook | if (best_prio <= s->priority_mask[cpu]) {
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152 | 9ee6e8bb | pbrook | s->current_pending[cpu] = best_irq; |
153 | 9ee6e8bb | pbrook | if (best_prio < s->running_priority[cpu]) {
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154 | 9ee6e8bb | pbrook | DPRINTF("Raised pending IRQ %d\n", best_irq);
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155 | 9ee6e8bb | pbrook | level = 1;
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156 | 9ee6e8bb | pbrook | } |
157 | e69954b9 | pbrook | } |
158 | 9ee6e8bb | pbrook | qemu_set_irq(s->parent_irq[cpu], level); |
159 | e69954b9 | pbrook | } |
160 | e69954b9 | pbrook | } |
161 | e69954b9 | pbrook | |
162 | 9ee6e8bb | pbrook | static void __attribute__((unused)) |
163 | 9ee6e8bb | pbrook | gic_set_pending_private(gic_state *s, int cpu, int irq) |
164 | 9ee6e8bb | pbrook | { |
165 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
166 | 9ee6e8bb | pbrook | |
167 | 9ee6e8bb | pbrook | if (GIC_TEST_PENDING(irq, cm))
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168 | 9ee6e8bb | pbrook | return;
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169 | 9ee6e8bb | pbrook | |
170 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending cpu %d\n", irq, cpu);
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171 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, cm); |
172 | 9ee6e8bb | pbrook | gic_update(s); |
173 | 9ee6e8bb | pbrook | } |
174 | 9ee6e8bb | pbrook | |
175 | 9ee6e8bb | pbrook | /* Process a change in an external IRQ input. */
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176 | e69954b9 | pbrook | static void gic_set_irq(void *opaque, int irq, int level) |
177 | e69954b9 | pbrook | { |
178 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
179 | e69954b9 | pbrook | /* The first external input line is internal interrupt 32. */
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180 | 69253800 | Rusty Russell | irq += GIC_INTERNAL; |
181 | 9ee6e8bb | pbrook | if (level == GIC_TEST_LEVEL(irq, ALL_CPU_MASK))
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182 | e69954b9 | pbrook | return;
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183 | e69954b9 | pbrook | |
184 | e69954b9 | pbrook | if (level) {
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185 | 9ee6e8bb | pbrook | GIC_SET_LEVEL(irq, ALL_CPU_MASK); |
186 | 41bf234d | Rabin Vincent | if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, ALL_CPU_MASK)) {
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187 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq, GIC_TARGET(irq));
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188 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, GIC_TARGET(irq)); |
189 | e69954b9 | pbrook | } |
190 | e69954b9 | pbrook | } else {
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191 | 9ee6e8bb | pbrook | GIC_CLEAR_LEVEL(irq, ALL_CPU_MASK); |
192 | e69954b9 | pbrook | } |
193 | e69954b9 | pbrook | gic_update(s); |
194 | e69954b9 | pbrook | } |
195 | e69954b9 | pbrook | |
196 | 9ee6e8bb | pbrook | static void gic_set_running_irq(gic_state *s, int cpu, int irq) |
197 | e69954b9 | pbrook | { |
198 | 9ee6e8bb | pbrook | s->running_irq[cpu] = irq; |
199 | 9ee6e8bb | pbrook | if (irq == 1023) { |
200 | 9ee6e8bb | pbrook | s->running_priority[cpu] = 0x100;
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201 | 9ee6e8bb | pbrook | } else {
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202 | 9ee6e8bb | pbrook | s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); |
203 | 9ee6e8bb | pbrook | } |
204 | e69954b9 | pbrook | gic_update(s); |
205 | e69954b9 | pbrook | } |
206 | e69954b9 | pbrook | |
207 | 9ee6e8bb | pbrook | static uint32_t gic_acknowledge_irq(gic_state *s, int cpu) |
208 | e69954b9 | pbrook | { |
209 | e69954b9 | pbrook | int new_irq;
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210 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
211 | 9ee6e8bb | pbrook | new_irq = s->current_pending[cpu]; |
212 | 9ee6e8bb | pbrook | if (new_irq == 1023 |
213 | 9ee6e8bb | pbrook | || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) { |
214 | e69954b9 | pbrook | DPRINTF("ACK no pending IRQ\n");
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215 | e69954b9 | pbrook | return 1023; |
216 | e69954b9 | pbrook | } |
217 | 9ee6e8bb | pbrook | s->last_active[new_irq][cpu] = s->running_irq[cpu]; |
218 | 9ee6e8bb | pbrook | /* Clear pending flags for both level and edge triggered interrupts.
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219 | 9ee6e8bb | pbrook | Level triggered IRQs will be reasserted once they become inactive. */
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220 | 9ee6e8bb | pbrook | GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm); |
221 | 9ee6e8bb | pbrook | gic_set_running_irq(s, cpu, new_irq); |
222 | e69954b9 | pbrook | DPRINTF("ACK %d\n", new_irq);
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223 | e69954b9 | pbrook | return new_irq;
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224 | e69954b9 | pbrook | } |
225 | e69954b9 | pbrook | |
226 | 9ee6e8bb | pbrook | static void gic_complete_irq(gic_state * s, int cpu, int irq) |
227 | e69954b9 | pbrook | { |
228 | e69954b9 | pbrook | int update = 0; |
229 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
230 | df628ff1 | pbrook | DPRINTF("EOI %d\n", irq);
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231 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq) {
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232 | 217bfb44 | Peter Maydell | /* This handles two cases:
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233 | 217bfb44 | Peter Maydell | * 1. If software writes the ID of a spurious interrupt [ie 1023]
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234 | 217bfb44 | Peter Maydell | * to the GICC_EOIR, the GIC ignores that write.
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235 | 217bfb44 | Peter Maydell | * 2. If software writes the number of a non-existent interrupt
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236 | 217bfb44 | Peter Maydell | * this must be a subcase of "value written does not match the last
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237 | 217bfb44 | Peter Maydell | * valid interrupt value read from the Interrupt Acknowledge
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238 | 217bfb44 | Peter Maydell | * register" and so this is UNPREDICTABLE. We choose to ignore it.
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239 | 217bfb44 | Peter Maydell | */
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240 | 217bfb44 | Peter Maydell | return;
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241 | 217bfb44 | Peter Maydell | } |
242 | 9ee6e8bb | pbrook | if (s->running_irq[cpu] == 1023) |
243 | e69954b9 | pbrook | return; /* No active IRQ. */ |
244 | 217bfb44 | Peter Maydell | /* Mark level triggered interrupts as pending if they are still
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245 | 217bfb44 | Peter Maydell | raised. */
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246 | 217bfb44 | Peter Maydell | if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
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247 | 217bfb44 | Peter Maydell | && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
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248 | 217bfb44 | Peter Maydell | DPRINTF("Set %d pending mask %x\n", irq, cm);
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249 | 217bfb44 | Peter Maydell | GIC_SET_PENDING(irq, cm); |
250 | 217bfb44 | Peter Maydell | update = 1;
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251 | e69954b9 | pbrook | } |
252 | 9ee6e8bb | pbrook | if (irq != s->running_irq[cpu]) {
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253 | e69954b9 | pbrook | /* Complete an IRQ that is not currently running. */
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254 | 9ee6e8bb | pbrook | int tmp = s->running_irq[cpu];
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255 | 9ee6e8bb | pbrook | while (s->last_active[tmp][cpu] != 1023) { |
256 | 9ee6e8bb | pbrook | if (s->last_active[tmp][cpu] == irq) {
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257 | 9ee6e8bb | pbrook | s->last_active[tmp][cpu] = s->last_active[irq][cpu]; |
258 | e69954b9 | pbrook | break;
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259 | e69954b9 | pbrook | } |
260 | 9ee6e8bb | pbrook | tmp = s->last_active[tmp][cpu]; |
261 | e69954b9 | pbrook | } |
262 | e69954b9 | pbrook | if (update) {
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263 | e69954b9 | pbrook | gic_update(s); |
264 | e69954b9 | pbrook | } |
265 | e69954b9 | pbrook | } else {
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266 | e69954b9 | pbrook | /* Complete the current running IRQ. */
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267 | 9ee6e8bb | pbrook | gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); |
268 | e69954b9 | pbrook | } |
269 | e69954b9 | pbrook | } |
270 | e69954b9 | pbrook | |
271 | c227f099 | Anthony Liguori | static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) |
272 | e69954b9 | pbrook | { |
273 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
274 | e69954b9 | pbrook | uint32_t res; |
275 | e69954b9 | pbrook | int irq;
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276 | e69954b9 | pbrook | int i;
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277 | 9ee6e8bb | pbrook | int cpu;
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278 | 9ee6e8bb | pbrook | int cm;
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279 | 9ee6e8bb | pbrook | int mask;
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280 | e69954b9 | pbrook | |
281 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
282 | 9ee6e8bb | pbrook | cm = 1 << cpu;
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283 | e69954b9 | pbrook | if (offset < 0x100) { |
284 | 9ee6e8bb | pbrook | #ifndef NVIC
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285 | e69954b9 | pbrook | if (offset == 0) |
286 | e69954b9 | pbrook | return s->enabled;
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287 | e69954b9 | pbrook | if (offset == 4) |
288 | a32134aa | Mark Langsdorf | return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); |
289 | e69954b9 | pbrook | if (offset < 0x08) |
290 | e69954b9 | pbrook | return 0; |
291 | b79f2265 | Rob Herring | if (offset >= 0x80) { |
292 | b79f2265 | Rob Herring | /* Interrupt Security , RAZ/WI */
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293 | b79f2265 | Rob Herring | return 0; |
294 | b79f2265 | Rob Herring | } |
295 | 9ee6e8bb | pbrook | #endif
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296 | e69954b9 | pbrook | goto bad_reg;
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297 | e69954b9 | pbrook | } else if (offset < 0x200) { |
298 | e69954b9 | pbrook | /* Interrupt Set/Clear Enable. */
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299 | e69954b9 | pbrook | if (offset < 0x180) |
300 | e69954b9 | pbrook | irq = (offset - 0x100) * 8; |
301 | e69954b9 | pbrook | else
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302 | e69954b9 | pbrook | irq = (offset - 0x180) * 8; |
303 | 9ee6e8bb | pbrook | irq += GIC_BASE_IRQ; |
304 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
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305 | e69954b9 | pbrook | goto bad_reg;
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306 | e69954b9 | pbrook | res = 0;
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307 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
308 | 41bf234d | Rabin Vincent | if (GIC_TEST_ENABLED(irq + i, cm)) {
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309 | e69954b9 | pbrook | res |= (1 << i);
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310 | e69954b9 | pbrook | } |
311 | e69954b9 | pbrook | } |
312 | e69954b9 | pbrook | } else if (offset < 0x300) { |
313 | e69954b9 | pbrook | /* Interrupt Set/Clear Pending. */
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314 | e69954b9 | pbrook | if (offset < 0x280) |
315 | e69954b9 | pbrook | irq = (offset - 0x200) * 8; |
316 | e69954b9 | pbrook | else
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317 | e69954b9 | pbrook | irq = (offset - 0x280) * 8; |
318 | 9ee6e8bb | pbrook | irq += GIC_BASE_IRQ; |
319 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
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320 | e69954b9 | pbrook | goto bad_reg;
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321 | e69954b9 | pbrook | res = 0;
|
322 | 69253800 | Rusty Russell | mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
323 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
324 | 9ee6e8bb | pbrook | if (GIC_TEST_PENDING(irq + i, mask)) {
|
325 | e69954b9 | pbrook | res |= (1 << i);
|
326 | e69954b9 | pbrook | } |
327 | e69954b9 | pbrook | } |
328 | e69954b9 | pbrook | } else if (offset < 0x400) { |
329 | e69954b9 | pbrook | /* Interrupt Active. */
|
330 | 9ee6e8bb | pbrook | irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; |
331 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
332 | e69954b9 | pbrook | goto bad_reg;
|
333 | e69954b9 | pbrook | res = 0;
|
334 | 69253800 | Rusty Russell | mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
335 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
336 | 9ee6e8bb | pbrook | if (GIC_TEST_ACTIVE(irq + i, mask)) {
|
337 | e69954b9 | pbrook | res |= (1 << i);
|
338 | e69954b9 | pbrook | } |
339 | e69954b9 | pbrook | } |
340 | e69954b9 | pbrook | } else if (offset < 0x800) { |
341 | e69954b9 | pbrook | /* Interrupt Priority. */
|
342 | 9ee6e8bb | pbrook | irq = (offset - 0x400) + GIC_BASE_IRQ;
|
343 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
344 | e69954b9 | pbrook | goto bad_reg;
|
345 | 9ee6e8bb | pbrook | res = GIC_GET_PRIORITY(irq, cpu); |
346 | 9ee6e8bb | pbrook | #ifndef NVIC
|
347 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
348 | e69954b9 | pbrook | /* Interrupt CPU Target. */
|
349 | 9ee6e8bb | pbrook | irq = (offset - 0x800) + GIC_BASE_IRQ;
|
350 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
351 | e69954b9 | pbrook | goto bad_reg;
|
352 | 9ee6e8bb | pbrook | if (irq >= 29 && irq <= 31) { |
353 | 9ee6e8bb | pbrook | res = cm; |
354 | 9ee6e8bb | pbrook | } else {
|
355 | 9ee6e8bb | pbrook | res = GIC_TARGET(irq); |
356 | 9ee6e8bb | pbrook | } |
357 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
358 | e69954b9 | pbrook | /* Interrupt Configuration. */
|
359 | 9ee6e8bb | pbrook | irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; |
360 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
361 | e69954b9 | pbrook | goto bad_reg;
|
362 | e69954b9 | pbrook | res = 0;
|
363 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
364 | e69954b9 | pbrook | if (GIC_TEST_MODEL(irq + i))
|
365 | e69954b9 | pbrook | res |= (1 << (i * 2)); |
366 | e69954b9 | pbrook | if (GIC_TEST_TRIGGER(irq + i))
|
367 | e69954b9 | pbrook | res |= (2 << (i * 2)); |
368 | e69954b9 | pbrook | } |
369 | 9ee6e8bb | pbrook | #endif
|
370 | e69954b9 | pbrook | } else if (offset < 0xfe0) { |
371 | e69954b9 | pbrook | goto bad_reg;
|
372 | e69954b9 | pbrook | } else /* offset >= 0xfe0 */ { |
373 | e69954b9 | pbrook | if (offset & 3) { |
374 | e69954b9 | pbrook | res = 0;
|
375 | e69954b9 | pbrook | } else {
|
376 | e69954b9 | pbrook | res = gic_id[(offset - 0xfe0) >> 2]; |
377 | e69954b9 | pbrook | } |
378 | e69954b9 | pbrook | } |
379 | e69954b9 | pbrook | return res;
|
380 | e69954b9 | pbrook | bad_reg:
|
381 | 2ac71179 | Paul Brook | hw_error("gic_dist_readb: Bad offset %x\n", (int)offset); |
382 | e69954b9 | pbrook | return 0; |
383 | e69954b9 | pbrook | } |
384 | e69954b9 | pbrook | |
385 | c227f099 | Anthony Liguori | static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset) |
386 | e69954b9 | pbrook | { |
387 | e69954b9 | pbrook | uint32_t val; |
388 | e69954b9 | pbrook | val = gic_dist_readb(opaque, offset); |
389 | e69954b9 | pbrook | val |= gic_dist_readb(opaque, offset + 1) << 8; |
390 | e69954b9 | pbrook | return val;
|
391 | e69954b9 | pbrook | } |
392 | e69954b9 | pbrook | |
393 | c227f099 | Anthony Liguori | static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) |
394 | e69954b9 | pbrook | { |
395 | e69954b9 | pbrook | uint32_t val; |
396 | 9ee6e8bb | pbrook | #ifdef NVIC
|
397 | 9ee6e8bb | pbrook | gic_state *s = (gic_state *)opaque; |
398 | 9ee6e8bb | pbrook | uint32_t addr; |
399 | 8da3ff18 | pbrook | addr = offset; |
400 | 9ee6e8bb | pbrook | if (addr < 0x100 || addr > 0xd00) |
401 | fe7e8758 | Paul Brook | return nvic_readl(s, addr);
|
402 | 9ee6e8bb | pbrook | #endif
|
403 | e69954b9 | pbrook | val = gic_dist_readw(opaque, offset); |
404 | e69954b9 | pbrook | val |= gic_dist_readw(opaque, offset + 2) << 16; |
405 | e69954b9 | pbrook | return val;
|
406 | e69954b9 | pbrook | } |
407 | e69954b9 | pbrook | |
408 | c227f099 | Anthony Liguori | static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, |
409 | e69954b9 | pbrook | uint32_t value) |
410 | e69954b9 | pbrook | { |
411 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
412 | e69954b9 | pbrook | int irq;
|
413 | e69954b9 | pbrook | int i;
|
414 | 9ee6e8bb | pbrook | int cpu;
|
415 | e69954b9 | pbrook | |
416 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
417 | e69954b9 | pbrook | if (offset < 0x100) { |
418 | 9ee6e8bb | pbrook | #ifdef NVIC
|
419 | 9ee6e8bb | pbrook | goto bad_reg;
|
420 | 9ee6e8bb | pbrook | #else
|
421 | e69954b9 | pbrook | if (offset == 0) { |
422 | e69954b9 | pbrook | s->enabled = (value & 1);
|
423 | e69954b9 | pbrook | DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); |
424 | e69954b9 | pbrook | } else if (offset < 4) { |
425 | e69954b9 | pbrook | /* ignored. */
|
426 | b79f2265 | Rob Herring | } else if (offset >= 0x80) { |
427 | b79f2265 | Rob Herring | /* Interrupt Security Registers, RAZ/WI */
|
428 | e69954b9 | pbrook | } else {
|
429 | e69954b9 | pbrook | goto bad_reg;
|
430 | e69954b9 | pbrook | } |
431 | 9ee6e8bb | pbrook | #endif
|
432 | e69954b9 | pbrook | } else if (offset < 0x180) { |
433 | e69954b9 | pbrook | /* Interrupt Set Enable. */
|
434 | 9ee6e8bb | pbrook | irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; |
435 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
436 | e69954b9 | pbrook | goto bad_reg;
|
437 | 9ee6e8bb | pbrook | if (irq < 16) |
438 | 9ee6e8bb | pbrook | value = 0xff;
|
439 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
440 | e69954b9 | pbrook | if (value & (1 << i)) { |
441 | 69253800 | Rusty Russell | int mask = (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq); |
442 | 69253800 | Rusty Russell | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
443 | 41bf234d | Rabin Vincent | |
444 | 41bf234d | Rabin Vincent | if (!GIC_TEST_ENABLED(irq + i, cm)) {
|
445 | e69954b9 | pbrook | DPRINTF("Enabled IRQ %d\n", irq + i);
|
446 | 41bf234d | Rabin Vincent | } |
447 | 41bf234d | Rabin Vincent | GIC_SET_ENABLED(irq + i, cm); |
448 | e69954b9 | pbrook | /* If a raised level triggered IRQ enabled then mark
|
449 | e69954b9 | pbrook | is as pending. */
|
450 | 9ee6e8bb | pbrook | if (GIC_TEST_LEVEL(irq + i, mask)
|
451 | 9ee6e8bb | pbrook | && !GIC_TEST_TRIGGER(irq + i)) { |
452 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq + i, mask);
|
453 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq + i, mask); |
454 | 9ee6e8bb | pbrook | } |
455 | e69954b9 | pbrook | } |
456 | e69954b9 | pbrook | } |
457 | e69954b9 | pbrook | } else if (offset < 0x200) { |
458 | e69954b9 | pbrook | /* Interrupt Clear Enable. */
|
459 | 9ee6e8bb | pbrook | irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; |
460 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
461 | e69954b9 | pbrook | goto bad_reg;
|
462 | 9ee6e8bb | pbrook | if (irq < 16) |
463 | 9ee6e8bb | pbrook | value = 0;
|
464 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
465 | e69954b9 | pbrook | if (value & (1 << i)) { |
466 | 69253800 | Rusty Russell | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
467 | 41bf234d | Rabin Vincent | |
468 | 41bf234d | Rabin Vincent | if (GIC_TEST_ENABLED(irq + i, cm)) {
|
469 | e69954b9 | pbrook | DPRINTF("Disabled IRQ %d\n", irq + i);
|
470 | 41bf234d | Rabin Vincent | } |
471 | 41bf234d | Rabin Vincent | GIC_CLEAR_ENABLED(irq + i, cm); |
472 | e69954b9 | pbrook | } |
473 | e69954b9 | pbrook | } |
474 | e69954b9 | pbrook | } else if (offset < 0x280) { |
475 | e69954b9 | pbrook | /* Interrupt Set Pending. */
|
476 | 9ee6e8bb | pbrook | irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; |
477 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
478 | e69954b9 | pbrook | goto bad_reg;
|
479 | 9ee6e8bb | pbrook | if (irq < 16) |
480 | 9ee6e8bb | pbrook | irq = 0;
|
481 | 9ee6e8bb | pbrook | |
482 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
483 | e69954b9 | pbrook | if (value & (1 << i)) { |
484 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq + i, GIC_TARGET(irq)); |
485 | e69954b9 | pbrook | } |
486 | e69954b9 | pbrook | } |
487 | e69954b9 | pbrook | } else if (offset < 0x300) { |
488 | e69954b9 | pbrook | /* Interrupt Clear Pending. */
|
489 | 9ee6e8bb | pbrook | irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; |
490 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
491 | e69954b9 | pbrook | goto bad_reg;
|
492 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
493 | 9ee6e8bb | pbrook | /* ??? This currently clears the pending bit for all CPUs, even
|
494 | 9ee6e8bb | pbrook | for per-CPU interrupts. It's unclear whether this is the
|
495 | 9ee6e8bb | pbrook | corect behavior. */
|
496 | e69954b9 | pbrook | if (value & (1 << i)) { |
497 | 9ee6e8bb | pbrook | GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); |
498 | e69954b9 | pbrook | } |
499 | e69954b9 | pbrook | } |
500 | e69954b9 | pbrook | } else if (offset < 0x400) { |
501 | e69954b9 | pbrook | /* Interrupt Active. */
|
502 | e69954b9 | pbrook | goto bad_reg;
|
503 | e69954b9 | pbrook | } else if (offset < 0x800) { |
504 | e69954b9 | pbrook | /* Interrupt Priority. */
|
505 | 9ee6e8bb | pbrook | irq = (offset - 0x400) + GIC_BASE_IRQ;
|
506 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
507 | e69954b9 | pbrook | goto bad_reg;
|
508 | 69253800 | Rusty Russell | if (irq < GIC_INTERNAL) {
|
509 | 9ee6e8bb | pbrook | s->priority1[irq][cpu] = value; |
510 | 9ee6e8bb | pbrook | } else {
|
511 | 69253800 | Rusty Russell | s->priority2[irq - GIC_INTERNAL] = value; |
512 | 9ee6e8bb | pbrook | } |
513 | 9ee6e8bb | pbrook | #ifndef NVIC
|
514 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
515 | e69954b9 | pbrook | /* Interrupt CPU Target. */
|
516 | 9ee6e8bb | pbrook | irq = (offset - 0x800) + GIC_BASE_IRQ;
|
517 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
518 | e69954b9 | pbrook | goto bad_reg;
|
519 | 9ee6e8bb | pbrook | if (irq < 29) |
520 | 9ee6e8bb | pbrook | value = 0;
|
521 | 69253800 | Rusty Russell | else if (irq < GIC_INTERNAL) |
522 | 9ee6e8bb | pbrook | value = ALL_CPU_MASK; |
523 | 9ee6e8bb | pbrook | s->irq_target[irq] = value & ALL_CPU_MASK; |
524 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
525 | e69954b9 | pbrook | /* Interrupt Configuration. */
|
526 | 9ee6e8bb | pbrook | irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; |
527 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
528 | e69954b9 | pbrook | goto bad_reg;
|
529 | 69253800 | Rusty Russell | if (irq < GIC_INTERNAL)
|
530 | 9ee6e8bb | pbrook | value |= 0xaa;
|
531 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
532 | e69954b9 | pbrook | if (value & (1 << (i * 2))) { |
533 | e69954b9 | pbrook | GIC_SET_MODEL(irq + i); |
534 | e69954b9 | pbrook | } else {
|
535 | e69954b9 | pbrook | GIC_CLEAR_MODEL(irq + i); |
536 | e69954b9 | pbrook | } |
537 | e69954b9 | pbrook | if (value & (2 << (i * 2))) { |
538 | e69954b9 | pbrook | GIC_SET_TRIGGER(irq + i); |
539 | e69954b9 | pbrook | } else {
|
540 | e69954b9 | pbrook | GIC_CLEAR_TRIGGER(irq + i); |
541 | e69954b9 | pbrook | } |
542 | e69954b9 | pbrook | } |
543 | 9ee6e8bb | pbrook | #endif
|
544 | e69954b9 | pbrook | } else {
|
545 | 9ee6e8bb | pbrook | /* 0xf00 is only handled for 32-bit writes. */
|
546 | e69954b9 | pbrook | goto bad_reg;
|
547 | e69954b9 | pbrook | } |
548 | e69954b9 | pbrook | gic_update(s); |
549 | e69954b9 | pbrook | return;
|
550 | e69954b9 | pbrook | bad_reg:
|
551 | 2ac71179 | Paul Brook | hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset); |
552 | e69954b9 | pbrook | } |
553 | e69954b9 | pbrook | |
554 | c227f099 | Anthony Liguori | static void gic_dist_writew(void *opaque, target_phys_addr_t offset, |
555 | e69954b9 | pbrook | uint32_t value) |
556 | e69954b9 | pbrook | { |
557 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset, value & 0xff);
|
558 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset + 1, value >> 8); |
559 | e69954b9 | pbrook | } |
560 | e69954b9 | pbrook | |
561 | c227f099 | Anthony Liguori | static void gic_dist_writel(void *opaque, target_phys_addr_t offset, |
562 | e69954b9 | pbrook | uint32_t value) |
563 | e69954b9 | pbrook | { |
564 | 9ee6e8bb | pbrook | gic_state *s = (gic_state *)opaque; |
565 | 9ee6e8bb | pbrook | #ifdef NVIC
|
566 | 9ee6e8bb | pbrook | uint32_t addr; |
567 | 8da3ff18 | pbrook | addr = offset; |
568 | 9ee6e8bb | pbrook | if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) { |
569 | fe7e8758 | Paul Brook | nvic_writel(s, addr, value); |
570 | 9ee6e8bb | pbrook | return;
|
571 | 9ee6e8bb | pbrook | } |
572 | 9ee6e8bb | pbrook | #endif
|
573 | 8da3ff18 | pbrook | if (offset == 0xf00) { |
574 | 9ee6e8bb | pbrook | int cpu;
|
575 | 9ee6e8bb | pbrook | int irq;
|
576 | 9ee6e8bb | pbrook | int mask;
|
577 | 9ee6e8bb | pbrook | |
578 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
579 | 9ee6e8bb | pbrook | irq = value & 0x3ff;
|
580 | 9ee6e8bb | pbrook | switch ((value >> 24) & 3) { |
581 | 9ee6e8bb | pbrook | case 0: |
582 | 9ee6e8bb | pbrook | mask = (value >> 16) & ALL_CPU_MASK;
|
583 | 9ee6e8bb | pbrook | break;
|
584 | 9ee6e8bb | pbrook | case 1: |
585 | fa250144 | Adam Lackorzynski | mask = ALL_CPU_MASK ^ (1 << cpu);
|
586 | 9ee6e8bb | pbrook | break;
|
587 | 9ee6e8bb | pbrook | case 2: |
588 | fa250144 | Adam Lackorzynski | mask = 1 << cpu;
|
589 | 9ee6e8bb | pbrook | break;
|
590 | 9ee6e8bb | pbrook | default:
|
591 | 9ee6e8bb | pbrook | DPRINTF("Bad Soft Int target filter\n");
|
592 | 9ee6e8bb | pbrook | mask = ALL_CPU_MASK; |
593 | 9ee6e8bb | pbrook | break;
|
594 | 9ee6e8bb | pbrook | } |
595 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, mask); |
596 | 9ee6e8bb | pbrook | gic_update(s); |
597 | 9ee6e8bb | pbrook | return;
|
598 | 9ee6e8bb | pbrook | } |
599 | e69954b9 | pbrook | gic_dist_writew(opaque, offset, value & 0xffff);
|
600 | e69954b9 | pbrook | gic_dist_writew(opaque, offset + 2, value >> 16); |
601 | e69954b9 | pbrook | } |
602 | e69954b9 | pbrook | |
603 | 755c0802 | Avi Kivity | static const MemoryRegionOps gic_dist_ops = { |
604 | 755c0802 | Avi Kivity | .old_mmio = { |
605 | 755c0802 | Avi Kivity | .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, }, |
606 | 755c0802 | Avi Kivity | .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, }, |
607 | 755c0802 | Avi Kivity | }, |
608 | 755c0802 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
609 | e69954b9 | pbrook | }; |
610 | e69954b9 | pbrook | |
611 | 9ee6e8bb | pbrook | #ifndef NVIC
|
612 | 9ee6e8bb | pbrook | static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset) |
613 | e69954b9 | pbrook | { |
614 | e69954b9 | pbrook | switch (offset) {
|
615 | e69954b9 | pbrook | case 0x00: /* Control */ |
616 | 9ee6e8bb | pbrook | return s->cpu_enabled[cpu];
|
617 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
618 | 9ee6e8bb | pbrook | return s->priority_mask[cpu];
|
619 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
620 | e69954b9 | pbrook | /* ??? Not implemented. */
|
621 | e69954b9 | pbrook | return 0; |
622 | e69954b9 | pbrook | case 0x0c: /* Acknowledge */ |
623 | 9ee6e8bb | pbrook | return gic_acknowledge_irq(s, cpu);
|
624 | 66a0a2cb | Dong Xu Wang | case 0x14: /* Running Priority */ |
625 | 9ee6e8bb | pbrook | return s->running_priority[cpu];
|
626 | e69954b9 | pbrook | case 0x18: /* Highest Pending Interrupt */ |
627 | 9ee6e8bb | pbrook | return s->current_pending[cpu];
|
628 | e69954b9 | pbrook | default:
|
629 | 2ac71179 | Paul Brook | hw_error("gic_cpu_read: Bad offset %x\n", (int)offset); |
630 | e69954b9 | pbrook | return 0; |
631 | e69954b9 | pbrook | } |
632 | e69954b9 | pbrook | } |
633 | e69954b9 | pbrook | |
634 | 9ee6e8bb | pbrook | static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value) |
635 | e69954b9 | pbrook | { |
636 | e69954b9 | pbrook | switch (offset) {
|
637 | e69954b9 | pbrook | case 0x00: /* Control */ |
638 | 9ee6e8bb | pbrook | s->cpu_enabled[cpu] = (value & 1);
|
639 | f7c70325 | Paul Brook | DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis"); |
640 | e69954b9 | pbrook | break;
|
641 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
642 | 9ee6e8bb | pbrook | s->priority_mask[cpu] = (value & 0xff);
|
643 | e69954b9 | pbrook | break;
|
644 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
645 | e69954b9 | pbrook | /* ??? Not implemented. */
|
646 | e69954b9 | pbrook | break;
|
647 | e69954b9 | pbrook | case 0x10: /* End Of Interrupt */ |
648 | 9ee6e8bb | pbrook | return gic_complete_irq(s, cpu, value & 0x3ff); |
649 | e69954b9 | pbrook | default:
|
650 | 2ac71179 | Paul Brook | hw_error("gic_cpu_write: Bad offset %x\n", (int)offset); |
651 | e69954b9 | pbrook | return;
|
652 | e69954b9 | pbrook | } |
653 | e69954b9 | pbrook | gic_update(s); |
654 | e69954b9 | pbrook | } |
655 | e2c56465 | Peter Maydell | |
656 | e2c56465 | Peter Maydell | /* Wrappers to read/write the GIC CPU interface for the current CPU */
|
657 | e2c56465 | Peter Maydell | static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr, |
658 | e2c56465 | Peter Maydell | unsigned size)
|
659 | e2c56465 | Peter Maydell | { |
660 | e2c56465 | Peter Maydell | gic_state *s = (gic_state *)opaque; |
661 | 0e4a398a | Peter Maydell | return gic_cpu_read(s, gic_get_current_cpu(), addr);
|
662 | e2c56465 | Peter Maydell | } |
663 | e2c56465 | Peter Maydell | |
664 | e2c56465 | Peter Maydell | static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr, |
665 | e2c56465 | Peter Maydell | uint64_t value, unsigned size)
|
666 | e2c56465 | Peter Maydell | { |
667 | e2c56465 | Peter Maydell | gic_state *s = (gic_state *)opaque; |
668 | 0e4a398a | Peter Maydell | gic_cpu_write(s, gic_get_current_cpu(), addr, value); |
669 | e2c56465 | Peter Maydell | } |
670 | e2c56465 | Peter Maydell | |
671 | e2c56465 | Peter Maydell | /* Wrappers to read/write the GIC CPU interface for a specific CPU.
|
672 | e2c56465 | Peter Maydell | * These just decode the opaque pointer into gic_state* + cpu id.
|
673 | e2c56465 | Peter Maydell | */
|
674 | e2c56465 | Peter Maydell | static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr, |
675 | e2c56465 | Peter Maydell | unsigned size)
|
676 | e2c56465 | Peter Maydell | { |
677 | e2c56465 | Peter Maydell | gic_state **backref = (gic_state **)opaque; |
678 | e2c56465 | Peter Maydell | gic_state *s = *backref; |
679 | e2c56465 | Peter Maydell | int id = (backref - s->backref);
|
680 | 0e4a398a | Peter Maydell | return gic_cpu_read(s, id, addr);
|
681 | e2c56465 | Peter Maydell | } |
682 | e2c56465 | Peter Maydell | |
683 | e2c56465 | Peter Maydell | static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr, |
684 | e2c56465 | Peter Maydell | uint64_t value, unsigned size)
|
685 | e2c56465 | Peter Maydell | { |
686 | e2c56465 | Peter Maydell | gic_state **backref = (gic_state **)opaque; |
687 | e2c56465 | Peter Maydell | gic_state *s = *backref; |
688 | e2c56465 | Peter Maydell | int id = (backref - s->backref);
|
689 | 0e4a398a | Peter Maydell | gic_cpu_write(s, id, addr, value); |
690 | e2c56465 | Peter Maydell | } |
691 | e2c56465 | Peter Maydell | |
692 | e2c56465 | Peter Maydell | static const MemoryRegionOps gic_thiscpu_ops = { |
693 | e2c56465 | Peter Maydell | .read = gic_thiscpu_read, |
694 | e2c56465 | Peter Maydell | .write = gic_thiscpu_write, |
695 | e2c56465 | Peter Maydell | .endianness = DEVICE_NATIVE_ENDIAN, |
696 | e2c56465 | Peter Maydell | }; |
697 | e2c56465 | Peter Maydell | |
698 | e2c56465 | Peter Maydell | static const MemoryRegionOps gic_cpu_ops = { |
699 | e2c56465 | Peter Maydell | .read = gic_do_cpu_read, |
700 | e2c56465 | Peter Maydell | .write = gic_do_cpu_write, |
701 | e2c56465 | Peter Maydell | .endianness = DEVICE_NATIVE_ENDIAN, |
702 | e2c56465 | Peter Maydell | }; |
703 | 9ee6e8bb | pbrook | #endif
|
704 | e69954b9 | pbrook | |
705 | e69954b9 | pbrook | static void gic_reset(gic_state *s) |
706 | e69954b9 | pbrook | { |
707 | e69954b9 | pbrook | int i;
|
708 | a32134aa | Mark Langsdorf | memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); |
709 | c988bfad | Paul Brook | for (i = 0 ; i < NUM_CPU(s); i++) { |
710 | 9ee6e8bb | pbrook | s->priority_mask[i] = 0xf0;
|
711 | 9ee6e8bb | pbrook | s->current_pending[i] = 1023;
|
712 | 9ee6e8bb | pbrook | s->running_irq[i] = 1023;
|
713 | 9ee6e8bb | pbrook | s->running_priority[i] = 0x100;
|
714 | 9ee6e8bb | pbrook | #ifdef NVIC
|
715 | 9ee6e8bb | pbrook | /* The NVIC doesn't have per-cpu interfaces, so enable by default. */
|
716 | 9ee6e8bb | pbrook | s->cpu_enabled[i] = 1;
|
717 | 9ee6e8bb | pbrook | #else
|
718 | 9ee6e8bb | pbrook | s->cpu_enabled[i] = 0;
|
719 | 9ee6e8bb | pbrook | #endif
|
720 | 9ee6e8bb | pbrook | } |
721 | e57ec016 | pbrook | for (i = 0; i < 16; i++) { |
722 | 41bf234d | Rabin Vincent | GIC_SET_ENABLED(i, ALL_CPU_MASK); |
723 | e69954b9 | pbrook | GIC_SET_TRIGGER(i); |
724 | e69954b9 | pbrook | } |
725 | 9ee6e8bb | pbrook | #ifdef NVIC
|
726 | 9ee6e8bb | pbrook | /* The NVIC is always enabled. */
|
727 | 9ee6e8bb | pbrook | s->enabled = 1;
|
728 | 9ee6e8bb | pbrook | #else
|
729 | e69954b9 | pbrook | s->enabled = 0;
|
730 | 9ee6e8bb | pbrook | #endif
|
731 | e69954b9 | pbrook | } |
732 | e69954b9 | pbrook | |
733 | 23e39294 | pbrook | static void gic_save(QEMUFile *f, void *opaque) |
734 | 23e39294 | pbrook | { |
735 | 23e39294 | pbrook | gic_state *s = (gic_state *)opaque; |
736 | 23e39294 | pbrook | int i;
|
737 | 23e39294 | pbrook | int j;
|
738 | 23e39294 | pbrook | |
739 | 23e39294 | pbrook | qemu_put_be32(f, s->enabled); |
740 | c988bfad | Paul Brook | for (i = 0; i < NUM_CPU(s); i++) { |
741 | 23e39294 | pbrook | qemu_put_be32(f, s->cpu_enabled[i]); |
742 | 69253800 | Rusty Russell | for (j = 0; j < GIC_INTERNAL; j++) |
743 | 23e39294 | pbrook | qemu_put_be32(f, s->priority1[j][i]); |
744 | a32134aa | Mark Langsdorf | for (j = 0; j < s->num_irq; j++) |
745 | 23e39294 | pbrook | qemu_put_be32(f, s->last_active[j][i]); |
746 | 23e39294 | pbrook | qemu_put_be32(f, s->priority_mask[i]); |
747 | 23e39294 | pbrook | qemu_put_be32(f, s->running_irq[i]); |
748 | 23e39294 | pbrook | qemu_put_be32(f, s->running_priority[i]); |
749 | 23e39294 | pbrook | qemu_put_be32(f, s->current_pending[i]); |
750 | 23e39294 | pbrook | } |
751 | 69253800 | Rusty Russell | for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) { |
752 | 23e39294 | pbrook | qemu_put_be32(f, s->priority2[i]); |
753 | 23e39294 | pbrook | } |
754 | a32134aa | Mark Langsdorf | for (i = 0; i < s->num_irq; i++) { |
755 | c2e2343e | Dmitry Koshelev | #ifndef NVIC
|
756 | c2e2343e | Dmitry Koshelev | qemu_put_be32(f, s->irq_target[i]); |
757 | c2e2343e | Dmitry Koshelev | #endif
|
758 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].enabled); |
759 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].pending); |
760 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].active); |
761 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].level); |
762 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].model); |
763 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].trigger); |
764 | 23e39294 | pbrook | } |
765 | 23e39294 | pbrook | } |
766 | 23e39294 | pbrook | |
767 | 23e39294 | pbrook | static int gic_load(QEMUFile *f, void *opaque, int version_id) |
768 | 23e39294 | pbrook | { |
769 | 23e39294 | pbrook | gic_state *s = (gic_state *)opaque; |
770 | 23e39294 | pbrook | int i;
|
771 | 23e39294 | pbrook | int j;
|
772 | 23e39294 | pbrook | |
773 | c2e2343e | Dmitry Koshelev | if (version_id != 2) |
774 | 23e39294 | pbrook | return -EINVAL;
|
775 | 23e39294 | pbrook | |
776 | 23e39294 | pbrook | s->enabled = qemu_get_be32(f); |
777 | c988bfad | Paul Brook | for (i = 0; i < NUM_CPU(s); i++) { |
778 | 23e39294 | pbrook | s->cpu_enabled[i] = qemu_get_be32(f); |
779 | 69253800 | Rusty Russell | for (j = 0; j < GIC_INTERNAL; j++) |
780 | 23e39294 | pbrook | s->priority1[j][i] = qemu_get_be32(f); |
781 | a32134aa | Mark Langsdorf | for (j = 0; j < s->num_irq; j++) |
782 | 23e39294 | pbrook | s->last_active[j][i] = qemu_get_be32(f); |
783 | 23e39294 | pbrook | s->priority_mask[i] = qemu_get_be32(f); |
784 | 23e39294 | pbrook | s->running_irq[i] = qemu_get_be32(f); |
785 | 23e39294 | pbrook | s->running_priority[i] = qemu_get_be32(f); |
786 | 23e39294 | pbrook | s->current_pending[i] = qemu_get_be32(f); |
787 | 23e39294 | pbrook | } |
788 | 69253800 | Rusty Russell | for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) { |
789 | 23e39294 | pbrook | s->priority2[i] = qemu_get_be32(f); |
790 | 23e39294 | pbrook | } |
791 | a32134aa | Mark Langsdorf | for (i = 0; i < s->num_irq; i++) { |
792 | c2e2343e | Dmitry Koshelev | #ifndef NVIC
|
793 | c2e2343e | Dmitry Koshelev | s->irq_target[i] = qemu_get_be32(f); |
794 | c2e2343e | Dmitry Koshelev | #endif
|
795 | 23e39294 | pbrook | s->irq_state[i].enabled = qemu_get_byte(f); |
796 | 23e39294 | pbrook | s->irq_state[i].pending = qemu_get_byte(f); |
797 | 23e39294 | pbrook | s->irq_state[i].active = qemu_get_byte(f); |
798 | 23e39294 | pbrook | s->irq_state[i].level = qemu_get_byte(f); |
799 | 23e39294 | pbrook | s->irq_state[i].model = qemu_get_byte(f); |
800 | 23e39294 | pbrook | s->irq_state[i].trigger = qemu_get_byte(f); |
801 | 23e39294 | pbrook | } |
802 | 23e39294 | pbrook | |
803 | 23e39294 | pbrook | return 0; |
804 | 23e39294 | pbrook | } |
805 | 23e39294 | pbrook | |
806 | c988bfad | Paul Brook | #if NCPU > 1 |
807 | a32134aa | Mark Langsdorf | static void gic_init(gic_state *s, int num_cpu, int num_irq) |
808 | c988bfad | Paul Brook | #else
|
809 | a32134aa | Mark Langsdorf | static void gic_init(gic_state *s, int num_irq) |
810 | c988bfad | Paul Brook | #endif
|
811 | e69954b9 | pbrook | { |
812 | 9ee6e8bb | pbrook | int i;
|
813 | e69954b9 | pbrook | |
814 | c988bfad | Paul Brook | #if NCPU > 1 |
815 | c988bfad | Paul Brook | s->num_cpu = num_cpu; |
816 | c988bfad | Paul Brook | #endif
|
817 | a32134aa | Mark Langsdorf | s->num_irq = num_irq + GIC_BASE_IRQ; |
818 | a32134aa | Mark Langsdorf | if (s->num_irq > GIC_MAXIRQ) {
|
819 | a32134aa | Mark Langsdorf | hw_error("requested %u interrupt lines exceeds GIC maximum %d\n",
|
820 | a32134aa | Mark Langsdorf | num_irq, GIC_MAXIRQ); |
821 | a32134aa | Mark Langsdorf | } |
822 | 41c1e2f5 | Rusty Russell | /* ITLinesNumber is represented as (N / 32) - 1 (see
|
823 | 41c1e2f5 | Rusty Russell | * gic_dist_readb) so this is an implementation imposed
|
824 | 41c1e2f5 | Rusty Russell | * restriction, not an architectural one:
|
825 | 41c1e2f5 | Rusty Russell | */
|
826 | 41c1e2f5 | Rusty Russell | if (s->num_irq < 32 || (s->num_irq % 32)) { |
827 | 41c1e2f5 | Rusty Russell | hw_error("%d interrupt lines unsupported: not divisible by 32\n",
|
828 | 41c1e2f5 | Rusty Russell | num_irq); |
829 | 41c1e2f5 | Rusty Russell | } |
830 | 41c1e2f5 | Rusty Russell | |
831 | 69253800 | Rusty Russell | qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, s->num_irq - GIC_INTERNAL); |
832 | c988bfad | Paul Brook | for (i = 0; i < NUM_CPU(s); i++) { |
833 | fe7e8758 | Paul Brook | sysbus_init_irq(&s->busdev, &s->parent_irq[i]); |
834 | e69954b9 | pbrook | } |
835 | 755c0802 | Avi Kivity | memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000); |
836 | e2c56465 | Peter Maydell | #ifndef NVIC
|
837 | e2c56465 | Peter Maydell | /* Memory regions for the CPU interfaces (NVIC doesn't have these):
|
838 | e2c56465 | Peter Maydell | * a region for "CPU interface for this core", then a region for
|
839 | e2c56465 | Peter Maydell | * "CPU interface for core 0", "for core 1", ...
|
840 | e2c56465 | Peter Maydell | * NB that the memory region size of 0x100 applies for the 11MPCore
|
841 | e2c56465 | Peter Maydell | * and also cores following the GIC v1 spec (ie A9).
|
842 | e2c56465 | Peter Maydell | * GIC v2 defines a larger memory region (0x1000) so this will need
|
843 | e2c56465 | Peter Maydell | * to be extended when we implement A15.
|
844 | e2c56465 | Peter Maydell | */
|
845 | e2c56465 | Peter Maydell | memory_region_init_io(&s->cpuiomem[0], &gic_thiscpu_ops, s,
|
846 | e2c56465 | Peter Maydell | "gic_cpu", 0x100); |
847 | e2c56465 | Peter Maydell | for (i = 0; i < NUM_CPU(s); i++) { |
848 | e2c56465 | Peter Maydell | s->backref[i] = s; |
849 | e2c56465 | Peter Maydell | memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i],
|
850 | e2c56465 | Peter Maydell | "gic_cpu", 0x100); |
851 | e2c56465 | Peter Maydell | } |
852 | e2c56465 | Peter Maydell | #endif
|
853 | e2c56465 | Peter Maydell | |
854 | e69954b9 | pbrook | gic_reset(s); |
855 | c2e2343e | Dmitry Koshelev | register_savevm(NULL, "arm_gic", -1, 2, gic_save, gic_load, s); |
856 | e69954b9 | pbrook | } |