root / hw / pci.h @ 4b8f1c88
History | View | Annotate | Download (19 kB)
1 | 87ecb68b | pbrook | #ifndef QEMU_PCI_H
|
---|---|---|---|
2 | 87ecb68b | pbrook | #define QEMU_PCI_H
|
3 | 87ecb68b | pbrook | |
4 | 376253ec | aliguori | #include "qemu-common.h" |
5 | 376253ec | aliguori | |
6 | 6b1b92d3 | Paul Brook | #include "qdev.h" |
7 | 1e39101c | Avi Kivity | #include "memory.h" |
8 | ec174575 | David Gibson | #include "dma.h" |
9 | 6b1b92d3 | Paul Brook | |
10 | 87ecb68b | pbrook | /* PCI includes legacy ISA access. */
|
11 | 87ecb68b | pbrook | #include "isa.h" |
12 | 87ecb68b | pbrook | |
13 | 0428527c | Isaku Yamahata | #include "pcie.h" |
14 | 0428527c | Isaku Yamahata | |
15 | 87ecb68b | pbrook | /* PCI bus */
|
16 | 87ecb68b | pbrook | |
17 | 3ae80618 | aliguori | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
18 | 3ae80618 | aliguori | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
19 | 3ae80618 | aliguori | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
20 | 90a20dbb | Isaku Yamahata | #define PCI_SLOT_MAX 32 |
21 | 6fa84913 | Isaku Yamahata | #define PCI_FUNC_MAX 8 |
22 | 3ae80618 | aliguori | |
23 | a770dc7e | aliguori | /* Class, Vendor and Device IDs from Linux's pci_ids.h */
|
24 | a770dc7e | aliguori | #include "pci_ids.h" |
25 | 173a543b | blueswir1 | |
26 | a770dc7e | aliguori | /* QEMU-specific Vendor and Device ID definitions */
|
27 | 6f338c34 | aliguori | |
28 | a770dc7e | aliguori | /* IBM (0x1014) */
|
29 | a770dc7e | aliguori | #define PCI_DEVICE_ID_IBM_440GX 0x027f |
30 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
31 | deb54399 | aliguori | |
32 | a770dc7e | aliguori | /* Hitachi (0x1054) */
|
33 | deb54399 | aliguori | #define PCI_VENDOR_ID_HITACHI 0x1054 |
34 | a770dc7e | aliguori | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
35 | deb54399 | aliguori | |
36 | a770dc7e | aliguori | /* Apple (0x106b) */
|
37 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
38 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e |
39 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f |
40 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
41 | a770dc7e | aliguori | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
42 | deb54399 | aliguori | |
43 | a770dc7e | aliguori | /* Realtek (0x10ec) */
|
44 | a770dc7e | aliguori | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 |
45 | deb54399 | aliguori | |
46 | a770dc7e | aliguori | /* Xilinx (0x10ee) */
|
47 | a770dc7e | aliguori | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 |
48 | deb54399 | aliguori | |
49 | a770dc7e | aliguori | /* Marvell (0x11ab) */
|
50 | a770dc7e | aliguori | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 |
51 | deb54399 | aliguori | |
52 | a770dc7e | aliguori | /* QEMU/Bochs VGA (0x1234) */
|
53 | 4ebcf884 | blueswir1 | #define PCI_VENDOR_ID_QEMU 0x1234 |
54 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 |
55 | 4ebcf884 | blueswir1 | |
56 | a770dc7e | aliguori | /* VMWare (0x15ad) */
|
57 | deb54399 | aliguori | #define PCI_VENDOR_ID_VMWARE 0x15ad |
58 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
59 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
60 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
61 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
62 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
63 | deb54399 | aliguori | |
64 | cef3017c | aliguori | /* Intel (0x8086) */
|
65 | a770dc7e | aliguori | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
66 | d6fd1e66 | Stefan Weil | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
67 | 1a5a86fb | Alexander Graf | #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 |
68 | 74c62ba8 | aurel32 | |
69 | deb54399 | aliguori | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
|
70 | d350d97d | aliguori | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
71 | d350d97d | aliguori | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 |
72 | d350d97d | aliguori | #define PCI_SUBDEVICE_ID_QEMU 0x1100 |
73 | d350d97d | aliguori | |
74 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 |
75 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 |
76 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 |
77 | 14d50bef | aliguori | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
78 | 973abc7f | Stefan Hajnoczi | #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 |
79 | d350d97d | aliguori | |
80 | 4f8589e1 | Isaku Yamahata | #define FMT_PCIBUS PRIx64
|
81 | 6e355d90 | Isaku Yamahata | |
82 | 87ecb68b | pbrook | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
83 | 87ecb68b | pbrook | uint32_t address, uint32_t data, int len);
|
84 | 87ecb68b | pbrook | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
|
85 | 87ecb68b | pbrook | uint32_t address, int len);
|
86 | 87ecb68b | pbrook | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
87 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type);
|
88 | 5851e08c | aliguori | typedef int PCIUnregisterFunc(PCIDevice *pci_dev); |
89 | 87ecb68b | pbrook | |
90 | 87ecb68b | pbrook | typedef struct PCIIORegion { |
91 | 6e355d90 | Isaku Yamahata | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
|
92 | 6e355d90 | Isaku Yamahata | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) |
93 | 6e355d90 | Isaku Yamahata | pcibus_t size; |
94 | 87ecb68b | pbrook | uint8_t type; |
95 | 79ff8cb0 | Avi Kivity | MemoryRegion *memory; |
96 | 5968eca3 | Avi Kivity | MemoryRegion *address_space; |
97 | 87ecb68b | pbrook | } PCIIORegion; |
98 | 87ecb68b | pbrook | |
99 | 87ecb68b | pbrook | #define PCI_ROM_SLOT 6 |
100 | 87ecb68b | pbrook | #define PCI_NUM_REGIONS 7 |
101 | 87ecb68b | pbrook | |
102 | fb58a897 | Isaku Yamahata | #include "pci_regs.h" |
103 | fb58a897 | Isaku Yamahata | |
104 | fb58a897 | Isaku Yamahata | /* PCI HEADER_TYPE */
|
105 | 6407f373 | Isaku Yamahata | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
106 | 8098ed41 | aurel32 | |
107 | b7ee1603 | Michael S. Tsirkin | /* Size of the standard PCI config header */
|
108 | b7ee1603 | Michael S. Tsirkin | #define PCI_CONFIG_HEADER_SIZE 0x40 |
109 | b7ee1603 | Michael S. Tsirkin | /* Size of the standard PCI config space */
|
110 | b7ee1603 | Michael S. Tsirkin | #define PCI_CONFIG_SPACE_SIZE 0x100 |
111 | a9f49946 | Isaku Yamahata | /* Size of the standart PCIe config space: 4KB */
|
112 | a9f49946 | Isaku Yamahata | #define PCIE_CONFIG_SPACE_SIZE 0x1000 |
113 | b7ee1603 | Michael S. Tsirkin | |
114 | e369cad7 | Isaku Yamahata | #define PCI_NUM_PINS 4 /* A-D */ |
115 | e369cad7 | Isaku Yamahata | |
116 | 02eb84d0 | Michael S. Tsirkin | /* Bits in cap_present field. */
|
117 | 02eb84d0 | Michael S. Tsirkin | enum {
|
118 | e4c7d2ae | Isaku Yamahata | QEMU_PCI_CAP_MSI = 0x1,
|
119 | e4c7d2ae | Isaku Yamahata | QEMU_PCI_CAP_MSIX = 0x2,
|
120 | e4c7d2ae | Isaku Yamahata | QEMU_PCI_CAP_EXPRESS = 0x4,
|
121 | 49823868 | Isaku Yamahata | |
122 | 49823868 | Isaku Yamahata | /* multifunction capable device */
|
123 | e4c7d2ae | Isaku Yamahata | #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
124 | 49823868 | Isaku Yamahata | QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
|
125 | b1aeb926 | Isaku Yamahata | |
126 | b1aeb926 | Isaku Yamahata | /* command register SERR bit enabled */
|
127 | b1aeb926 | Isaku Yamahata | #define QEMU_PCI_CAP_SERR_BITNR 4 |
128 | b1aeb926 | Isaku Yamahata | QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
|
129 | 1dc324d2 | Michael S. Tsirkin | /* Standard hot plug controller. */
|
130 | 1dc324d2 | Michael S. Tsirkin | #define QEMU_PCI_SHPC_BITNR 5 |
131 | 1dc324d2 | Michael S. Tsirkin | QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
|
132 | 762833b3 | Michael S. Tsirkin | #define QEMU_PCI_SLOTID_BITNR 6 |
133 | 762833b3 | Michael S. Tsirkin | QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
|
134 | 02eb84d0 | Michael S. Tsirkin | }; |
135 | 02eb84d0 | Michael S. Tsirkin | |
136 | 40021f08 | Anthony Liguori | #define TYPE_PCI_DEVICE "pci-device" |
137 | 40021f08 | Anthony Liguori | #define PCI_DEVICE(obj) \
|
138 | 40021f08 | Anthony Liguori | OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) |
139 | 40021f08 | Anthony Liguori | #define PCI_DEVICE_CLASS(klass) \
|
140 | 40021f08 | Anthony Liguori | OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) |
141 | 40021f08 | Anthony Liguori | #define PCI_DEVICE_GET_CLASS(obj) \
|
142 | 40021f08 | Anthony Liguori | OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) |
143 | 40021f08 | Anthony Liguori | |
144 | 40021f08 | Anthony Liguori | typedef struct PCIDeviceClass { |
145 | 40021f08 | Anthony Liguori | DeviceClass parent_class; |
146 | 40021f08 | Anthony Liguori | |
147 | 40021f08 | Anthony Liguori | int (*init)(PCIDevice *dev);
|
148 | 40021f08 | Anthony Liguori | PCIUnregisterFunc *exit; |
149 | 40021f08 | Anthony Liguori | PCIConfigReadFunc *config_read; |
150 | 40021f08 | Anthony Liguori | PCIConfigWriteFunc *config_write; |
151 | 40021f08 | Anthony Liguori | |
152 | 40021f08 | Anthony Liguori | uint16_t vendor_id; |
153 | 40021f08 | Anthony Liguori | uint16_t device_id; |
154 | 40021f08 | Anthony Liguori | uint8_t revision; |
155 | 40021f08 | Anthony Liguori | uint16_t class_id; |
156 | 40021f08 | Anthony Liguori | uint16_t subsystem_vendor_id; /* only for header type = 0 */
|
157 | 40021f08 | Anthony Liguori | uint16_t subsystem_id; /* only for header type = 0 */
|
158 | 40021f08 | Anthony Liguori | |
159 | 40021f08 | Anthony Liguori | /*
|
160 | 40021f08 | Anthony Liguori | * pci-to-pci bridge or normal device.
|
161 | 40021f08 | Anthony Liguori | * This doesn't mean pci host switch.
|
162 | 40021f08 | Anthony Liguori | * When card bus bridge is supported, this would be enhanced.
|
163 | 40021f08 | Anthony Liguori | */
|
164 | 40021f08 | Anthony Liguori | int is_bridge;
|
165 | 40021f08 | Anthony Liguori | |
166 | 40021f08 | Anthony Liguori | /* pcie stuff */
|
167 | 40021f08 | Anthony Liguori | int is_express; /* is this device pci express? */ |
168 | 40021f08 | Anthony Liguori | |
169 | 40021f08 | Anthony Liguori | /* device isn't hot-pluggable */
|
170 | 40021f08 | Anthony Liguori | int no_hotplug;
|
171 | 40021f08 | Anthony Liguori | |
172 | 40021f08 | Anthony Liguori | /* rom bar */
|
173 | 40021f08 | Anthony Liguori | const char *romfile; |
174 | 40021f08 | Anthony Liguori | } PCIDeviceClass; |
175 | 40021f08 | Anthony Liguori | |
176 | 87ecb68b | pbrook | struct PCIDevice {
|
177 | 6b1b92d3 | Paul Brook | DeviceState qdev; |
178 | 87ecb68b | pbrook | /* PCI config space */
|
179 | a9f49946 | Isaku Yamahata | uint8_t *config; |
180 | b7ee1603 | Michael S. Tsirkin | |
181 | ebabb67a | Stefan Weil | /* Used to enable config checks on load. Note that writable bits are
|
182 | bd4b65ee | Michael S. Tsirkin | * never checked even if set in cmask. */
|
183 | a9f49946 | Isaku Yamahata | uint8_t *cmask; |
184 | bd4b65ee | Michael S. Tsirkin | |
185 | b7ee1603 | Michael S. Tsirkin | /* Used to implement R/W bytes */
|
186 | a9f49946 | Isaku Yamahata | uint8_t *wmask; |
187 | 87ecb68b | pbrook | |
188 | 92ba5f51 | Isaku Yamahata | /* Used to implement RW1C(Write 1 to Clear) bytes */
|
189 | 92ba5f51 | Isaku Yamahata | uint8_t *w1cmask; |
190 | 92ba5f51 | Isaku Yamahata | |
191 | 6f4cbd39 | Michael S. Tsirkin | /* Used to allocate config space for capabilities. */
|
192 | a9f49946 | Isaku Yamahata | uint8_t *used; |
193 | 6f4cbd39 | Michael S. Tsirkin | |
194 | 87ecb68b | pbrook | /* the following fields are read only */
|
195 | 87ecb68b | pbrook | PCIBus *bus; |
196 | 54586bd1 | Gerd Hoffmann | uint32_t devfn; |
197 | 87ecb68b | pbrook | char name[64]; |
198 | 87ecb68b | pbrook | PCIIORegion io_regions[PCI_NUM_REGIONS]; |
199 | 87ecb68b | pbrook | |
200 | 87ecb68b | pbrook | /* do not access the following fields */
|
201 | 87ecb68b | pbrook | PCIConfigReadFunc *config_read; |
202 | 87ecb68b | pbrook | PCIConfigWriteFunc *config_write; |
203 | 87ecb68b | pbrook | |
204 | 87ecb68b | pbrook | /* IRQ objects for the INTA-INTD pins. */
|
205 | 87ecb68b | pbrook | qemu_irq *irq; |
206 | 87ecb68b | pbrook | |
207 | 87ecb68b | pbrook | /* Current IRQ levels. Used internally by the generic PCI code. */
|
208 | d036bb21 | Michael S. Tsirkin | uint8_t irq_state; |
209 | 02eb84d0 | Michael S. Tsirkin | |
210 | 02eb84d0 | Michael S. Tsirkin | /* Capability bits */
|
211 | 02eb84d0 | Michael S. Tsirkin | uint32_t cap_present; |
212 | 02eb84d0 | Michael S. Tsirkin | |
213 | 02eb84d0 | Michael S. Tsirkin | /* Offset of MSI-X capability in config space */
|
214 | 02eb84d0 | Michael S. Tsirkin | uint8_t msix_cap; |
215 | 02eb84d0 | Michael S. Tsirkin | |
216 | 02eb84d0 | Michael S. Tsirkin | /* MSI-X entries */
|
217 | 02eb84d0 | Michael S. Tsirkin | int msix_entries_nr;
|
218 | 02eb84d0 | Michael S. Tsirkin | |
219 | 02eb84d0 | Michael S. Tsirkin | /* Space to store MSIX table */
|
220 | 02eb84d0 | Michael S. Tsirkin | uint8_t *msix_table_page; |
221 | 02eb84d0 | Michael S. Tsirkin | /* MMIO index used to map MSIX table and pending bit entries. */
|
222 | 95524ae8 | Avi Kivity | MemoryRegion msix_mmio; |
223 | 02eb84d0 | Michael S. Tsirkin | /* Reference-count for entries actually in use by driver. */
|
224 | 02eb84d0 | Michael S. Tsirkin | unsigned *msix_entry_used;
|
225 | 02eb84d0 | Michael S. Tsirkin | /* Region including the MSI-X table */
|
226 | 02eb84d0 | Michael S. Tsirkin | uint32_t msix_bar_size; |
227 | 50322249 | Michael S. Tsirkin | /* MSIX function mask set or MSIX disabled */
|
228 | 50322249 | Michael S. Tsirkin | bool msix_function_masked;
|
229 | f16c4abf | Juan Quintela | /* Version id needed for VMState */
|
230 | f16c4abf | Juan Quintela | int32_t version_id; |
231 | c2039bd0 | Anthony Liguori | |
232 | e4c7d2ae | Isaku Yamahata | /* Offset of MSI capability in config space */
|
233 | e4c7d2ae | Isaku Yamahata | uint8_t msi_cap; |
234 | e4c7d2ae | Isaku Yamahata | |
235 | 0428527c | Isaku Yamahata | /* PCI Express */
|
236 | 0428527c | Isaku Yamahata | PCIExpressDevice exp; |
237 | 0428527c | Isaku Yamahata | |
238 | 1dc324d2 | Michael S. Tsirkin | /* SHPC */
|
239 | 1dc324d2 | Michael S. Tsirkin | SHPCDevice *shpc; |
240 | 1dc324d2 | Michael S. Tsirkin | |
241 | c2039bd0 | Anthony Liguori | /* Location of option rom */
|
242 | 8c52c8f3 | Gerd Hoffmann | char *romfile;
|
243 | 14caaf7f | Avi Kivity | bool has_rom;
|
244 | 14caaf7f | Avi Kivity | MemoryRegion rom; |
245 | 88169ddf | Gerd Hoffmann | uint32_t rom_bar; |
246 | 87ecb68b | pbrook | }; |
247 | 87ecb68b | pbrook | |
248 | e824b2cc | Avi Kivity | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
249 | e824b2cc | Avi Kivity | uint8_t attr, MemoryRegion *memory); |
250 | 16a96f28 | Avi Kivity | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
|
251 | 87ecb68b | pbrook | |
252 | ca77089d | Isaku Yamahata | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
|
253 | ca77089d | Isaku Yamahata | uint8_t offset, uint8_t size); |
254 | 6f4cbd39 | Michael S. Tsirkin | |
255 | 6f4cbd39 | Michael S. Tsirkin | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
|
256 | 6f4cbd39 | Michael S. Tsirkin | |
257 | 6f4cbd39 | Michael S. Tsirkin | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
258 | 6f4cbd39 | Michael S. Tsirkin | |
259 | 6f4cbd39 | Michael S. Tsirkin | |
260 | 87ecb68b | pbrook | uint32_t pci_default_read_config(PCIDevice *d, |
261 | 87ecb68b | pbrook | uint32_t address, int len);
|
262 | 87ecb68b | pbrook | void pci_default_write_config(PCIDevice *d,
|
263 | 87ecb68b | pbrook | uint32_t address, uint32_t val, int len);
|
264 | 87ecb68b | pbrook | void pci_device_save(PCIDevice *s, QEMUFile *f);
|
265 | 87ecb68b | pbrook | int pci_device_load(PCIDevice *s, QEMUFile *f);
|
266 | f5e6fed8 | Avi Kivity | MemoryRegion *pci_address_space(PCIDevice *dev); |
267 | e11d6439 | Richard Henderson | MemoryRegion *pci_address_space_io(PCIDevice *dev); |
268 | 87ecb68b | pbrook | |
269 | 5d4e84c8 | Juan Quintela | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
270 | 87ecb68b | pbrook | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
271 | e927d487 | Michael S. Tsirkin | |
272 | e927d487 | Michael S. Tsirkin | typedef enum { |
273 | e927d487 | Michael S. Tsirkin | PCI_HOTPLUG_DISABLED, |
274 | e927d487 | Michael S. Tsirkin | PCI_HOTPLUG_ENABLED, |
275 | e927d487 | Michael S. Tsirkin | PCI_COLDPLUG_ENABLED, |
276 | e927d487 | Michael S. Tsirkin | } PCIHotplugState; |
277 | e927d487 | Michael S. Tsirkin | |
278 | e927d487 | Michael S. Tsirkin | typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, |
279 | e927d487 | Michael S. Tsirkin | PCIHotplugState state); |
280 | 21eea4b3 | Gerd Hoffmann | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
|
281 | 1e39101c | Avi Kivity | const char *name, |
282 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem, |
283 | aee97b84 | Avi Kivity | MemoryRegion *address_space_io, |
284 | 1e39101c | Avi Kivity | uint8_t devfn_min); |
285 | 1e39101c | Avi Kivity | PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
286 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem, |
287 | aee97b84 | Avi Kivity | MemoryRegion *address_space_io, |
288 | aee97b84 | Avi Kivity | uint8_t devfn_min); |
289 | 21eea4b3 | Gerd Hoffmann | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
|
290 | 21eea4b3 | Gerd Hoffmann | void *irq_opaque, int nirq); |
291 | 9ddf8437 | Isaku Yamahata | int pci_bus_get_irq_level(PCIBus *bus, int irq_num); |
292 | 87c30546 | Isaku Yamahata | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
|
293 | 02e2da45 | Paul Brook | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
294 | 02e2da45 | Paul Brook | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
295 | 1e39101c | Avi Kivity | void *irq_opaque,
|
296 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem, |
297 | aee97b84 | Avi Kivity | MemoryRegion *address_space_io, |
298 | 1e39101c | Avi Kivity | uint8_t devfn_min, int nirq);
|
299 | 0ead87c8 | Isaku Yamahata | void pci_device_reset(PCIDevice *dev);
|
300 | 9bb33586 | Isaku Yamahata | void pci_bus_reset(PCIBus *bus);
|
301 | 87ecb68b | pbrook | |
302 | 5607c388 | Markus Armbruster | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
303 | 5607c388 | Markus Armbruster | const char *default_devaddr); |
304 | 07caea31 | Markus Armbruster | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
305 | 07caea31 | Markus Armbruster | const char *default_devaddr); |
306 | 87ecb68b | pbrook | int pci_bus_num(PCIBus *s);
|
307 | e822a52a | Isaku Yamahata | void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d)); |
308 | c469e1dd | Isaku Yamahata | PCIBus *pci_find_root_bus(int domain);
|
309 | e075e788 | Isaku Yamahata | int pci_find_domain(const PCIBus *bus); |
310 | 5256d8bf | Isaku Yamahata | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
|
311 | f3006dd1 | Isaku Yamahata | int pci_qdev_find_device(const char *id, PCIDevice **pdev); |
312 | 49bd1458 | Markus Armbruster | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); |
313 | 87ecb68b | pbrook | |
314 | e9283f8b | Jan Kiszka | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
315 | e9283f8b | Jan Kiszka | unsigned *slotp);
|
316 | 880345c4 | aliguori | |
317 | 4c92325b | Isaku Yamahata | void pci_device_deassert_intx(PCIDevice *dev);
|
318 | 4c92325b | Isaku Yamahata | |
319 | deb54399 | aliguori | static inline void |
320 | 64d50b8b | Michael S. Tsirkin | pci_set_byte(uint8_t *config, uint8_t val) |
321 | 64d50b8b | Michael S. Tsirkin | { |
322 | 64d50b8b | Michael S. Tsirkin | *config = val; |
323 | 64d50b8b | Michael S. Tsirkin | } |
324 | 64d50b8b | Michael S. Tsirkin | |
325 | 64d50b8b | Michael S. Tsirkin | static inline uint8_t |
326 | cb95c2e4 | Stefan Weil | pci_get_byte(const uint8_t *config)
|
327 | 64d50b8b | Michael S. Tsirkin | { |
328 | 64d50b8b | Michael S. Tsirkin | return *config;
|
329 | 64d50b8b | Michael S. Tsirkin | } |
330 | 64d50b8b | Michael S. Tsirkin | |
331 | 64d50b8b | Michael S. Tsirkin | static inline void |
332 | 14e12559 | Michael S. Tsirkin | pci_set_word(uint8_t *config, uint16_t val) |
333 | 14e12559 | Michael S. Tsirkin | { |
334 | 14e12559 | Michael S. Tsirkin | cpu_to_le16wu((uint16_t *)config, val); |
335 | 14e12559 | Michael S. Tsirkin | } |
336 | 14e12559 | Michael S. Tsirkin | |
337 | 14e12559 | Michael S. Tsirkin | static inline uint16_t |
338 | cb95c2e4 | Stefan Weil | pci_get_word(const uint8_t *config)
|
339 | 14e12559 | Michael S. Tsirkin | { |
340 | cb95c2e4 | Stefan Weil | return le16_to_cpupu((const uint16_t *)config); |
341 | 14e12559 | Michael S. Tsirkin | } |
342 | 14e12559 | Michael S. Tsirkin | |
343 | 14e12559 | Michael S. Tsirkin | static inline void |
344 | 14e12559 | Michael S. Tsirkin | pci_set_long(uint8_t *config, uint32_t val) |
345 | 14e12559 | Michael S. Tsirkin | { |
346 | 14e12559 | Michael S. Tsirkin | cpu_to_le32wu((uint32_t *)config, val); |
347 | 14e12559 | Michael S. Tsirkin | } |
348 | 14e12559 | Michael S. Tsirkin | |
349 | 14e12559 | Michael S. Tsirkin | static inline uint32_t |
350 | cb95c2e4 | Stefan Weil | pci_get_long(const uint8_t *config)
|
351 | 14e12559 | Michael S. Tsirkin | { |
352 | cb95c2e4 | Stefan Weil | return le32_to_cpupu((const uint32_t *)config); |
353 | 14e12559 | Michael S. Tsirkin | } |
354 | 14e12559 | Michael S. Tsirkin | |
355 | 14e12559 | Michael S. Tsirkin | static inline void |
356 | fb5ce7d2 | Isaku Yamahata | pci_set_quad(uint8_t *config, uint64_t val) |
357 | fb5ce7d2 | Isaku Yamahata | { |
358 | fb5ce7d2 | Isaku Yamahata | cpu_to_le64w((uint64_t *)config, val); |
359 | fb5ce7d2 | Isaku Yamahata | } |
360 | fb5ce7d2 | Isaku Yamahata | |
361 | fb5ce7d2 | Isaku Yamahata | static inline uint64_t |
362 | cb95c2e4 | Stefan Weil | pci_get_quad(const uint8_t *config)
|
363 | fb5ce7d2 | Isaku Yamahata | { |
364 | cb95c2e4 | Stefan Weil | return le64_to_cpup((const uint64_t *)config); |
365 | fb5ce7d2 | Isaku Yamahata | } |
366 | fb5ce7d2 | Isaku Yamahata | |
367 | fb5ce7d2 | Isaku Yamahata | static inline void |
368 | deb54399 | aliguori | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) |
369 | deb54399 | aliguori | { |
370 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
371 | deb54399 | aliguori | } |
372 | deb54399 | aliguori | |
373 | deb54399 | aliguori | static inline void |
374 | deb54399 | aliguori | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) |
375 | deb54399 | aliguori | { |
376 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
377 | deb54399 | aliguori | } |
378 | deb54399 | aliguori | |
379 | 173a543b | blueswir1 | static inline void |
380 | cf602c7b | Izik Eidus | pci_config_set_revision(uint8_t *pci_config, uint8_t val) |
381 | cf602c7b | Izik Eidus | { |
382 | cf602c7b | Izik Eidus | pci_set_byte(&pci_config[PCI_REVISION_ID], val); |
383 | cf602c7b | Izik Eidus | } |
384 | cf602c7b | Izik Eidus | |
385 | cf602c7b | Izik Eidus | static inline void |
386 | 173a543b | blueswir1 | pci_config_set_class(uint8_t *pci_config, uint16_t val) |
387 | 173a543b | blueswir1 | { |
388 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
389 | 173a543b | blueswir1 | } |
390 | 173a543b | blueswir1 | |
391 | cf602c7b | Izik Eidus | static inline void |
392 | cf602c7b | Izik Eidus | pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) |
393 | cf602c7b | Izik Eidus | { |
394 | cf602c7b | Izik Eidus | pci_set_byte(&pci_config[PCI_CLASS_PROG], val); |
395 | cf602c7b | Izik Eidus | } |
396 | cf602c7b | Izik Eidus | |
397 | cf602c7b | Izik Eidus | static inline void |
398 | cf602c7b | Izik Eidus | pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) |
399 | cf602c7b | Izik Eidus | { |
400 | cf602c7b | Izik Eidus | pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); |
401 | cf602c7b | Izik Eidus | } |
402 | cf602c7b | Izik Eidus | |
403 | aabcf526 | Isaku Yamahata | /*
|
404 | aabcf526 | Isaku Yamahata | * helper functions to do bit mask operation on configuration space.
|
405 | aabcf526 | Isaku Yamahata | * Just to set bit, use test-and-set and discard returned value.
|
406 | aabcf526 | Isaku Yamahata | * Just to clear bit, use test-and-clear and discard returned value.
|
407 | aabcf526 | Isaku Yamahata | * NOTE: They aren't atomic.
|
408 | aabcf526 | Isaku Yamahata | */
|
409 | aabcf526 | Isaku Yamahata | static inline uint8_t |
410 | aabcf526 | Isaku Yamahata | pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) |
411 | aabcf526 | Isaku Yamahata | { |
412 | aabcf526 | Isaku Yamahata | uint8_t val = pci_get_byte(config); |
413 | aabcf526 | Isaku Yamahata | pci_set_byte(config, val & ~mask); |
414 | aabcf526 | Isaku Yamahata | return val & mask;
|
415 | aabcf526 | Isaku Yamahata | } |
416 | aabcf526 | Isaku Yamahata | |
417 | aabcf526 | Isaku Yamahata | static inline uint8_t |
418 | aabcf526 | Isaku Yamahata | pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) |
419 | aabcf526 | Isaku Yamahata | { |
420 | aabcf526 | Isaku Yamahata | uint8_t val = pci_get_byte(config); |
421 | aabcf526 | Isaku Yamahata | pci_set_byte(config, val | mask); |
422 | aabcf526 | Isaku Yamahata | return val & mask;
|
423 | aabcf526 | Isaku Yamahata | } |
424 | aabcf526 | Isaku Yamahata | |
425 | aabcf526 | Isaku Yamahata | static inline uint16_t |
426 | aabcf526 | Isaku Yamahata | pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) |
427 | aabcf526 | Isaku Yamahata | { |
428 | aabcf526 | Isaku Yamahata | uint16_t val = pci_get_word(config); |
429 | aabcf526 | Isaku Yamahata | pci_set_word(config, val & ~mask); |
430 | aabcf526 | Isaku Yamahata | return val & mask;
|
431 | aabcf526 | Isaku Yamahata | } |
432 | aabcf526 | Isaku Yamahata | |
433 | aabcf526 | Isaku Yamahata | static inline uint16_t |
434 | aabcf526 | Isaku Yamahata | pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) |
435 | aabcf526 | Isaku Yamahata | { |
436 | aabcf526 | Isaku Yamahata | uint16_t val = pci_get_word(config); |
437 | aabcf526 | Isaku Yamahata | pci_set_word(config, val | mask); |
438 | aabcf526 | Isaku Yamahata | return val & mask;
|
439 | aabcf526 | Isaku Yamahata | } |
440 | aabcf526 | Isaku Yamahata | |
441 | aabcf526 | Isaku Yamahata | static inline uint32_t |
442 | aabcf526 | Isaku Yamahata | pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) |
443 | aabcf526 | Isaku Yamahata | { |
444 | aabcf526 | Isaku Yamahata | uint32_t val = pci_get_long(config); |
445 | aabcf526 | Isaku Yamahata | pci_set_long(config, val & ~mask); |
446 | aabcf526 | Isaku Yamahata | return val & mask;
|
447 | aabcf526 | Isaku Yamahata | } |
448 | aabcf526 | Isaku Yamahata | |
449 | aabcf526 | Isaku Yamahata | static inline uint32_t |
450 | aabcf526 | Isaku Yamahata | pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) |
451 | aabcf526 | Isaku Yamahata | { |
452 | aabcf526 | Isaku Yamahata | uint32_t val = pci_get_long(config); |
453 | aabcf526 | Isaku Yamahata | pci_set_long(config, val | mask); |
454 | aabcf526 | Isaku Yamahata | return val & mask;
|
455 | aabcf526 | Isaku Yamahata | } |
456 | aabcf526 | Isaku Yamahata | |
457 | aabcf526 | Isaku Yamahata | static inline uint64_t |
458 | aabcf526 | Isaku Yamahata | pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) |
459 | aabcf526 | Isaku Yamahata | { |
460 | aabcf526 | Isaku Yamahata | uint64_t val = pci_get_quad(config); |
461 | aabcf526 | Isaku Yamahata | pci_set_quad(config, val & ~mask); |
462 | aabcf526 | Isaku Yamahata | return val & mask;
|
463 | aabcf526 | Isaku Yamahata | } |
464 | aabcf526 | Isaku Yamahata | |
465 | aabcf526 | Isaku Yamahata | static inline uint64_t |
466 | aabcf526 | Isaku Yamahata | pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) |
467 | aabcf526 | Isaku Yamahata | { |
468 | aabcf526 | Isaku Yamahata | uint64_t val = pci_get_quad(config); |
469 | aabcf526 | Isaku Yamahata | pci_set_quad(config, val | mask); |
470 | aabcf526 | Isaku Yamahata | return val & mask;
|
471 | aabcf526 | Isaku Yamahata | } |
472 | aabcf526 | Isaku Yamahata | |
473 | c9f50cea | Michael S. Tsirkin | /* Access a register specified by a mask */
|
474 | c9f50cea | Michael S. Tsirkin | static inline void |
475 | c9f50cea | Michael S. Tsirkin | pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) |
476 | c9f50cea | Michael S. Tsirkin | { |
477 | c9f50cea | Michael S. Tsirkin | uint8_t val = pci_get_byte(config); |
478 | c9f50cea | Michael S. Tsirkin | uint8_t rval = reg << (ffs(mask) - 1);
|
479 | c9f50cea | Michael S. Tsirkin | pci_set_byte(config, (~mask & val) | (mask & rval)); |
480 | c9f50cea | Michael S. Tsirkin | } |
481 | c9f50cea | Michael S. Tsirkin | |
482 | c9f50cea | Michael S. Tsirkin | static inline uint8_t |
483 | c9f50cea | Michael S. Tsirkin | pci_get_byte_by_mask(uint8_t *config, uint8_t mask) |
484 | c9f50cea | Michael S. Tsirkin | { |
485 | c9f50cea | Michael S. Tsirkin | uint8_t val = pci_get_byte(config); |
486 | c9f50cea | Michael S. Tsirkin | return (val & mask) >> (ffs(mask) - 1); |
487 | c9f50cea | Michael S. Tsirkin | } |
488 | c9f50cea | Michael S. Tsirkin | |
489 | c9f50cea | Michael S. Tsirkin | static inline void |
490 | c9f50cea | Michael S. Tsirkin | pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) |
491 | c9f50cea | Michael S. Tsirkin | { |
492 | c9f50cea | Michael S. Tsirkin | uint16_t val = pci_get_word(config); |
493 | c9f50cea | Michael S. Tsirkin | uint16_t rval = reg << (ffs(mask) - 1);
|
494 | c9f50cea | Michael S. Tsirkin | pci_set_word(config, (~mask & val) | (mask & rval)); |
495 | c9f50cea | Michael S. Tsirkin | } |
496 | c9f50cea | Michael S. Tsirkin | |
497 | c9f50cea | Michael S. Tsirkin | static inline uint16_t |
498 | c9f50cea | Michael S. Tsirkin | pci_get_word_by_mask(uint8_t *config, uint16_t mask) |
499 | c9f50cea | Michael S. Tsirkin | { |
500 | c9f50cea | Michael S. Tsirkin | uint16_t val = pci_get_word(config); |
501 | c9f50cea | Michael S. Tsirkin | return (val & mask) >> (ffs(mask) - 1); |
502 | c9f50cea | Michael S. Tsirkin | } |
503 | c9f50cea | Michael S. Tsirkin | |
504 | c9f50cea | Michael S. Tsirkin | static inline void |
505 | c9f50cea | Michael S. Tsirkin | pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) |
506 | c9f50cea | Michael S. Tsirkin | { |
507 | c9f50cea | Michael S. Tsirkin | uint32_t val = pci_get_long(config); |
508 | c9f50cea | Michael S. Tsirkin | uint32_t rval = reg << (ffs(mask) - 1);
|
509 | c9f50cea | Michael S. Tsirkin | pci_set_long(config, (~mask & val) | (mask & rval)); |
510 | c9f50cea | Michael S. Tsirkin | } |
511 | c9f50cea | Michael S. Tsirkin | |
512 | c9f50cea | Michael S. Tsirkin | static inline uint32_t |
513 | c9f50cea | Michael S. Tsirkin | pci_get_long_by_mask(uint8_t *config, uint32_t mask) |
514 | c9f50cea | Michael S. Tsirkin | { |
515 | c9f50cea | Michael S. Tsirkin | uint32_t val = pci_get_long(config); |
516 | c9f50cea | Michael S. Tsirkin | return (val & mask) >> (ffs(mask) - 1); |
517 | c9f50cea | Michael S. Tsirkin | } |
518 | c9f50cea | Michael S. Tsirkin | |
519 | c9f50cea | Michael S. Tsirkin | static inline void |
520 | c9f50cea | Michael S. Tsirkin | pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) |
521 | c9f50cea | Michael S. Tsirkin | { |
522 | c9f50cea | Michael S. Tsirkin | uint64_t val = pci_get_quad(config); |
523 | c9f50cea | Michael S. Tsirkin | uint64_t rval = reg << (ffs(mask) - 1);
|
524 | c9f50cea | Michael S. Tsirkin | pci_set_quad(config, (~mask & val) | (mask & rval)); |
525 | c9f50cea | Michael S. Tsirkin | } |
526 | c9f50cea | Michael S. Tsirkin | |
527 | c9f50cea | Michael S. Tsirkin | static inline uint64_t |
528 | c9f50cea | Michael S. Tsirkin | pci_get_quad_by_mask(uint8_t *config, uint64_t mask) |
529 | c9f50cea | Michael S. Tsirkin | { |
530 | c9f50cea | Michael S. Tsirkin | uint64_t val = pci_get_quad(config); |
531 | c9f50cea | Michael S. Tsirkin | return (val & mask) >> (ffs(mask) - 1); |
532 | c9f50cea | Michael S. Tsirkin | } |
533 | c9f50cea | Michael S. Tsirkin | |
534 | 49823868 | Isaku Yamahata | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
535 | 49823868 | Isaku Yamahata | const char *name); |
536 | 49823868 | Isaku Yamahata | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
|
537 | 49823868 | Isaku Yamahata | bool multifunction,
|
538 | 49823868 | Isaku Yamahata | const char *name); |
539 | 499cf102 | Markus Armbruster | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
540 | 6b1b92d3 | Paul Brook | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
541 | 6b1b92d3 | Paul Brook | |
542 | 3c18685f | Isaku Yamahata | static inline int pci_is_express(const PCIDevice *d) |
543 | a9f49946 | Isaku Yamahata | { |
544 | a9f49946 | Isaku Yamahata | return d->cap_present & QEMU_PCI_CAP_EXPRESS;
|
545 | a9f49946 | Isaku Yamahata | } |
546 | a9f49946 | Isaku Yamahata | |
547 | 3c18685f | Isaku Yamahata | static inline uint32_t pci_config_size(const PCIDevice *d) |
548 | a9f49946 | Isaku Yamahata | { |
549 | a9f49946 | Isaku Yamahata | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
|
550 | a9f49946 | Isaku Yamahata | } |
551 | a9f49946 | Isaku Yamahata | |
552 | ec174575 | David Gibson | /* DMA access functions */
|
553 | ec174575 | David Gibson | static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, |
554 | ec174575 | David Gibson | void *buf, dma_addr_t len, DMADirection dir)
|
555 | ec174575 | David Gibson | { |
556 | ec174575 | David Gibson | cpu_physical_memory_rw(addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE); |
557 | ec174575 | David Gibson | return 0; |
558 | ec174575 | David Gibson | } |
559 | ec174575 | David Gibson | |
560 | ec174575 | David Gibson | static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, |
561 | ec174575 | David Gibson | void *buf, dma_addr_t len)
|
562 | ec174575 | David Gibson | { |
563 | ec174575 | David Gibson | return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
|
564 | ec174575 | David Gibson | } |
565 | ec174575 | David Gibson | |
566 | ec174575 | David Gibson | static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, |
567 | ec174575 | David Gibson | const void *buf, dma_addr_t len) |
568 | ec174575 | David Gibson | { |
569 | ec174575 | David Gibson | return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); |
570 | ec174575 | David Gibson | } |
571 | ec174575 | David Gibson | |
572 | ec174575 | David Gibson | #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
|
573 | ec174575 | David Gibson | static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ |
574 | ec174575 | David Gibson | dma_addr_t addr) \ |
575 | ec174575 | David Gibson | { \ |
576 | ec174575 | David Gibson | return ld##_l##_phys(addr); \ |
577 | ec174575 | David Gibson | } \ |
578 | ec174575 | David Gibson | static inline void st##_s##_pci_dma(PCIDevice *dev, \ |
579 | ec174575 | David Gibson | dma_addr_t addr, uint##_bits##_t val) \ |
580 | ec174575 | David Gibson | { \ |
581 | ec174575 | David Gibson | st##_s##_phys(addr, val); \ |
582 | ec174575 | David Gibson | } |
583 | ec174575 | David Gibson | |
584 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(ub, b, 8);
|
585 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
|
586 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
|
587 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
|
588 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
|
589 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
|
590 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
|
591 | ec174575 | David Gibson | |
592 | ec174575 | David Gibson | #undef PCI_DMA_DEFINE_LDST
|
593 | ec174575 | David Gibson | |
594 | ec174575 | David Gibson | static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, |
595 | ec174575 | David Gibson | dma_addr_t *plen, DMADirection dir) |
596 | ec174575 | David Gibson | { |
597 | ec174575 | David Gibson | target_phys_addr_t len = *plen; |
598 | ec174575 | David Gibson | void *buf;
|
599 | ec174575 | David Gibson | |
600 | ec174575 | David Gibson | buf = cpu_physical_memory_map(addr, &len, dir == DMA_DIRECTION_FROM_DEVICE); |
601 | ec174575 | David Gibson | *plen = len; |
602 | ec174575 | David Gibson | return buf;
|
603 | ec174575 | David Gibson | } |
604 | ec174575 | David Gibson | |
605 | ec174575 | David Gibson | static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, |
606 | ec174575 | David Gibson | DMADirection dir, dma_addr_t access_len) |
607 | ec174575 | David Gibson | { |
608 | ec174575 | David Gibson | cpu_physical_memory_unmap(buffer, len, dir == DMA_DIRECTION_FROM_DEVICE, |
609 | ec174575 | David Gibson | access_len); |
610 | ec174575 | David Gibson | } |
611 | ec174575 | David Gibson | |
612 | ec174575 | David Gibson | static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, |
613 | ec174575 | David Gibson | int alloc_hint)
|
614 | ec174575 | David Gibson | { |
615 | ec174575 | David Gibson | qemu_sglist_init(qsg, alloc_hint); |
616 | ec174575 | David Gibson | } |
617 | ec174575 | David Gibson | |
618 | 701a8f76 | Paolo Bonzini | extern const VMStateDescription vmstate_pci_device; |
619 | 701a8f76 | Paolo Bonzini | |
620 | 701a8f76 | Paolo Bonzini | #define VMSTATE_PCI_DEVICE(_field, _state) { \
|
621 | 701a8f76 | Paolo Bonzini | .name = (stringify(_field)), \ |
622 | 701a8f76 | Paolo Bonzini | .size = sizeof(PCIDevice), \
|
623 | 701a8f76 | Paolo Bonzini | .vmsd = &vmstate_pci_device, \ |
624 | 701a8f76 | Paolo Bonzini | .flags = VMS_STRUCT, \ |
625 | 701a8f76 | Paolo Bonzini | .offset = vmstate_offset_value(_state, _field, PCIDevice), \ |
626 | 701a8f76 | Paolo Bonzini | } |
627 | 701a8f76 | Paolo Bonzini | |
628 | 701a8f76 | Paolo Bonzini | #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
|
629 | 701a8f76 | Paolo Bonzini | .name = (stringify(_field)), \ |
630 | 701a8f76 | Paolo Bonzini | .size = sizeof(PCIDevice), \
|
631 | 701a8f76 | Paolo Bonzini | .vmsd = &vmstate_pci_device, \ |
632 | 701a8f76 | Paolo Bonzini | .flags = VMS_STRUCT|VMS_POINTER, \ |
633 | 701a8f76 | Paolo Bonzini | .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ |
634 | 701a8f76 | Paolo Bonzini | } |
635 | 701a8f76 | Paolo Bonzini | |
636 | 87ecb68b | pbrook | #endif |