root / hw / mc146818rtc.c @ 4be403c8
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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU MC146818 RTC emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sysemu.h" |
27 | 1d914fa0 | Isaku Yamahata | #include "mc146818rtc.h" |
28 | 80cabfad | bellard | |
29 | d362e757 | Jan Kiszka | #ifdef TARGET_I386
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30 | d362e757 | Jan Kiszka | #include "apic.h" |
31 | d362e757 | Jan Kiszka | #endif
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32 | d362e757 | Jan Kiszka | |
33 | 80cabfad | bellard | //#define DEBUG_CMOS
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34 | aa6f63ff | Blue Swirl | //#define DEBUG_COALESCED
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35 | 80cabfad | bellard | |
36 | ec51e364 | Isaku Yamahata | #ifdef DEBUG_CMOS
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37 | ec51e364 | Isaku Yamahata | # define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
38 | ec51e364 | Isaku Yamahata | #else
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39 | ec51e364 | Isaku Yamahata | # define CMOS_DPRINTF(format, ...) do { } while (0) |
40 | ec51e364 | Isaku Yamahata | #endif
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41 | ec51e364 | Isaku Yamahata | |
42 | aa6f63ff | Blue Swirl | #ifdef DEBUG_COALESCED
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43 | aa6f63ff | Blue Swirl | # define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__) |
44 | aa6f63ff | Blue Swirl | #else
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45 | aa6f63ff | Blue Swirl | # define DPRINTF_C(format, ...) do { } while (0) |
46 | aa6f63ff | Blue Swirl | #endif
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47 | aa6f63ff | Blue Swirl | |
48 | 56038ef6 | Yang Zhang | #define NSEC_PER_SEC 1000000000LL |
49 | 00cf5774 | Paolo Bonzini | #define SEC_PER_MIN 60 |
50 | 00cf5774 | Paolo Bonzini | #define MIN_PER_HOUR 60 |
51 | 00cf5774 | Paolo Bonzini | #define SEC_PER_HOUR 3600 |
52 | 00cf5774 | Paolo Bonzini | #define HOUR_PER_DAY 24 |
53 | 00cf5774 | Paolo Bonzini | #define SEC_PER_DAY 86400 |
54 | 56038ef6 | Yang Zhang | |
55 | dd17765b | Gleb Natapov | #define RTC_REINJECT_ON_ACK_COUNT 20 |
56 | e46deaba | Paolo Bonzini | #define RTC_CLOCK_RATE 32768 |
57 | 56038ef6 | Yang Zhang | #define UIP_HOLD_LENGTH (8 * NSEC_PER_SEC / 32768) |
58 | ba32edab | Gleb Natapov | |
59 | 1d914fa0 | Isaku Yamahata | typedef struct RTCState { |
60 | 32e0c826 | Gerd Hoffmann | ISADevice dev; |
61 | b2c5009b | Richard Henderson | MemoryRegion io; |
62 | dff38e7b | bellard | uint8_t cmos_data[128];
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63 | dff38e7b | bellard | uint8_t cmos_index; |
64 | 32e0c826 | Gerd Hoffmann | int32_t base_year; |
65 | 56038ef6 | Yang Zhang | uint64_t base_rtc; |
66 | 56038ef6 | Yang Zhang | uint64_t last_update; |
67 | 56038ef6 | Yang Zhang | int64_t offset; |
68 | d537cf6c | pbrook | qemu_irq irq; |
69 | 100d9891 | aurel32 | qemu_irq sqw_irq; |
70 | 18c6e2ff | ths | int it_shift;
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71 | dff38e7b | bellard | /* periodic timer */
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72 | dff38e7b | bellard | QEMUTimer *periodic_timer; |
73 | dff38e7b | bellard | int64_t next_periodic_time; |
74 | 56038ef6 | Yang Zhang | /* update-ended timer */
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75 | 56038ef6 | Yang Zhang | QEMUTimer *update_timer; |
76 | 00cf5774 | Paolo Bonzini | uint64_t next_alarm_time; |
77 | ba32edab | Gleb Natapov | uint16_t irq_reinject_on_ack_count; |
78 | 73822ec8 | aliguori | uint32_t irq_coalesced; |
79 | 73822ec8 | aliguori | uint32_t period; |
80 | 93b66569 | aliguori | QEMUTimer *coalesced_timer; |
81 | 17604dac | Jan Kiszka | Notifier clock_reset_notifier; |
82 | 433acf0d | Jan Kiszka | LostTickPolicy lost_tick_policy; |
83 | da98c8eb | Gerd Hoffmann | Notifier suspend_notifier; |
84 | 1d914fa0 | Isaku Yamahata | } RTCState; |
85 | dff38e7b | bellard | |
86 | dff38e7b | bellard | static void rtc_set_time(RTCState *s); |
87 | 56038ef6 | Yang Zhang | static void rtc_update_time(RTCState *s); |
88 | e2826cf4 | Paolo Bonzini | static void rtc_set_cmos(RTCState *s, const struct tm *tm); |
89 | 56038ef6 | Yang Zhang | static inline int rtc_from_bcd(RTCState *s, int a); |
90 | 00cf5774 | Paolo Bonzini | static uint64_t get_next_alarm(RTCState *s);
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91 | 56038ef6 | Yang Zhang | |
92 | 41a9b8b2 | Yang Zhang | static inline bool rtc_running(RTCState *s) |
93 | 41a9b8b2 | Yang Zhang | { |
94 | 41a9b8b2 | Yang Zhang | return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
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95 | 41a9b8b2 | Yang Zhang | (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20); |
96 | 41a9b8b2 | Yang Zhang | } |
97 | 41a9b8b2 | Yang Zhang | |
98 | 56038ef6 | Yang Zhang | static uint64_t get_guest_rtc_ns(RTCState *s)
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99 | 56038ef6 | Yang Zhang | { |
100 | 56038ef6 | Yang Zhang | uint64_t guest_rtc; |
101 | 56038ef6 | Yang Zhang | uint64_t guest_clock = qemu_get_clock_ns(rtc_clock); |
102 | 56038ef6 | Yang Zhang | |
103 | 56038ef6 | Yang Zhang | guest_rtc = s->base_rtc * NSEC_PER_SEC |
104 | 56038ef6 | Yang Zhang | + guest_clock - s->last_update + s->offset; |
105 | 56038ef6 | Yang Zhang | return guest_rtc;
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106 | 56038ef6 | Yang Zhang | } |
107 | dff38e7b | bellard | |
108 | 93b66569 | aliguori | #ifdef TARGET_I386
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109 | 93b66569 | aliguori | static void rtc_coalesced_timer_update(RTCState *s) |
110 | 93b66569 | aliguori | { |
111 | 93b66569 | aliguori | if (s->irq_coalesced == 0) { |
112 | 93b66569 | aliguori | qemu_del_timer(s->coalesced_timer); |
113 | 93b66569 | aliguori | } else {
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114 | 93b66569 | aliguori | /* divide each RTC interval to 2 - 8 smaller intervals */
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115 | 93b66569 | aliguori | int c = MIN(s->irq_coalesced, 7) + 1; |
116 | 74475455 | Paolo Bonzini | int64_t next_clock = qemu_get_clock_ns(rtc_clock) + |
117 | e46deaba | Paolo Bonzini | muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE); |
118 | 93b66569 | aliguori | qemu_mod_timer(s->coalesced_timer, next_clock); |
119 | 93b66569 | aliguori | } |
120 | 93b66569 | aliguori | } |
121 | 93b66569 | aliguori | |
122 | 93b66569 | aliguori | static void rtc_coalesced_timer(void *opaque) |
123 | 93b66569 | aliguori | { |
124 | 93b66569 | aliguori | RTCState *s = opaque; |
125 | 93b66569 | aliguori | |
126 | 93b66569 | aliguori | if (s->irq_coalesced != 0) { |
127 | 93b66569 | aliguori | apic_reset_irq_delivered(); |
128 | 93b66569 | aliguori | s->cmos_data[RTC_REG_C] |= 0xc0;
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129 | aa6f63ff | Blue Swirl | DPRINTF_C("cmos: injecting from timer\n");
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130 | 7d932dfd | Jan Kiszka | qemu_irq_raise(s->irq); |
131 | 93b66569 | aliguori | if (apic_get_irq_delivered()) {
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132 | 93b66569 | aliguori | s->irq_coalesced--; |
133 | aa6f63ff | Blue Swirl | DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
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134 | aa6f63ff | Blue Swirl | s->irq_coalesced); |
135 | 93b66569 | aliguori | } |
136 | 93b66569 | aliguori | } |
137 | 93b66569 | aliguori | |
138 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
139 | 93b66569 | aliguori | } |
140 | 93b66569 | aliguori | #endif
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141 | 93b66569 | aliguori | |
142 | 56038ef6 | Yang Zhang | /* handle periodic timer */
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143 | c4c18e24 | Yang Zhang | static void periodic_timer_update(RTCState *s, int64_t current_time) |
144 | dff38e7b | bellard | { |
145 | dff38e7b | bellard | int period_code, period;
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146 | dff38e7b | bellard | int64_t cur_clock, next_irq_clock; |
147 | dff38e7b | bellard | |
148 | dff38e7b | bellard | period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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149 | 100d9891 | aurel32 | if (period_code != 0 |
150 | 7d932dfd | Jan Kiszka | && ((s->cmos_data[RTC_REG_B] & REG_B_PIE) |
151 | 100d9891 | aurel32 | || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { |
152 | dff38e7b | bellard | if (period_code <= 2) |
153 | dff38e7b | bellard | period_code += 7;
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154 | dff38e7b | bellard | /* period in 32 Khz cycles */
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155 | dff38e7b | bellard | period = 1 << (period_code - 1); |
156 | 73822ec8 | aliguori | #ifdef TARGET_I386
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157 | aa6f63ff | Blue Swirl | if (period != s->period) {
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158 | 73822ec8 | aliguori | s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
159 | aa6f63ff | Blue Swirl | DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
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160 | aa6f63ff | Blue Swirl | } |
161 | 73822ec8 | aliguori | s->period = period; |
162 | 73822ec8 | aliguori | #endif
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163 | dff38e7b | bellard | /* compute 32 khz clock */
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164 | e46deaba | Paolo Bonzini | cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec()); |
165 | dff38e7b | bellard | next_irq_clock = (cur_clock & ~(period - 1)) + period;
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166 | 6875204c | Jan Kiszka | s->next_periodic_time = |
167 | e46deaba | Paolo Bonzini | muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
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168 | dff38e7b | bellard | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
169 | dff38e7b | bellard | } else {
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170 | 73822ec8 | aliguori | #ifdef TARGET_I386
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171 | 73822ec8 | aliguori | s->irq_coalesced = 0;
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172 | 73822ec8 | aliguori | #endif
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173 | dff38e7b | bellard | qemu_del_timer(s->periodic_timer); |
174 | dff38e7b | bellard | } |
175 | dff38e7b | bellard | } |
176 | dff38e7b | bellard | |
177 | dff38e7b | bellard | static void rtc_periodic_timer(void *opaque) |
178 | dff38e7b | bellard | { |
179 | dff38e7b | bellard | RTCState *s = opaque; |
180 | dff38e7b | bellard | |
181 | c4c18e24 | Yang Zhang | periodic_timer_update(s, s->next_periodic_time); |
182 | 663447d4 | Paolo Bonzini | s->cmos_data[RTC_REG_C] |= REG_C_PF; |
183 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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184 | 663447d4 | Paolo Bonzini | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
185 | 93b66569 | aliguori | #ifdef TARGET_I386
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186 | 433acf0d | Jan Kiszka | if (s->lost_tick_policy == LOST_TICK_SLEW) {
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187 | ba32edab | Gleb Natapov | if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
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188 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count = 0;
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189 | 93b66569 | aliguori | apic_reset_irq_delivered(); |
190 | 7d932dfd | Jan Kiszka | qemu_irq_raise(s->irq); |
191 | 93b66569 | aliguori | if (!apic_get_irq_delivered()) {
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192 | 93b66569 | aliguori | s->irq_coalesced++; |
193 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
194 | aa6f63ff | Blue Swirl | DPRINTF_C("cmos: coalesced irqs increased to %d\n",
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195 | aa6f63ff | Blue Swirl | s->irq_coalesced); |
196 | 93b66569 | aliguori | } |
197 | 93b66569 | aliguori | } else
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198 | 93b66569 | aliguori | #endif
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199 | 7d932dfd | Jan Kiszka | qemu_irq_raise(s->irq); |
200 | 100d9891 | aurel32 | } |
201 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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202 | 100d9891 | aurel32 | /* Not square wave at all but we don't want 2048Hz interrupts!
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203 | 100d9891 | aurel32 | Must be seen as a pulse. */
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204 | 100d9891 | aurel32 | qemu_irq_raise(s->sqw_irq); |
205 | 100d9891 | aurel32 | } |
206 | dff38e7b | bellard | } |
207 | 80cabfad | bellard | |
208 | 56038ef6 | Yang Zhang | /* handle update-ended timer */
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209 | 56038ef6 | Yang Zhang | static void check_update_timer(RTCState *s) |
210 | 56038ef6 | Yang Zhang | { |
211 | 56038ef6 | Yang Zhang | uint64_t next_update_time; |
212 | 56038ef6 | Yang Zhang | uint64_t guest_nsec; |
213 | 00cf5774 | Paolo Bonzini | int next_alarm_sec;
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214 | 56038ef6 | Yang Zhang | |
215 | 41a9b8b2 | Yang Zhang | /* From the data sheet: "Holding the dividers in reset prevents
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216 | 41a9b8b2 | Yang Zhang | * interrupts from operating, while setting the SET bit allows"
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217 | 41a9b8b2 | Yang Zhang | * them to occur. However, it will prevent an alarm interrupt
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218 | 41a9b8b2 | Yang Zhang | * from occurring, because the time of day is not updated.
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219 | 56038ef6 | Yang Zhang | */
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220 | 41a9b8b2 | Yang Zhang | if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) { |
221 | 41a9b8b2 | Yang Zhang | qemu_del_timer(s->update_timer); |
222 | 41a9b8b2 | Yang Zhang | return;
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223 | 41a9b8b2 | Yang Zhang | } |
224 | 56038ef6 | Yang Zhang | if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
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225 | 56038ef6 | Yang Zhang | (s->cmos_data[RTC_REG_B] & REG_B_SET)) { |
226 | 56038ef6 | Yang Zhang | qemu_del_timer(s->update_timer); |
227 | 56038ef6 | Yang Zhang | return;
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228 | 56038ef6 | Yang Zhang | } |
229 | 56038ef6 | Yang Zhang | if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
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230 | 56038ef6 | Yang Zhang | (s->cmos_data[RTC_REG_C] & REG_C_AF)) { |
231 | 56038ef6 | Yang Zhang | qemu_del_timer(s->update_timer); |
232 | 56038ef6 | Yang Zhang | return;
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233 | 56038ef6 | Yang Zhang | } |
234 | 56038ef6 | Yang Zhang | |
235 | 56038ef6 | Yang Zhang | guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC; |
236 | 00cf5774 | Paolo Bonzini | /* if UF is clear, reprogram to next second */
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237 | 56038ef6 | Yang Zhang | next_update_time = qemu_get_clock_ns(rtc_clock) |
238 | 56038ef6 | Yang Zhang | + NSEC_PER_SEC - guest_nsec; |
239 | 00cf5774 | Paolo Bonzini | |
240 | 00cf5774 | Paolo Bonzini | /* Compute time of next alarm. One second is already accounted
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241 | 00cf5774 | Paolo Bonzini | * for in next_update_time.
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242 | 00cf5774 | Paolo Bonzini | */
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243 | 00cf5774 | Paolo Bonzini | next_alarm_sec = get_next_alarm(s); |
244 | 00cf5774 | Paolo Bonzini | s->next_alarm_time = next_update_time + (next_alarm_sec - 1) * NSEC_PER_SEC;
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245 | 00cf5774 | Paolo Bonzini | |
246 | 00cf5774 | Paolo Bonzini | if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
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247 | 00cf5774 | Paolo Bonzini | /* UF is set, but AF is clear. Program the timer to target
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248 | 00cf5774 | Paolo Bonzini | * the alarm time. */
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249 | 00cf5774 | Paolo Bonzini | next_update_time = s->next_alarm_time; |
250 | 00cf5774 | Paolo Bonzini | } |
251 | 56038ef6 | Yang Zhang | if (next_update_time != qemu_timer_expire_time_ns(s->update_timer)) {
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252 | 56038ef6 | Yang Zhang | qemu_mod_timer(s->update_timer, next_update_time); |
253 | 56038ef6 | Yang Zhang | } |
254 | 56038ef6 | Yang Zhang | } |
255 | 56038ef6 | Yang Zhang | |
256 | 56038ef6 | Yang Zhang | static inline uint8_t convert_hour(RTCState *s, uint8_t hour) |
257 | 56038ef6 | Yang Zhang | { |
258 | 56038ef6 | Yang Zhang | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
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259 | 56038ef6 | Yang Zhang | hour %= 12;
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260 | 56038ef6 | Yang Zhang | if (s->cmos_data[RTC_HOURS] & 0x80) { |
261 | 56038ef6 | Yang Zhang | hour += 12;
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262 | 56038ef6 | Yang Zhang | } |
263 | 56038ef6 | Yang Zhang | } |
264 | 56038ef6 | Yang Zhang | return hour;
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265 | 56038ef6 | Yang Zhang | } |
266 | 56038ef6 | Yang Zhang | |
267 | 00cf5774 | Paolo Bonzini | static uint64_t get_next_alarm(RTCState *s)
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268 | 56038ef6 | Yang Zhang | { |
269 | 00cf5774 | Paolo Bonzini | int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec; |
270 | 00cf5774 | Paolo Bonzini | int32_t hour, min, sec; |
271 | 00cf5774 | Paolo Bonzini | |
272 | 00cf5774 | Paolo Bonzini | rtc_update_time(s); |
273 | 56038ef6 | Yang Zhang | |
274 | 56038ef6 | Yang Zhang | alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]); |
275 | 56038ef6 | Yang Zhang | alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]); |
276 | 56038ef6 | Yang Zhang | alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]); |
277 | 00cf5774 | Paolo Bonzini | alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour); |
278 | 56038ef6 | Yang Zhang | |
279 | 56038ef6 | Yang Zhang | cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
280 | 56038ef6 | Yang Zhang | cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); |
281 | 56038ef6 | Yang Zhang | cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]); |
282 | 56038ef6 | Yang Zhang | cur_hour = convert_hour(s, cur_hour); |
283 | 56038ef6 | Yang Zhang | |
284 | 00cf5774 | Paolo Bonzini | if (alarm_hour == -1) { |
285 | 00cf5774 | Paolo Bonzini | alarm_hour = cur_hour; |
286 | 00cf5774 | Paolo Bonzini | if (alarm_min == -1) { |
287 | 00cf5774 | Paolo Bonzini | alarm_min = cur_min; |
288 | 00cf5774 | Paolo Bonzini | if (alarm_sec == -1) { |
289 | 00cf5774 | Paolo Bonzini | alarm_sec = cur_sec + 1;
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290 | 00cf5774 | Paolo Bonzini | } else if (cur_sec > alarm_sec) { |
291 | 00cf5774 | Paolo Bonzini | alarm_min++; |
292 | 00cf5774 | Paolo Bonzini | } |
293 | 00cf5774 | Paolo Bonzini | } else if (cur_min == alarm_min) { |
294 | 00cf5774 | Paolo Bonzini | if (alarm_sec == -1) { |
295 | 00cf5774 | Paolo Bonzini | alarm_sec = cur_sec + 1;
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296 | 00cf5774 | Paolo Bonzini | } else {
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297 | 00cf5774 | Paolo Bonzini | if (cur_sec > alarm_sec) {
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298 | 00cf5774 | Paolo Bonzini | alarm_hour++; |
299 | 00cf5774 | Paolo Bonzini | } |
300 | 00cf5774 | Paolo Bonzini | } |
301 | 00cf5774 | Paolo Bonzini | if (alarm_sec == SEC_PER_MIN) {
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302 | 00cf5774 | Paolo Bonzini | /* wrap to next hour, minutes is not in don't care mode */
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303 | 00cf5774 | Paolo Bonzini | alarm_sec = 0;
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304 | 00cf5774 | Paolo Bonzini | alarm_hour++; |
305 | 00cf5774 | Paolo Bonzini | } |
306 | 00cf5774 | Paolo Bonzini | } else if (cur_min > alarm_min) { |
307 | 00cf5774 | Paolo Bonzini | alarm_hour++; |
308 | 00cf5774 | Paolo Bonzini | } |
309 | 00cf5774 | Paolo Bonzini | } else if (cur_hour == alarm_hour) { |
310 | 00cf5774 | Paolo Bonzini | if (alarm_min == -1) { |
311 | 00cf5774 | Paolo Bonzini | alarm_min = cur_min; |
312 | 00cf5774 | Paolo Bonzini | if (alarm_sec == -1) { |
313 | 00cf5774 | Paolo Bonzini | alarm_sec = cur_sec + 1;
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314 | 00cf5774 | Paolo Bonzini | } else if (cur_sec > alarm_sec) { |
315 | 00cf5774 | Paolo Bonzini | alarm_min++; |
316 | 00cf5774 | Paolo Bonzini | } |
317 | 00cf5774 | Paolo Bonzini | |
318 | 00cf5774 | Paolo Bonzini | if (alarm_sec == SEC_PER_MIN) {
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319 | 00cf5774 | Paolo Bonzini | alarm_sec = 0;
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320 | 00cf5774 | Paolo Bonzini | alarm_min++; |
321 | 00cf5774 | Paolo Bonzini | } |
322 | 00cf5774 | Paolo Bonzini | /* wrap to next day, hour is not in don't care mode */
|
323 | 00cf5774 | Paolo Bonzini | alarm_min %= MIN_PER_HOUR; |
324 | 00cf5774 | Paolo Bonzini | } else if (cur_min == alarm_min) { |
325 | 00cf5774 | Paolo Bonzini | if (alarm_sec == -1) { |
326 | 00cf5774 | Paolo Bonzini | alarm_sec = cur_sec + 1;
|
327 | 00cf5774 | Paolo Bonzini | } |
328 | 00cf5774 | Paolo Bonzini | /* wrap to next day, hours+minutes not in don't care mode */
|
329 | 00cf5774 | Paolo Bonzini | alarm_sec %= SEC_PER_MIN; |
330 | 00cf5774 | Paolo Bonzini | } |
331 | 56038ef6 | Yang Zhang | } |
332 | 56038ef6 | Yang Zhang | |
333 | 00cf5774 | Paolo Bonzini | /* values that are still don't care fire at the next min/sec */
|
334 | 00cf5774 | Paolo Bonzini | if (alarm_min == -1) { |
335 | 00cf5774 | Paolo Bonzini | alarm_min = 0;
|
336 | 00cf5774 | Paolo Bonzini | } |
337 | 00cf5774 | Paolo Bonzini | if (alarm_sec == -1) { |
338 | 00cf5774 | Paolo Bonzini | alarm_sec = 0;
|
339 | 00cf5774 | Paolo Bonzini | } |
340 | 00cf5774 | Paolo Bonzini | |
341 | 00cf5774 | Paolo Bonzini | /* keep values in range */
|
342 | 00cf5774 | Paolo Bonzini | if (alarm_sec == SEC_PER_MIN) {
|
343 | 00cf5774 | Paolo Bonzini | alarm_sec = 0;
|
344 | 00cf5774 | Paolo Bonzini | alarm_min++; |
345 | 00cf5774 | Paolo Bonzini | } |
346 | 00cf5774 | Paolo Bonzini | if (alarm_min == MIN_PER_HOUR) {
|
347 | 00cf5774 | Paolo Bonzini | alarm_min = 0;
|
348 | 00cf5774 | Paolo Bonzini | alarm_hour++; |
349 | 00cf5774 | Paolo Bonzini | } |
350 | 00cf5774 | Paolo Bonzini | alarm_hour %= HOUR_PER_DAY; |
351 | 00cf5774 | Paolo Bonzini | |
352 | 00cf5774 | Paolo Bonzini | hour = alarm_hour - cur_hour; |
353 | 00cf5774 | Paolo Bonzini | min = hour * MIN_PER_HOUR + alarm_min - cur_min; |
354 | 00cf5774 | Paolo Bonzini | sec = min * SEC_PER_MIN + alarm_sec - cur_sec; |
355 | 00cf5774 | Paolo Bonzini | return sec <= 0 ? sec + SEC_PER_DAY : sec; |
356 | 56038ef6 | Yang Zhang | } |
357 | 56038ef6 | Yang Zhang | |
358 | 56038ef6 | Yang Zhang | static void rtc_update_timer(void *opaque) |
359 | 56038ef6 | Yang Zhang | { |
360 | 56038ef6 | Yang Zhang | RTCState *s = opaque; |
361 | 56038ef6 | Yang Zhang | int32_t irqs = REG_C_UF; |
362 | 56038ef6 | Yang Zhang | int32_t new_irqs; |
363 | 56038ef6 | Yang Zhang | |
364 | 41a9b8b2 | Yang Zhang | assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60); |
365 | 41a9b8b2 | Yang Zhang | |
366 | 56038ef6 | Yang Zhang | /* UIP might have been latched, update time and clear it. */
|
367 | 56038ef6 | Yang Zhang | rtc_update_time(s); |
368 | 56038ef6 | Yang Zhang | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
369 | 56038ef6 | Yang Zhang | |
370 | 00cf5774 | Paolo Bonzini | if (qemu_get_clock_ns(rtc_clock) >= s->next_alarm_time) {
|
371 | 56038ef6 | Yang Zhang | irqs |= REG_C_AF; |
372 | 56038ef6 | Yang Zhang | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
373 | 56038ef6 | Yang Zhang | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC); |
374 | 56038ef6 | Yang Zhang | } |
375 | 56038ef6 | Yang Zhang | } |
376 | 00cf5774 | Paolo Bonzini | |
377 | 56038ef6 | Yang Zhang | new_irqs = irqs & ~s->cmos_data[RTC_REG_C]; |
378 | 56038ef6 | Yang Zhang | s->cmos_data[RTC_REG_C] |= irqs; |
379 | 56038ef6 | Yang Zhang | if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) { |
380 | 56038ef6 | Yang Zhang | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
381 | 56038ef6 | Yang Zhang | qemu_irq_raise(s->irq); |
382 | 56038ef6 | Yang Zhang | } |
383 | 56038ef6 | Yang Zhang | check_update_timer(s); |
384 | 56038ef6 | Yang Zhang | } |
385 | 56038ef6 | Yang Zhang | |
386 | b41a2cd1 | bellard | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
387 | 80cabfad | bellard | { |
388 | b41a2cd1 | bellard | RTCState *s = opaque; |
389 | 80cabfad | bellard | |
390 | 80cabfad | bellard | if ((addr & 1) == 0) { |
391 | 80cabfad | bellard | s->cmos_index = data & 0x7f;
|
392 | 80cabfad | bellard | } else {
|
393 | ec51e364 | Isaku Yamahata | CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
|
394 | ec51e364 | Isaku Yamahata | s->cmos_index, data); |
395 | dff38e7b | bellard | switch(s->cmos_index) {
|
396 | 80cabfad | bellard | case RTC_SECONDS_ALARM:
|
397 | 80cabfad | bellard | case RTC_MINUTES_ALARM:
|
398 | 80cabfad | bellard | case RTC_HOURS_ALARM:
|
399 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
400 | 56038ef6 | Yang Zhang | check_update_timer(s); |
401 | 80cabfad | bellard | break;
|
402 | 80cabfad | bellard | case RTC_SECONDS:
|
403 | 80cabfad | bellard | case RTC_MINUTES:
|
404 | 80cabfad | bellard | case RTC_HOURS:
|
405 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
|
406 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
|
407 | 80cabfad | bellard | case RTC_MONTH:
|
408 | 80cabfad | bellard | case RTC_YEAR:
|
409 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
410 | dff38e7b | bellard | /* if in set mode, do not update the time */
|
411 | 41a9b8b2 | Yang Zhang | if (rtc_running(s)) {
|
412 | dff38e7b | bellard | rtc_set_time(s); |
413 | 56038ef6 | Yang Zhang | check_update_timer(s); |
414 | dff38e7b | bellard | } |
415 | 80cabfad | bellard | break;
|
416 | 80cabfad | bellard | case RTC_REG_A:
|
417 | 41a9b8b2 | Yang Zhang | if ((data & 0x60) == 0x60) { |
418 | 41a9b8b2 | Yang Zhang | if (rtc_running(s)) {
|
419 | 41a9b8b2 | Yang Zhang | rtc_update_time(s); |
420 | 41a9b8b2 | Yang Zhang | } |
421 | 41a9b8b2 | Yang Zhang | /* What happens to UIP when divider reset is enabled is
|
422 | 41a9b8b2 | Yang Zhang | * unclear from the datasheet. Shouldn't matter much
|
423 | 41a9b8b2 | Yang Zhang | * though.
|
424 | 41a9b8b2 | Yang Zhang | */
|
425 | 41a9b8b2 | Yang Zhang | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
426 | 41a9b8b2 | Yang Zhang | } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) && |
427 | 41a9b8b2 | Yang Zhang | (data & 0x70) <= 0x20) { |
428 | 41a9b8b2 | Yang Zhang | /* when the divider reset is removed, the first update cycle
|
429 | 41a9b8b2 | Yang Zhang | * begins one-half second later*/
|
430 | 41a9b8b2 | Yang Zhang | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
431 | 41a9b8b2 | Yang Zhang | s->offset = 500000000;
|
432 | 41a9b8b2 | Yang Zhang | rtc_set_time(s); |
433 | 41a9b8b2 | Yang Zhang | } |
434 | 41a9b8b2 | Yang Zhang | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
435 | 41a9b8b2 | Yang Zhang | } |
436 | dff38e7b | bellard | /* UIP bit is read only */
|
437 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
438 | dff38e7b | bellard | (s->cmos_data[RTC_REG_A] & REG_A_UIP); |
439 | c4c18e24 | Yang Zhang | periodic_timer_update(s, qemu_get_clock_ns(rtc_clock)); |
440 | 56038ef6 | Yang Zhang | check_update_timer(s); |
441 | dff38e7b | bellard | break;
|
442 | 80cabfad | bellard | case RTC_REG_B:
|
443 | dff38e7b | bellard | if (data & REG_B_SET) {
|
444 | 56038ef6 | Yang Zhang | /* update cmos to when the rtc was stopping */
|
445 | 41a9b8b2 | Yang Zhang | if (rtc_running(s)) {
|
446 | 56038ef6 | Yang Zhang | rtc_update_time(s); |
447 | 56038ef6 | Yang Zhang | } |
448 | dff38e7b | bellard | /* set mode: reset UIP mode */
|
449 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
450 | dff38e7b | bellard | data &= ~REG_B_UIE; |
451 | dff38e7b | bellard | } else {
|
452 | dff38e7b | bellard | /* if disabling set mode, update the time */
|
453 | 41a9b8b2 | Yang Zhang | if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
|
454 | 41a9b8b2 | Yang Zhang | (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) { |
455 | 56038ef6 | Yang Zhang | s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC; |
456 | dff38e7b | bellard | rtc_set_time(s); |
457 | dff38e7b | bellard | } |
458 | dff38e7b | bellard | } |
459 | 9324cc50 | Yang Zhang | /* if an interrupt flag is already set when the interrupt
|
460 | 9324cc50 | Yang Zhang | * becomes enabled, raise an interrupt immediately. */
|
461 | 9324cc50 | Yang Zhang | if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
|
462 | 9324cc50 | Yang Zhang | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
463 | 9324cc50 | Yang Zhang | qemu_irq_raise(s->irq); |
464 | 9324cc50 | Yang Zhang | } else {
|
465 | 9324cc50 | Yang Zhang | s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF; |
466 | 9324cc50 | Yang Zhang | qemu_irq_lower(s->irq); |
467 | 9324cc50 | Yang Zhang | } |
468 | bedc572e | Yang Zhang | s->cmos_data[RTC_REG_B] = data; |
469 | c4c18e24 | Yang Zhang | periodic_timer_update(s, qemu_get_clock_ns(rtc_clock)); |
470 | 56038ef6 | Yang Zhang | check_update_timer(s); |
471 | 80cabfad | bellard | break;
|
472 | 80cabfad | bellard | case RTC_REG_C:
|
473 | 80cabfad | bellard | case RTC_REG_D:
|
474 | 80cabfad | bellard | /* cannot write to them */
|
475 | 80cabfad | bellard | break;
|
476 | 80cabfad | bellard | default:
|
477 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
478 | 80cabfad | bellard | break;
|
479 | 80cabfad | bellard | } |
480 | 80cabfad | bellard | } |
481 | 80cabfad | bellard | } |
482 | 80cabfad | bellard | |
483 | abd0c6bd | Paul Brook | static inline int rtc_to_bcd(RTCState *s, int a) |
484 | 80cabfad | bellard | { |
485 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
|
486 | dff38e7b | bellard | return a;
|
487 | dff38e7b | bellard | } else {
|
488 | dff38e7b | bellard | return ((a / 10) << 4) | (a % 10); |
489 | dff38e7b | bellard | } |
490 | 80cabfad | bellard | } |
491 | 80cabfad | bellard | |
492 | abd0c6bd | Paul Brook | static inline int rtc_from_bcd(RTCState *s, int a) |
493 | 80cabfad | bellard | { |
494 | 00cf5774 | Paolo Bonzini | if ((a & 0xc0) == 0xc0) { |
495 | 00cf5774 | Paolo Bonzini | return -1; |
496 | 00cf5774 | Paolo Bonzini | } |
497 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
|
498 | dff38e7b | bellard | return a;
|
499 | dff38e7b | bellard | } else {
|
500 | dff38e7b | bellard | return ((a >> 4) * 10) + (a & 0x0f); |
501 | dff38e7b | bellard | } |
502 | dff38e7b | bellard | } |
503 | dff38e7b | bellard | |
504 | e2826cf4 | Paolo Bonzini | static void rtc_get_time(RTCState *s, struct tm *tm) |
505 | dff38e7b | bellard | { |
506 | abd0c6bd | Paul Brook | tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
507 | abd0c6bd | Paul Brook | tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); |
508 | abd0c6bd | Paul Brook | tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
|
509 | 3b89eb43 | Paolo Bonzini | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
|
510 | 3b89eb43 | Paolo Bonzini | tm->tm_hour %= 12;
|
511 | 3b89eb43 | Paolo Bonzini | if (s->cmos_data[RTC_HOURS] & 0x80) { |
512 | 3b89eb43 | Paolo Bonzini | tm->tm_hour += 12;
|
513 | 3b89eb43 | Paolo Bonzini | } |
514 | 43f493af | bellard | } |
515 | abd0c6bd | Paul Brook | tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
|
516 | abd0c6bd | Paul Brook | tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
517 | abd0c6bd | Paul Brook | tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
|
518 | abd0c6bd | Paul Brook | tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
|
519 | e2826cf4 | Paolo Bonzini | } |
520 | e2826cf4 | Paolo Bonzini | |
521 | e2826cf4 | Paolo Bonzini | static void rtc_set_time(RTCState *s) |
522 | e2826cf4 | Paolo Bonzini | { |
523 | e2826cf4 | Paolo Bonzini | struct tm tm;
|
524 | 80cd3478 | Luiz Capitulino | |
525 | e2826cf4 | Paolo Bonzini | rtc_get_time(s, &tm); |
526 | e2826cf4 | Paolo Bonzini | s->base_rtc = mktimegm(&tm); |
527 | 56038ef6 | Yang Zhang | s->last_update = qemu_get_clock_ns(rtc_clock); |
528 | 56038ef6 | Yang Zhang | |
529 | e2826cf4 | Paolo Bonzini | rtc_change_mon_event(&tm); |
530 | 43f493af | bellard | } |
531 | 43f493af | bellard | |
532 | e2826cf4 | Paolo Bonzini | static void rtc_set_cmos(RTCState *s, const struct tm *tm) |
533 | 43f493af | bellard | { |
534 | 42fc73a1 | aurel32 | int year;
|
535 | dff38e7b | bellard | |
536 | abd0c6bd | Paul Brook | s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
537 | abd0c6bd | Paul Brook | s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); |
538 | c29cd656 | Aurelien Jarno | if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
|
539 | 43f493af | bellard | /* 24 hour format */
|
540 | abd0c6bd | Paul Brook | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
541 | 43f493af | bellard | } else {
|
542 | 43f493af | bellard | /* 12 hour format */
|
543 | 3b89eb43 | Paolo Bonzini | int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12; |
544 | 3b89eb43 | Paolo Bonzini | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h); |
545 | 43f493af | bellard | if (tm->tm_hour >= 12) |
546 | 43f493af | bellard | s->cmos_data[RTC_HOURS] |= 0x80;
|
547 | 43f493af | bellard | } |
548 | abd0c6bd | Paul Brook | s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
|
549 | abd0c6bd | Paul Brook | s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); |
550 | abd0c6bd | Paul Brook | s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
|
551 | 42fc73a1 | aurel32 | year = (tm->tm_year - s->base_year) % 100;
|
552 | 42fc73a1 | aurel32 | if (year < 0) |
553 | 42fc73a1 | aurel32 | year += 100;
|
554 | abd0c6bd | Paul Brook | s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year); |
555 | 43f493af | bellard | } |
556 | 43f493af | bellard | |
557 | 56038ef6 | Yang Zhang | static void rtc_update_time(RTCState *s) |
558 | 43f493af | bellard | { |
559 | 56038ef6 | Yang Zhang | struct tm ret;
|
560 | 56038ef6 | Yang Zhang | time_t guest_sec; |
561 | 56038ef6 | Yang Zhang | int64_t guest_nsec; |
562 | 56038ef6 | Yang Zhang | |
563 | 56038ef6 | Yang Zhang | guest_nsec = get_guest_rtc_ns(s); |
564 | 56038ef6 | Yang Zhang | guest_sec = guest_nsec / NSEC_PER_SEC; |
565 | 56038ef6 | Yang Zhang | gmtime_r(&guest_sec, &ret); |
566 | e2826cf4 | Paolo Bonzini | rtc_set_cmos(s, &ret); |
567 | 43f493af | bellard | } |
568 | 43f493af | bellard | |
569 | 56038ef6 | Yang Zhang | static int update_in_progress(RTCState *s) |
570 | 43f493af | bellard | { |
571 | 56038ef6 | Yang Zhang | int64_t guest_nsec; |
572 | 3b46e624 | ths | |
573 | 41a9b8b2 | Yang Zhang | if (!rtc_running(s)) {
|
574 | 56038ef6 | Yang Zhang | return 0; |
575 | dff38e7b | bellard | } |
576 | 56038ef6 | Yang Zhang | if (qemu_timer_pending(s->update_timer)) {
|
577 | 56038ef6 | Yang Zhang | int64_t next_update_time = qemu_timer_expire_time_ns(s->update_timer); |
578 | 56038ef6 | Yang Zhang | /* Latch UIP until the timer expires. */
|
579 | 56038ef6 | Yang Zhang | if (qemu_get_clock_ns(rtc_clock) >= (next_update_time - UIP_HOLD_LENGTH)) {
|
580 | 56038ef6 | Yang Zhang | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
581 | 56038ef6 | Yang Zhang | return 1; |
582 | dff38e7b | bellard | } |
583 | dff38e7b | bellard | } |
584 | dff38e7b | bellard | |
585 | 56038ef6 | Yang Zhang | guest_nsec = get_guest_rtc_ns(s); |
586 | 56038ef6 | Yang Zhang | /* UIP bit will be set at last 244us of every second. */
|
587 | 56038ef6 | Yang Zhang | if ((guest_nsec % NSEC_PER_SEC) >= (NSEC_PER_SEC - UIP_HOLD_LENGTH)) {
|
588 | 56038ef6 | Yang Zhang | return 1; |
589 | dff38e7b | bellard | } |
590 | 56038ef6 | Yang Zhang | return 0; |
591 | 80cabfad | bellard | } |
592 | 80cabfad | bellard | |
593 | b41a2cd1 | bellard | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
594 | 80cabfad | bellard | { |
595 | b41a2cd1 | bellard | RTCState *s = opaque; |
596 | 80cabfad | bellard | int ret;
|
597 | 80cabfad | bellard | if ((addr & 1) == 0) { |
598 | 80cabfad | bellard | return 0xff; |
599 | 80cabfad | bellard | } else {
|
600 | 80cabfad | bellard | switch(s->cmos_index) {
|
601 | 80cabfad | bellard | case RTC_SECONDS:
|
602 | 80cabfad | bellard | case RTC_MINUTES:
|
603 | 80cabfad | bellard | case RTC_HOURS:
|
604 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
|
605 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
|
606 | 80cabfad | bellard | case RTC_MONTH:
|
607 | 80cabfad | bellard | case RTC_YEAR:
|
608 | 56038ef6 | Yang Zhang | /* if not in set mode, calibrate cmos before
|
609 | 56038ef6 | Yang Zhang | * reading*/
|
610 | 41a9b8b2 | Yang Zhang | if (rtc_running(s)) {
|
611 | 56038ef6 | Yang Zhang | rtc_update_time(s); |
612 | 56038ef6 | Yang Zhang | } |
613 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
614 | 80cabfad | bellard | break;
|
615 | 80cabfad | bellard | case RTC_REG_A:
|
616 | 56038ef6 | Yang Zhang | if (update_in_progress(s)) {
|
617 | 56038ef6 | Yang Zhang | s->cmos_data[s->cmos_index] |= REG_A_UIP; |
618 | 56038ef6 | Yang Zhang | } else {
|
619 | 56038ef6 | Yang Zhang | s->cmos_data[s->cmos_index] &= ~REG_A_UIP; |
620 | 56038ef6 | Yang Zhang | } |
621 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
622 | 80cabfad | bellard | break;
|
623 | 80cabfad | bellard | case RTC_REG_C:
|
624 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
625 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
626 | fbc15e27 | Paolo Bonzini | s->cmos_data[RTC_REG_C] = 0x00;
|
627 | 56038ef6 | Yang Zhang | if (ret & (REG_C_UF | REG_C_AF)) {
|
628 | 56038ef6 | Yang Zhang | check_update_timer(s); |
629 | 56038ef6 | Yang Zhang | } |
630 | ba32edab | Gleb Natapov | #ifdef TARGET_I386
|
631 | ba32edab | Gleb Natapov | if(s->irq_coalesced &&
|
632 | fbc15e27 | Paolo Bonzini | (s->cmos_data[RTC_REG_B] & REG_B_PIE) && |
633 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
634 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count++; |
635 | fbc15e27 | Paolo Bonzini | s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF; |
636 | ba32edab | Gleb Natapov | apic_reset_irq_delivered(); |
637 | aa6f63ff | Blue Swirl | DPRINTF_C("cmos: injecting on ack\n");
|
638 | ba32edab | Gleb Natapov | qemu_irq_raise(s->irq); |
639 | aa6f63ff | Blue Swirl | if (apic_get_irq_delivered()) {
|
640 | ba32edab | Gleb Natapov | s->irq_coalesced--; |
641 | aa6f63ff | Blue Swirl | DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
|
642 | aa6f63ff | Blue Swirl | s->irq_coalesced); |
643 | aa6f63ff | Blue Swirl | } |
644 | ba32edab | Gleb Natapov | } |
645 | ba32edab | Gleb Natapov | #endif
|
646 | 80cabfad | bellard | break;
|
647 | 80cabfad | bellard | default:
|
648 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
649 | 80cabfad | bellard | break;
|
650 | 80cabfad | bellard | } |
651 | ec51e364 | Isaku Yamahata | CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
|
652 | ec51e364 | Isaku Yamahata | s->cmos_index, ret); |
653 | 80cabfad | bellard | return ret;
|
654 | 80cabfad | bellard | } |
655 | 80cabfad | bellard | } |
656 | 80cabfad | bellard | |
657 | 1d914fa0 | Isaku Yamahata | void rtc_set_memory(ISADevice *dev, int addr, int val) |
658 | dff38e7b | bellard | { |
659 | 1d914fa0 | Isaku Yamahata | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
660 | dff38e7b | bellard | if (addr >= 0 && addr <= 127) |
661 | dff38e7b | bellard | s->cmos_data[addr] = val; |
662 | dff38e7b | bellard | } |
663 | dff38e7b | bellard | |
664 | ea55ffb3 | ths | /* PC cmos mappings */
|
665 | ea55ffb3 | ths | #define REG_IBM_CENTURY_BYTE 0x32 |
666 | ea55ffb3 | ths | #define REG_IBM_PS2_CENTURY_BYTE 0x37 |
667 | ea55ffb3 | ths | |
668 | 1d914fa0 | Isaku Yamahata | static void rtc_set_date_from_host(ISADevice *dev) |
669 | ea55ffb3 | ths | { |
670 | 1d914fa0 | Isaku Yamahata | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
671 | f6503059 | balrog | struct tm tm;
|
672 | ea55ffb3 | ths | int val;
|
673 | ea55ffb3 | ths | |
674 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
|
675 | 56038ef6 | Yang Zhang | |
676 | 56038ef6 | Yang Zhang | s->base_rtc = mktimegm(&tm); |
677 | 56038ef6 | Yang Zhang | s->last_update = qemu_get_clock_ns(rtc_clock); |
678 | 56038ef6 | Yang Zhang | s->offset = 0;
|
679 | 56038ef6 | Yang Zhang | |
680 | 56038ef6 | Yang Zhang | /* set the CMOS date */
|
681 | e2826cf4 | Paolo Bonzini | rtc_set_cmos(s, &tm); |
682 | ea55ffb3 | ths | |
683 | abd0c6bd | Paul Brook | val = rtc_to_bcd(s, (tm.tm_year / 100) + 19); |
684 | 1d914fa0 | Isaku Yamahata | rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val); |
685 | 1d914fa0 | Isaku Yamahata | rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val); |
686 | ea55ffb3 | ths | } |
687 | ea55ffb3 | ths | |
688 | 6b075b8a | Juan Quintela | static int rtc_post_load(void *opaque, int version_id) |
689 | 80cabfad | bellard | { |
690 | dff38e7b | bellard | RTCState *s = opaque; |
691 | dff38e7b | bellard | |
692 | 56038ef6 | Yang Zhang | if (version_id <= 2) { |
693 | 56038ef6 | Yang Zhang | rtc_set_time(s); |
694 | 56038ef6 | Yang Zhang | s->offset = 0;
|
695 | 56038ef6 | Yang Zhang | check_update_timer(s); |
696 | 56038ef6 | Yang Zhang | } |
697 | 56038ef6 | Yang Zhang | |
698 | 56038ef6 | Yang Zhang | #ifdef TARGET_I386
|
699 | 048c74c4 | Juan Quintela | if (version_id >= 2) { |
700 | 433acf0d | Jan Kiszka | if (s->lost_tick_policy == LOST_TICK_SLEW) {
|
701 | 048c74c4 | Juan Quintela | rtc_coalesced_timer_update(s); |
702 | 048c74c4 | Juan Quintela | } |
703 | 048c74c4 | Juan Quintela | } |
704 | 6b075b8a | Juan Quintela | #endif
|
705 | 73822ec8 | aliguori | return 0; |
706 | 73822ec8 | aliguori | } |
707 | 73822ec8 | aliguori | |
708 | 6b075b8a | Juan Quintela | static const VMStateDescription vmstate_rtc = { |
709 | 6b075b8a | Juan Quintela | .name = "mc146818rtc",
|
710 | 56038ef6 | Yang Zhang | .version_id = 3,
|
711 | 6b075b8a | Juan Quintela | .minimum_version_id = 1,
|
712 | 6b075b8a | Juan Quintela | .minimum_version_id_old = 1,
|
713 | 6b075b8a | Juan Quintela | .post_load = rtc_post_load, |
714 | 6b075b8a | Juan Quintela | .fields = (VMStateField []) { |
715 | 6b075b8a | Juan Quintela | VMSTATE_BUFFER(cmos_data, RTCState), |
716 | 6b075b8a | Juan Quintela | VMSTATE_UINT8(cmos_index, RTCState), |
717 | 89166459 | Paolo Bonzini | VMSTATE_UNUSED(7*4), |
718 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(periodic_timer, RTCState), |
719 | 6b075b8a | Juan Quintela | VMSTATE_INT64(next_periodic_time, RTCState), |
720 | 56038ef6 | Yang Zhang | VMSTATE_UNUSED(3*8), |
721 | 6b075b8a | Juan Quintela | VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
722 | 6b075b8a | Juan Quintela | VMSTATE_UINT32_V(period, RTCState, 2),
|
723 | 56038ef6 | Yang Zhang | VMSTATE_UINT64_V(base_rtc, RTCState, 3),
|
724 | 56038ef6 | Yang Zhang | VMSTATE_UINT64_V(last_update, RTCState, 3),
|
725 | 56038ef6 | Yang Zhang | VMSTATE_INT64_V(offset, RTCState, 3),
|
726 | 56038ef6 | Yang Zhang | VMSTATE_TIMER_V(update_timer, RTCState, 3),
|
727 | 00cf5774 | Paolo Bonzini | VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
|
728 | 6b075b8a | Juan Quintela | VMSTATE_END_OF_LIST() |
729 | 6b075b8a | Juan Quintela | } |
730 | 6b075b8a | Juan Quintela | }; |
731 | 6b075b8a | Juan Quintela | |
732 | 17604dac | Jan Kiszka | static void rtc_notify_clock_reset(Notifier *notifier, void *data) |
733 | 17604dac | Jan Kiszka | { |
734 | 17604dac | Jan Kiszka | RTCState *s = container_of(notifier, RTCState, clock_reset_notifier); |
735 | 17604dac | Jan Kiszka | int64_t now = *(int64_t *)data; |
736 | 17604dac | Jan Kiszka | |
737 | 17604dac | Jan Kiszka | rtc_set_date_from_host(&s->dev); |
738 | c4c18e24 | Yang Zhang | periodic_timer_update(s, now); |
739 | 56038ef6 | Yang Zhang | check_update_timer(s); |
740 | 17604dac | Jan Kiszka | #ifdef TARGET_I386
|
741 | 433acf0d | Jan Kiszka | if (s->lost_tick_policy == LOST_TICK_SLEW) {
|
742 | 17604dac | Jan Kiszka | rtc_coalesced_timer_update(s); |
743 | 17604dac | Jan Kiszka | } |
744 | 17604dac | Jan Kiszka | #endif
|
745 | 17604dac | Jan Kiszka | } |
746 | 17604dac | Jan Kiszka | |
747 | da98c8eb | Gerd Hoffmann | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
748 | da98c8eb | Gerd Hoffmann | BIOS will read it and start S3 resume at POST Entry */
|
749 | da98c8eb | Gerd Hoffmann | static void rtc_notify_suspend(Notifier *notifier, void *data) |
750 | da98c8eb | Gerd Hoffmann | { |
751 | da98c8eb | Gerd Hoffmann | RTCState *s = container_of(notifier, RTCState, suspend_notifier); |
752 | da98c8eb | Gerd Hoffmann | rtc_set_memory(&s->dev, 0xF, 0xFE); |
753 | da98c8eb | Gerd Hoffmann | } |
754 | da98c8eb | Gerd Hoffmann | |
755 | eeb7c03c | Gleb Natapov | static void rtc_reset(void *opaque) |
756 | eeb7c03c | Gleb Natapov | { |
757 | eeb7c03c | Gleb Natapov | RTCState *s = opaque; |
758 | eeb7c03c | Gleb Natapov | |
759 | 72716184 | Anthony Liguori | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
760 | 72716184 | Anthony Liguori | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); |
761 | 56038ef6 | Yang Zhang | check_update_timer(s); |
762 | eeb7c03c | Gleb Natapov | |
763 | 72716184 | Anthony Liguori | qemu_irq_lower(s->irq); |
764 | eeb7c03c | Gleb Natapov | |
765 | eeb7c03c | Gleb Natapov | #ifdef TARGET_I386
|
766 | 433acf0d | Jan Kiszka | if (s->lost_tick_policy == LOST_TICK_SLEW) {
|
767 | 433acf0d | Jan Kiszka | s->irq_coalesced = 0;
|
768 | 433acf0d | Jan Kiszka | } |
769 | eeb7c03c | Gleb Natapov | #endif
|
770 | eeb7c03c | Gleb Natapov | } |
771 | eeb7c03c | Gleb Natapov | |
772 | b2c5009b | Richard Henderson | static const MemoryRegionPortio cmos_portio[] = { |
773 | b2c5009b | Richard Henderson | {0, 2, 1, .read = cmos_ioport_read, .write = cmos_ioport_write }, |
774 | b2c5009b | Richard Henderson | PORTIO_END_OF_LIST(), |
775 | b2c5009b | Richard Henderson | }; |
776 | b2c5009b | Richard Henderson | |
777 | b2c5009b | Richard Henderson | static const MemoryRegionOps cmos_ops = { |
778 | b2c5009b | Richard Henderson | .old_portio = cmos_portio |
779 | b2c5009b | Richard Henderson | }; |
780 | b2c5009b | Richard Henderson | |
781 | 57c9fafe | Anthony Liguori | static void rtc_get_date(Object *obj, Visitor *v, void *opaque, |
782 | 18297050 | Anthony Liguori | const char *name, Error **errp) |
783 | 18297050 | Anthony Liguori | { |
784 | 57c9fafe | Anthony Liguori | ISADevice *isa = ISA_DEVICE(obj); |
785 | 18297050 | Anthony Liguori | RTCState *s = DO_UPCAST(RTCState, dev, isa); |
786 | e2826cf4 | Paolo Bonzini | struct tm current_tm;
|
787 | 18297050 | Anthony Liguori | |
788 | 56038ef6 | Yang Zhang | rtc_update_time(s); |
789 | e2826cf4 | Paolo Bonzini | rtc_get_time(s, ¤t_tm); |
790 | 18297050 | Anthony Liguori | visit_start_struct(v, NULL, "struct tm", name, 0, errp); |
791 | e2826cf4 | Paolo Bonzini | visit_type_int32(v, ¤t_tm.tm_year, "tm_year", errp);
|
792 | e2826cf4 | Paolo Bonzini | visit_type_int32(v, ¤t_tm.tm_mon, "tm_mon", errp);
|
793 | e2826cf4 | Paolo Bonzini | visit_type_int32(v, ¤t_tm.tm_mday, "tm_mday", errp);
|
794 | e2826cf4 | Paolo Bonzini | visit_type_int32(v, ¤t_tm.tm_hour, "tm_hour", errp);
|
795 | e2826cf4 | Paolo Bonzini | visit_type_int32(v, ¤t_tm.tm_min, "tm_min", errp);
|
796 | e2826cf4 | Paolo Bonzini | visit_type_int32(v, ¤t_tm.tm_sec, "tm_sec", errp);
|
797 | 18297050 | Anthony Liguori | visit_end_struct(v, errp); |
798 | 18297050 | Anthony Liguori | } |
799 | 18297050 | Anthony Liguori | |
800 | 32e0c826 | Gerd Hoffmann | static int rtc_initfn(ISADevice *dev) |
801 | dff38e7b | bellard | { |
802 | 32e0c826 | Gerd Hoffmann | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
803 | 32e0c826 | Gerd Hoffmann | int base = 0x70; |
804 | 80cabfad | bellard | |
805 | 80cabfad | bellard | s->cmos_data[RTC_REG_A] = 0x26;
|
806 | 80cabfad | bellard | s->cmos_data[RTC_REG_B] = 0x02;
|
807 | 80cabfad | bellard | s->cmos_data[RTC_REG_C] = 0x00;
|
808 | 80cabfad | bellard | s->cmos_data[RTC_REG_D] = 0x80;
|
809 | 80cabfad | bellard | |
810 | 1d914fa0 | Isaku Yamahata | rtc_set_date_from_host(dev); |
811 | ea55ffb3 | ths | |
812 | 93b66569 | aliguori | #ifdef TARGET_I386
|
813 | 433acf0d | Jan Kiszka | switch (s->lost_tick_policy) {
|
814 | 433acf0d | Jan Kiszka | case LOST_TICK_SLEW:
|
815 | 6875204c | Jan Kiszka | s->coalesced_timer = |
816 | 74475455 | Paolo Bonzini | qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s); |
817 | 433acf0d | Jan Kiszka | break;
|
818 | 433acf0d | Jan Kiszka | case LOST_TICK_DISCARD:
|
819 | 433acf0d | Jan Kiszka | break;
|
820 | 433acf0d | Jan Kiszka | default:
|
821 | 433acf0d | Jan Kiszka | return -EINVAL;
|
822 | 433acf0d | Jan Kiszka | } |
823 | 93b66569 | aliguori | #endif
|
824 | 433acf0d | Jan Kiszka | |
825 | 433acf0d | Jan Kiszka | s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s); |
826 | 56038ef6 | Yang Zhang | s->update_timer = qemu_new_timer_ns(rtc_clock, rtc_update_timer, s); |
827 | 56038ef6 | Yang Zhang | check_update_timer(s); |
828 | dff38e7b | bellard | |
829 | 17604dac | Jan Kiszka | s->clock_reset_notifier.notify = rtc_notify_clock_reset; |
830 | 17604dac | Jan Kiszka | qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier); |
831 | 17604dac | Jan Kiszka | |
832 | da98c8eb | Gerd Hoffmann | s->suspend_notifier.notify = rtc_notify_suspend; |
833 | da98c8eb | Gerd Hoffmann | qemu_register_suspend_notifier(&s->suspend_notifier); |
834 | da98c8eb | Gerd Hoffmann | |
835 | b2c5009b | Richard Henderson | memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2); |
836 | b2c5009b | Richard Henderson | isa_register_ioport(dev, &s->io, base); |
837 | dff38e7b | bellard | |
838 | 56038ef6 | Yang Zhang | qdev_set_legacy_instance_id(&dev->qdev, base, 3);
|
839 | a08d4367 | Jan Kiszka | qemu_register_reset(rtc_reset, s); |
840 | 18297050 | Anthony Liguori | |
841 | 57c9fafe | Anthony Liguori | object_property_add(OBJECT(s), "date", "struct tm", |
842 | 57c9fafe | Anthony Liguori | rtc_get_date, NULL, NULL, s, NULL); |
843 | 18297050 | Anthony Liguori | |
844 | 32e0c826 | Gerd Hoffmann | return 0; |
845 | 32e0c826 | Gerd Hoffmann | } |
846 | 32e0c826 | Gerd Hoffmann | |
847 | 48a18b3c | Hervé Poussineau | ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
|
848 | 32e0c826 | Gerd Hoffmann | { |
849 | 32e0c826 | Gerd Hoffmann | ISADevice *dev; |
850 | 7d932dfd | Jan Kiszka | RTCState *s; |
851 | eeb7c03c | Gleb Natapov | |
852 | 48a18b3c | Hervé Poussineau | dev = isa_create(bus, "mc146818rtc");
|
853 | 7d932dfd | Jan Kiszka | s = DO_UPCAST(RTCState, dev, dev); |
854 | 32e0c826 | Gerd Hoffmann | qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
855 | e23a1b33 | Markus Armbruster | qdev_init_nofail(&dev->qdev); |
856 | 7d932dfd | Jan Kiszka | if (intercept_irq) {
|
857 | 7d932dfd | Jan Kiszka | s->irq = intercept_irq; |
858 | 7d932dfd | Jan Kiszka | } else {
|
859 | 7d932dfd | Jan Kiszka | isa_init_irq(dev, &s->irq, RTC_ISA_IRQ); |
860 | 7d932dfd | Jan Kiszka | } |
861 | 1d914fa0 | Isaku Yamahata | return dev;
|
862 | 80cabfad | bellard | } |
863 | 80cabfad | bellard | |
864 | 39bffca2 | Anthony Liguori | static Property mc146818rtc_properties[] = {
|
865 | 39bffca2 | Anthony Liguori | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), |
866 | 39bffca2 | Anthony Liguori | DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
|
867 | 39bffca2 | Anthony Liguori | lost_tick_policy, LOST_TICK_DISCARD), |
868 | 39bffca2 | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
869 | 39bffca2 | Anthony Liguori | }; |
870 | 39bffca2 | Anthony Liguori | |
871 | 8f04ee08 | Anthony Liguori | static void rtc_class_initfn(ObjectClass *klass, void *data) |
872 | 8f04ee08 | Anthony Liguori | { |
873 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
874 | 8f04ee08 | Anthony Liguori | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
875 | 8f04ee08 | Anthony Liguori | ic->init = rtc_initfn; |
876 | 39bffca2 | Anthony Liguori | dc->no_user = 1;
|
877 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_rtc; |
878 | 39bffca2 | Anthony Liguori | dc->props = mc146818rtc_properties; |
879 | 8f04ee08 | Anthony Liguori | } |
880 | 8f04ee08 | Anthony Liguori | |
881 | 39bffca2 | Anthony Liguori | static TypeInfo mc146818rtc_info = {
|
882 | 39bffca2 | Anthony Liguori | .name = "mc146818rtc",
|
883 | 39bffca2 | Anthony Liguori | .parent = TYPE_ISA_DEVICE, |
884 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(RTCState),
|
885 | 39bffca2 | Anthony Liguori | .class_init = rtc_class_initfn, |
886 | 32e0c826 | Gerd Hoffmann | }; |
887 | 32e0c826 | Gerd Hoffmann | |
888 | 83f7d43a | Andreas Färber | static void mc146818rtc_register_types(void) |
889 | 100d9891 | aurel32 | { |
890 | 39bffca2 | Anthony Liguori | type_register_static(&mc146818rtc_info); |
891 | 100d9891 | aurel32 | } |
892 | 83f7d43a | Andreas Färber | |
893 | 83f7d43a | Andreas Färber | type_init(mc146818rtc_register_types) |