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root / target-arm @ 4c3b5a48

Name Size
cpu.h 16.8 kB
exec.h 1.6 kB
helper.c 74.6 kB
helpers.h 16.1 kB
iwmmxt_helper.c 24.7 kB
machine.c 6.6 kB
neon_helper.c 35.8 kB
op_addsub.h 1.8 kB
op_helper.c 10.5 kB
translate.c 316.4 kB

Latest revisions

# Date Author Comment
5642463a 01/18/2011 04:23 pm Peter Maydell

target-arm: Log instruction start in TCG code

Add support for logging the start of instructions in TCG
code debug dumps for ARM targets.

Signed-off-by: Peter Maydell <>
Signed-off-by: Edgar E. Iglesias <>
5df8bac1 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with VFP-enabled from TB flags, not CPUState

When translating code, whether the VFP unit is enabled for this TB
is stored in a bit in the TB flags. Use this rather than incorrectly
reading the FPEXC from the CPUState passed to translation....
69d1fc22 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with VFP len/stride from TB flags, not CPUState

When translating, the VFP vector length and stride for this TB are encoded
in the TB flags; the CPUState copies may be different and must not be used.

Signed-off-by: Peter Maydell <>...
7204ab88 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with Thumb state from TB flags, not CPUState

The Thumb/ARM state for the TB being translated should come from
the TB flags, not the CPUState.

Signed-off-by: Peter Maydell <>
Reviewed-by: Aurelien Jarno <>...
98eac7ca 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with condexec bits from TB flags, not CPUState

When translating, the condexec bits for the TB are in the TB flags;
the CPUState condexec bits may be different.

This patch fixes https://bugs.launchpad.net/bugs/604872 where we might
segfault if we took an exception in the middle of a TB with an IT...
05ed9a99 01/14/2011 09:39 pm Peter Maydell

target-arm: Set privileged bit in TB flags correctly for M profile

M profile ARM cores don't have a CPSR mode field. Set the bit in the
TB flags that indicates non-user mode correctly for these cores.

Signed-off-by: Peter Maydell <>...
61f74d6a 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with user-state from TB flags, not CPUState

When translating, get the user/priv state from the TB flags, not
the CPUState.

Signed-off-by: Peter Maydell <>
Reviewed-by: Aurelien Jarno <>
Signed-off-by: Aurelien Jarno <>
5de3a9d3 01/14/2011 09:39 pm Peter Maydell

target-arm: Remove redundant setting of IT bits before Thumb SWI

Remove a redundant call to gen_set_condexec() in the translation of Thumb
mode SWI. (SWI and WFI generate "exceptions" which happen after the
execution of the instruction, ie when PC and IT bits have updated....
bc4a0de0 01/14/2011 09:39 pm Peter Maydell

target-arm: Refactor translation of exception generating instructions

Create a new function which does the common sequence of gen_set_condexec,
gen_set_pc_im, gen_exception, set is_jmp to DISAS_JUMP.

Signed-off-by: Peter Maydell <>...
e12ce78d 01/14/2011 09:39 pm Peter Maydell

target-arm: Restore IT bits when resuming after an exception

We were not correctly restoring the IT bits when resuming execution
after taking an unexpected exception in the middle of an IT block.
Fix this by tracking them along with PC changes and restoring in...

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