root / hw / ppc_oldworld.c @ 4c823cff
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1 | 3cbee15b | j_mayer | /*
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2 | 3cbee15b | j_mayer | * QEMU OldWorld PowerMac (currently ~G3 B&W) hardware System Emulator
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3 | 3cbee15b | j_mayer | *
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4 | 3cbee15b | j_mayer | * Copyright (c) 2004-2007 Fabrice Bellard
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5 | 3cbee15b | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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6 | 3cbee15b | j_mayer | *
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7 | 3cbee15b | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 3cbee15b | j_mayer | * of this software and associated documentation files (the "Software"), to deal
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9 | 3cbee15b | j_mayer | * in the Software without restriction, including without limitation the rights
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10 | 3cbee15b | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 3cbee15b | j_mayer | * copies of the Software, and to permit persons to whom the Software is
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12 | 3cbee15b | j_mayer | * furnished to do so, subject to the following conditions:
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13 | 3cbee15b | j_mayer | *
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14 | 3cbee15b | j_mayer | * The above copyright notice and this permission notice shall be included in
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15 | 3cbee15b | j_mayer | * all copies or substantial portions of the Software.
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16 | 3cbee15b | j_mayer | *
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17 | 3cbee15b | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 3cbee15b | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 3cbee15b | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 3cbee15b | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 3cbee15b | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 3cbee15b | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 3cbee15b | j_mayer | * THE SOFTWARE.
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24 | 3cbee15b | j_mayer | */
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25 | 3cbee15b | j_mayer | #include "vl.h" |
26 | 3cbee15b | j_mayer | #include "ppc_mac.h" |
27 | 3cbee15b | j_mayer | |
28 | 3cbee15b | j_mayer | /* temporary frame buffer OSI calls for the video.x driver. The right
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29 | 3cbee15b | j_mayer | solution is to modify the driver to use VGA PCI I/Os */
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30 | 3cbee15b | j_mayer | /* XXX: to be removed. This is no way related to emulation */
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31 | 3cbee15b | j_mayer | static int vga_osi_call (CPUState *env) |
32 | 3cbee15b | j_mayer | { |
33 | 3cbee15b | j_mayer | static int vga_vbl_enabled; |
34 | 3cbee15b | j_mayer | int linesize;
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35 | 3cbee15b | j_mayer | |
36 | 3cbee15b | j_mayer | // printf("osi_call R5=%d\n", env->gpr[5]);
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37 | 3cbee15b | j_mayer | |
38 | 3cbee15b | j_mayer | /* same handler as PearPC, coming from the original MOL video
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39 | 3cbee15b | j_mayer | driver. */
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40 | 3cbee15b | j_mayer | switch(env->gpr[5]) { |
41 | 3cbee15b | j_mayer | case 4: |
42 | 3cbee15b | j_mayer | break;
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43 | 3cbee15b | j_mayer | case 28: /* set_vmode */ |
44 | 3cbee15b | j_mayer | if (env->gpr[6] != 1 || env->gpr[7] != 0) |
45 | 3cbee15b | j_mayer | env->gpr[3] = 1; |
46 | 3cbee15b | j_mayer | else
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47 | 3cbee15b | j_mayer | env->gpr[3] = 0; |
48 | 3cbee15b | j_mayer | break;
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49 | 3cbee15b | j_mayer | case 29: /* get_vmode_info */ |
50 | 3cbee15b | j_mayer | if (env->gpr[6] != 0) { |
51 | 3cbee15b | j_mayer | if (env->gpr[6] != 1 || env->gpr[7] != 0) { |
52 | 3cbee15b | j_mayer | env->gpr[3] = 1; |
53 | 3cbee15b | j_mayer | break;
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54 | 3cbee15b | j_mayer | } |
55 | 3cbee15b | j_mayer | } |
56 | 3cbee15b | j_mayer | env->gpr[3] = 0; |
57 | 3cbee15b | j_mayer | env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */ |
58 | 3cbee15b | j_mayer | env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */ |
59 | 3cbee15b | j_mayer | env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */ |
60 | 3cbee15b | j_mayer | env->gpr[7] = 85 << 16; /* refresh rate */ |
61 | 3cbee15b | j_mayer | env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */ |
62 | 3cbee15b | j_mayer | linesize = ((graphic_depth + 7) >> 3) * graphic_width; |
63 | 3cbee15b | j_mayer | linesize = (linesize + 3) & ~3; |
64 | 3cbee15b | j_mayer | env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */ |
65 | 3cbee15b | j_mayer | break;
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66 | 3cbee15b | j_mayer | case 31: /* set_video power */ |
67 | 3cbee15b | j_mayer | env->gpr[3] = 0; |
68 | 3cbee15b | j_mayer | break;
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69 | 3cbee15b | j_mayer | case 39: /* video_ctrl */ |
70 | 3cbee15b | j_mayer | if (env->gpr[6] == 0 || env->gpr[6] == 1) |
71 | 3cbee15b | j_mayer | vga_vbl_enabled = env->gpr[6];
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72 | 3cbee15b | j_mayer | env->gpr[3] = 0; |
73 | 3cbee15b | j_mayer | break;
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74 | 3cbee15b | j_mayer | case 47: |
75 | 3cbee15b | j_mayer | break;
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76 | 3cbee15b | j_mayer | case 59: /* set_color */ |
77 | 3cbee15b | j_mayer | /* R6 = index, R7 = RGB */
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78 | 3cbee15b | j_mayer | env->gpr[3] = 0; |
79 | 3cbee15b | j_mayer | break;
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80 | 3cbee15b | j_mayer | case 64: /* get color */ |
81 | 3cbee15b | j_mayer | /* R6 = index */
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82 | 3cbee15b | j_mayer | env->gpr[3] = 0; |
83 | 3cbee15b | j_mayer | break;
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84 | 3cbee15b | j_mayer | case 116: /* set hwcursor */ |
85 | 3cbee15b | j_mayer | /* R6 = x, R7 = y, R8 = visible, R9 = data */
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86 | 3cbee15b | j_mayer | break;
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87 | 3cbee15b | j_mayer | default:
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88 | 3cbee15b | j_mayer | fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]); |
89 | 3cbee15b | j_mayer | break;
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90 | 3cbee15b | j_mayer | } |
91 | 3cbee15b | j_mayer | |
92 | 3cbee15b | j_mayer | return 1; /* osi_call handled */ |
93 | 3cbee15b | j_mayer | } |
94 | 3cbee15b | j_mayer | |
95 | 3cbee15b | j_mayer | static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device, |
96 | 3cbee15b | j_mayer | DisplayState *ds, const char **fd_filename, |
97 | 3cbee15b | j_mayer | int snapshot,
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98 | 3cbee15b | j_mayer | const char *kernel_filename, |
99 | 3cbee15b | j_mayer | const char *kernel_cmdline, |
100 | 3cbee15b | j_mayer | const char *initrd_filename, |
101 | 3cbee15b | j_mayer | const char *cpu_model) |
102 | 3cbee15b | j_mayer | { |
103 | 3cbee15b | j_mayer | CPUState *env, *envs[MAX_CPUS]; |
104 | 3cbee15b | j_mayer | char buf[1024]; |
105 | 3cbee15b | j_mayer | qemu_irq *pic, **heathrow_irqs; |
106 | 3cbee15b | j_mayer | nvram_t nvram; |
107 | 3cbee15b | j_mayer | m48t59_t *m48t59; |
108 | 3cbee15b | j_mayer | int linux_boot, i;
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109 | 3cbee15b | j_mayer | unsigned long bios_offset, vga_bios_offset; |
110 | 3cbee15b | j_mayer | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
111 | 3cbee15b | j_mayer | ppc_def_t *def; |
112 | 3cbee15b | j_mayer | PCIBus *pci_bus; |
113 | 3cbee15b | j_mayer | MacIONVRAMState *nvr; |
114 | 3cbee15b | j_mayer | int vga_bios_size, bios_size;
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115 | 3cbee15b | j_mayer | qemu_irq *dummy_irq; |
116 | 3cbee15b | j_mayer | int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
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117 | 3cbee15b | j_mayer | |
118 | 3cbee15b | j_mayer | linux_boot = (kernel_filename != NULL);
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119 | 3cbee15b | j_mayer | |
120 | 3cbee15b | j_mayer | /* init CPUs */
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121 | 3cbee15b | j_mayer | env = cpu_init(); |
122 | 3cbee15b | j_mayer | if (cpu_model == NULL) |
123 | 3cbee15b | j_mayer | cpu_model = "default";
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124 | 3cbee15b | j_mayer | ppc_find_by_name(cpu_model, &def); |
125 | 3cbee15b | j_mayer | if (def == NULL) { |
126 | 3cbee15b | j_mayer | cpu_abort(env, "Unable to find PowerPC CPU definition\n");
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127 | 3cbee15b | j_mayer | } |
128 | 3cbee15b | j_mayer | for (i = 0; i < smp_cpus; i++) { |
129 | 3cbee15b | j_mayer | cpu_ppc_register(env, def); |
130 | 3cbee15b | j_mayer | cpu_ppc_reset(env); |
131 | 3cbee15b | j_mayer | /* Set time-base frequency to 100 Mhz */
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132 | 3cbee15b | j_mayer | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
133 | 3cbee15b | j_mayer | env->osi_call = vga_osi_call; |
134 | 3cbee15b | j_mayer | qemu_register_reset(&cpu_ppc_reset, env); |
135 | 3cbee15b | j_mayer | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
136 | 3cbee15b | j_mayer | envs[i] = env; |
137 | 3cbee15b | j_mayer | } |
138 | 4c823cff | j_mayer | if (env->nip < 0xFFF80000) { |
139 | 4c823cff | j_mayer | /* Special test for PowerPC 601:
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140 | 4c823cff | j_mayer | * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
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141 | 4c823cff | j_mayer | * But the NVRAM is located at 0xFFF04000...
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142 | 4c823cff | j_mayer | */
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143 | 4c823cff | j_mayer | cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
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144 | 4c823cff | j_mayer | } |
145 | 3cbee15b | j_mayer | |
146 | 3cbee15b | j_mayer | /* allocate RAM */
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147 | 3cbee15b | j_mayer | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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148 | 3cbee15b | j_mayer | |
149 | 3cbee15b | j_mayer | /* allocate and load BIOS */
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150 | 3cbee15b | j_mayer | bios_offset = ram_size + vga_ram_size; |
151 | 3cbee15b | j_mayer | if (bios_name == NULL) |
152 | 3cbee15b | j_mayer | bios_name = BIOS_FILENAME; |
153 | 3cbee15b | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
154 | 3cbee15b | j_mayer | bios_size = load_image(buf, phys_ram_base + bios_offset); |
155 | 3cbee15b | j_mayer | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
156 | 3cbee15b | j_mayer | cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
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157 | 3cbee15b | j_mayer | exit(1);
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158 | 3cbee15b | j_mayer | } |
159 | 3cbee15b | j_mayer | bios_size = (bios_size + 0xfff) & ~0xfff; |
160 | 4c823cff | j_mayer | if (bios_size > 0x00080000) { |
161 | 4c823cff | j_mayer | /* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
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162 | 4c823cff | j_mayer | cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
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163 | 4c823cff | j_mayer | } |
164 | 3cbee15b | j_mayer | cpu_register_physical_memory((uint32_t)(-bios_size), |
165 | 3cbee15b | j_mayer | bios_size, bios_offset | IO_MEM_ROM); |
166 | 3cbee15b | j_mayer | |
167 | 3cbee15b | j_mayer | /* allocate and load VGA BIOS */
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168 | 3cbee15b | j_mayer | vga_bios_offset = bios_offset + bios_size; |
169 | 3cbee15b | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
170 | 3cbee15b | j_mayer | vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
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171 | 3cbee15b | j_mayer | if (vga_bios_size < 0) { |
172 | 3cbee15b | j_mayer | /* if no bios is present, we can still work */
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173 | 3cbee15b | j_mayer | fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
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174 | 3cbee15b | j_mayer | vga_bios_size = 0;
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175 | 3cbee15b | j_mayer | } else {
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176 | 3cbee15b | j_mayer | /* set a specific header (XXX: find real Apple format for NDRV
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177 | 3cbee15b | j_mayer | drivers) */
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178 | 3cbee15b | j_mayer | phys_ram_base[vga_bios_offset] = 'N';
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179 | 3cbee15b | j_mayer | phys_ram_base[vga_bios_offset + 1] = 'D'; |
180 | 3cbee15b | j_mayer | phys_ram_base[vga_bios_offset + 2] = 'R'; |
181 | 3cbee15b | j_mayer | phys_ram_base[vga_bios_offset + 3] = 'V'; |
182 | 3cbee15b | j_mayer | cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
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183 | 3cbee15b | j_mayer | vga_bios_size); |
184 | 3cbee15b | j_mayer | vga_bios_size += 8;
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185 | 3cbee15b | j_mayer | } |
186 | 3cbee15b | j_mayer | vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff; |
187 | 3cbee15b | j_mayer | |
188 | 3cbee15b | j_mayer | if (linux_boot) {
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189 | 3cbee15b | j_mayer | kernel_base = KERNEL_LOAD_ADDR; |
190 | 3cbee15b | j_mayer | /* now we can load the kernel */
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191 | 3cbee15b | j_mayer | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
192 | 3cbee15b | j_mayer | if (kernel_size < 0) { |
193 | 3cbee15b | j_mayer | cpu_abort(env, "qemu: could not load kernel '%s'\n",
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194 | 3cbee15b | j_mayer | kernel_filename); |
195 | 3cbee15b | j_mayer | exit(1);
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196 | 3cbee15b | j_mayer | } |
197 | 3cbee15b | j_mayer | /* load initrd */
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198 | 3cbee15b | j_mayer | if (initrd_filename) {
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199 | 3cbee15b | j_mayer | initrd_base = INITRD_LOAD_ADDR; |
200 | 3cbee15b | j_mayer | initrd_size = load_image(initrd_filename, |
201 | 3cbee15b | j_mayer | phys_ram_base + initrd_base); |
202 | 3cbee15b | j_mayer | if (initrd_size < 0) { |
203 | 3cbee15b | j_mayer | cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
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204 | 3cbee15b | j_mayer | initrd_filename); |
205 | 3cbee15b | j_mayer | exit(1);
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206 | 3cbee15b | j_mayer | } |
207 | 3cbee15b | j_mayer | } else {
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208 | 3cbee15b | j_mayer | initrd_base = 0;
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209 | 3cbee15b | j_mayer | initrd_size = 0;
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210 | 3cbee15b | j_mayer | } |
211 | 3cbee15b | j_mayer | boot_device = 'm';
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212 | 3cbee15b | j_mayer | } else {
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213 | 3cbee15b | j_mayer | kernel_base = 0;
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214 | 3cbee15b | j_mayer | kernel_size = 0;
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215 | 3cbee15b | j_mayer | initrd_base = 0;
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216 | 3cbee15b | j_mayer | initrd_size = 0;
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217 | 3cbee15b | j_mayer | } |
218 | 3cbee15b | j_mayer | |
219 | 3cbee15b | j_mayer | isa_mem_base = 0x80000000;
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220 | 3cbee15b | j_mayer | |
221 | 3cbee15b | j_mayer | /* Register 2 MB of ISA IO space */
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222 | 3cbee15b | j_mayer | isa_mmio_init(0xfe000000, 0x00200000); |
223 | 3cbee15b | j_mayer | |
224 | 3cbee15b | j_mayer | /* XXX: we register only 1 output pin for heathrow PIC */
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225 | 3cbee15b | j_mayer | heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
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226 | 3cbee15b | j_mayer | heathrow_irqs[0] =
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227 | 3cbee15b | j_mayer | qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1); |
228 | 3cbee15b | j_mayer | /* Connect the heathrow PIC outputs to the 6xx bus */
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229 | 3cbee15b | j_mayer | for (i = 0; i < smp_cpus; i++) { |
230 | 3cbee15b | j_mayer | switch (PPC_INPUT(env)) {
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231 | 3cbee15b | j_mayer | case PPC_FLAGS_INPUT_6xx:
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232 | 3cbee15b | j_mayer | heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); |
233 | 3cbee15b | j_mayer | heathrow_irqs[i][0] =
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234 | 3cbee15b | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; |
235 | 3cbee15b | j_mayer | break;
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236 | 3cbee15b | j_mayer | default:
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237 | 3cbee15b | j_mayer | cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
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238 | 3cbee15b | j_mayer | exit(1);
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239 | 3cbee15b | j_mayer | } |
240 | 3cbee15b | j_mayer | } |
241 | 3cbee15b | j_mayer | |
242 | 3cbee15b | j_mayer | /* init basic PC hardware */
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243 | 3cbee15b | j_mayer | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
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244 | 3cbee15b | j_mayer | cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
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245 | 3cbee15b | j_mayer | exit(1);
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246 | 3cbee15b | j_mayer | } |
247 | 3cbee15b | j_mayer | pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
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248 | 3cbee15b | j_mayer | pci_bus = pci_grackle_init(0xfec00000, pic);
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249 | 3cbee15b | j_mayer | pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, |
250 | 3cbee15b | j_mayer | ram_size, vga_ram_size, |
251 | 3cbee15b | j_mayer | vga_bios_offset, vga_bios_size); |
252 | 3cbee15b | j_mayer | |
253 | 3cbee15b | j_mayer | /* XXX: suppress that */
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254 | 3cbee15b | j_mayer | dummy_irq = i8259_init(NULL);
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255 | 3cbee15b | j_mayer | |
256 | 3cbee15b | j_mayer | /* XXX: use Mac Serial port */
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257 | 3cbee15b | j_mayer | serial_init(0x3f8, dummy_irq[4], serial_hds[0]); |
258 | 3cbee15b | j_mayer | |
259 | 3cbee15b | j_mayer | for(i = 0; i < nb_nics; i++) { |
260 | 3cbee15b | j_mayer | if (!nd_table[i].model)
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261 | 3cbee15b | j_mayer | nd_table[i].model = "ne2k_pci";
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262 | 3cbee15b | j_mayer | pci_nic_init(pci_bus, &nd_table[i], -1);
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263 | 3cbee15b | j_mayer | } |
264 | 3cbee15b | j_mayer | |
265 | 3cbee15b | j_mayer | pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); |
266 | 3cbee15b | j_mayer | |
267 | 3cbee15b | j_mayer | /* cuda also initialize ADB */
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268 | 3cbee15b | j_mayer | cuda_init(&cuda_mem_index, pic[0x12]);
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269 | 3cbee15b | j_mayer | |
270 | 3cbee15b | j_mayer | adb_kbd_init(&adb_bus); |
271 | 3cbee15b | j_mayer | adb_mouse_init(&adb_bus); |
272 | 3cbee15b | j_mayer | |
273 | 3cbee15b | j_mayer | nvr = macio_nvram_init(&nvram_mem_index); |
274 | 3cbee15b | j_mayer | pmac_format_nvram_partition(nvr, 0x2000);
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275 | 3cbee15b | j_mayer | |
276 | 3cbee15b | j_mayer | dbdma_init(&dbdma_mem_index); |
277 | 3cbee15b | j_mayer | |
278 | 3cbee15b | j_mayer | macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index, |
279 | 3cbee15b | j_mayer | cuda_mem_index, nvram_mem_index, 0, NULL); |
280 | 3cbee15b | j_mayer | |
281 | 3cbee15b | j_mayer | if (usb_enabled) {
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282 | 3cbee15b | j_mayer | usb_ohci_init_pci(pci_bus, 3, -1); |
283 | 3cbee15b | j_mayer | } |
284 | 3cbee15b | j_mayer | |
285 | 3cbee15b | j_mayer | if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) |
286 | 3cbee15b | j_mayer | graphic_depth = 15;
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287 | 3cbee15b | j_mayer | |
288 | 3cbee15b | j_mayer | m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59); |
289 | 3cbee15b | j_mayer | nvram.opaque = m48t59; |
290 | 3cbee15b | j_mayer | nvram.read_fn = &m48t59_read; |
291 | 3cbee15b | j_mayer | nvram.write_fn = &m48t59_write; |
292 | 3cbee15b | j_mayer | PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size, boot_device,
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293 | 3cbee15b | j_mayer | kernel_base, kernel_size, |
294 | 3cbee15b | j_mayer | kernel_cmdline, |
295 | 3cbee15b | j_mayer | initrd_base, initrd_size, |
296 | 3cbee15b | j_mayer | /* XXX: need an option to load a NVRAM image */
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297 | 3cbee15b | j_mayer | 0,
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298 | 3cbee15b | j_mayer | graphic_width, graphic_height, graphic_depth); |
299 | 3cbee15b | j_mayer | /* No PCI init: the BIOS will do it */
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300 | 3cbee15b | j_mayer | |
301 | 3cbee15b | j_mayer | /* Special port to get debug messages from Open-Firmware */
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302 | 3cbee15b | j_mayer | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
303 | 3cbee15b | j_mayer | } |
304 | 3cbee15b | j_mayer | |
305 | 3cbee15b | j_mayer | QEMUMachine heathrow_machine = { |
306 | 3cbee15b | j_mayer | "g3bw",
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307 | 3cbee15b | j_mayer | "Heathrow based PowerMAC",
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308 | 3cbee15b | j_mayer | ppc_heathrow_init, |
309 | 3cbee15b | j_mayer | }; |